JPH0775017B2 - Memory access method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A memory access method of a system in which a plurality of data processing devices share access to a storage device, and an object of the present invention is to perform a process for a private area at high speed and efficiently. A comparison circuit that compares a lock byte, which is a part of data read from a predetermined area of the storage device and indicates whether the predetermined area is occupied, with comparison data supplied from the memory control device together with a specific request. A write control circuit for writing the write data supplied from the memory control device as a lock byte to the storage device together with a specific request in accordance with the comparison result of the comparison circuit, and providing the storage device with the write control circuit. Lock byte read from a predetermined area of the storage device by a specific request issued from The data including the data and the comparison result of the comparison circuit are supplied to the data processing device which issued the specific request, and the data fetch is performed simultaneously with the reference and rewriting of the lock byte.

[Industrial application field]

The present invention relates to a memory access method, and more particularly to a memory access method for a system in which a plurality of data processing devices share a storage device for access.

In a system in which multiple data processing devices such as a central processing unit (CPU) and channel processor (CHP) share the main memory (MSU), data can be accessed by multiple data processing devices accessing the same area of MUS at the same time. It is necessary to prevent it from being destroyed.

As a control method for this purpose, a method using a lock byte is generally used. That is, for each storage area to be occupied by the data processing device, a lock byte indicating whether or not this area is occupied is provided, and each data processing device refers to the lock byte before accessing this area to It is to confirm that the data processing device does not occupy this area.

For example, in the lock byte, each bit is associated with a single data processing device, and when the data processing device occupies the above area, the bit of the lock byte corresponding to the exclusive data processing device is set to 1 When the exclusive use of this area is completed, all bits of the lock byte are set to 0.

When using such a method, it is effective to refer to and rewrite the lock byte with a compare and swap (CS) instruction. This is data indicating that the lock byte contents are not occupied (all bits =
This is because, as compared with 0), two operations can be executed by one instruction, that is, if the data is not occupied, the data indicating the occupation by the own data processing device is written in the lock byte.

It is desired to perform the above-mentioned lock byte reference and rewrite processing at high speed.

[Conventional technology]

Usually, in order to realize the CS instruction, a special lock mechanism is required in the storage control unit (MCU) attached to the MSU, and the increase in the hardware amount of the MCU has been a problem.

As a solution to the increase in the amount of hardware, the present applicant has previously proposed, in Japanese Patent Application No. 62-62472, a memory access method in which a CS instruction is referenced and rewritten by an MSU.

FIG. 5 shows a block diagram of the above-mentioned conventional memory access type MSU.

MUS10 is divided into banks 11 _{1 to} 11 _n . Bank 1 ₁ ~ 1
In addition to the memory 12, each 1 _n includes a read control circuit 13, a write control circuit 14, and a comparator 15.

The CS instruction has three operands, comparison data is set in the first operand, an address is set in the second operand, and write data is set in the third operand.

When a CS request is issued by the CS instruction, pin 16
The address of the second operand of the CS instruction is supplied, and the read control circuit 13 reads the memory block of, for example, 8 bytes including the lock byte specified by the address from the memory 12 and supplies it to the comparator 15. The comparison data of the first operand (all bits are 0) is supplied to the terminal 17, and the comparator 15 outputs a condition indicating that the two match or do not match.
A code is generated, output from the terminal 18, and supplied to the write control circuit 14. When the write control circuit 14 is supplied with the condition code indicating the coincidence, the write data of the third operand coming from the terminal 19 (the value corresponding to the data processor which issued the CS instruction is 1)
The data, which replaces the lock byte of the memory block read in step 3, is written in the area specified by the address of the memory 12.

Execution of the above CS instruction is performed by the bank as shown in FIG. 6 (A).
It is performed with the bank priority of 11 ₁ . It should be noted that FIGS. 9B to 9C show the memory 12 and the comparator 13.
The respective operations are shown, and (D) to (F) in the figure respectively show the states of the comparison data, the write data, and the condition code.

In the conventional method, the bank priority of the bank is maintained while the CS instruction is executed. Since the MCU does not allow other data processing devices to access the bank with the bank priority, CS in the MCU is
There is no need to provide a lock mechanism dedicated to instructions.

[Problems to be solved by the invention]

When the data processing device needs the data in the area to be exclusively used by the MSU 10, it issues the fetch request shown in FIG. 7B following the CS request shown in FIG. 7A.

However, when the fetch request is issued, the bank priority of the bank including the lock byte is taken for the CS request as shown in FIG. 7C, and the memory by the CS request shown in FIG. The reading of the memory 12 by the fetch request is made to wait until the writing of 12 is completed.

Therefore, the fetch data is output at the timing shown in FIG. 9F, and the next process using the fetch data of the data processing device is executed at the timing shown in FIG. It should be noted that FIG. 8E shows the operation timing of the comparator 15.

Thus, there is a problem that the fetch request is kept waiting until the end of the CS request, and the processing for the private area is slow.

The present invention has been made in view of the above points, and a memory / memory capable of performing processing on a private area at high speed and efficiently.
The purpose is to provide an access method.

[Means for solving problems]

The memory access method of the present invention is a memory access method of a system in which a request for a plurality of data processing devices (21 to 23) to access a storage device (10) is controlled by a memory control device (24). A lock byte, which is a part of the data read from the predetermined area (30) of (10) and indicates whether the predetermined area (30) is occupied, and is supplied from the memory controller (24) together with a specific request. A comparison circuit (15) that compares the comparison data with the comparison data (15), and write data supplied from the memory control device (24) together with a specific request according to the comparison result of the comparison circuit (15) as a lock byte. ) Is provided in the storage device (10) and is written by a specific request issued from any of the plurality of data processing devices (21 to 23). A predetermined area of the device (3
Data (2) including lock byte read from 0)
5) and the comparison result (26) of the comparison circuit (15) are supplied to the data processing device that issued the specific request, and the data fetch is performed simultaneously with the reference and rewriting of the lock byte.

[Action]

In the system of the present invention, a predetermined area (3
0) is represented by a lock byte as to whether or not the data processing device (21-23) is occupied by any of the data processing devices (21-23).
When accessing, the lock byte is referenced and rewritten by a specific request.

Since the lock byte is a part of the predetermined area (30), the data including the lock byte read from the predetermined area (30) for the above reference and the comparison result of the comparison circuit (15) are locked. The data is supplied to the data processing device that issued the specific request at the same time as referring and rewriting the bytes.

Therefore, when the referenced lock byte matches the comparison data, the data processing device that has accessed the predetermined area (30) reads the read data from the predetermined area (30) before the reference and rewriting of the lock byte are completed. The next processing can be executed at high speed by using it, and only a single request needs to be issued, so the load on the data processing device (21 to 23) and the memory control device (24) is reduced, and the efficiency is improved. .

〔Example〕

FIG. 1 shows an MS to which the memory access method of the present invention is applied.
Figure 3 shows a block diagram of one embodiment of U. In the figure, those parts which are the same as those corresponding parts in FIG. 5 are designated by the same reference numerals.

The MCU 10 is divided into banks 11 _{1 to} 11 _n . Bank 11 ₁ ~
In addition to the memory 12, each of 11 _n includes a read control circuit 13, a write control circuit 14, and a comparator 15.

When a CS request or a CS & F request described later is issued, an address is supplied to the terminal 16, and the read control circuit 13 reads from the memory 12 a memory block 25 of, for example, 8 bytes including a lock byte whose address is specified. It is supplied to the comparator 15 and is output from the terminal 20. Comparison data (all bits are 0) is supplied to terminal 17,
The comparator 15 generates a condition code as a comparison result 26 representing the coincidence or non-coincidence of the two, outputs it from the terminal 18, and supplies it to the write control circuit 14. When the write control circuit 14 is supplied with the condition code indicating the coincidence, the write byte (a value corresponding to the data processing device is set to 1) which comes in from the terminal 19 reads the lock byte of the memory block. The replaced data is written in the area of the memory 12 designated by the address.

In the method of the present invention, a compare swap and fetch (CS & F) request is provided in addition to the CS request. The CS & F request is data indicating that the lock byte contents are not occupied (all bits =
0), if not occupied, the data indicating the occupation by the own data processing device is written in the lock byte, and the data block included in the lock byte read for the above comparison is read out of the memory. The following three operations are executed.

FIG. 2 shows a block diagram of a system to which the method of the present invention is applied. The CPUs 21, 22 and CHP 23 as data processing devices are connected to the MSU 10 via a memory control unit (MCU) 24, and the MSU 10 is shared by the CPUs 21, 22 and CHP 23. The MCU controls parallel requests to the banks of the MSU 10 from the CPUs 21 and 22 and the CHP 23, respectively, and prioritizes the requests to the banks.

For example, when the CPU 21 requests an I / O operation to the CHP 23, the CPU 21 sends a third data to a predetermined area in the MSU 10 via the MCU 24.
A 16-byte table (proprietary area) 30 as shown in the figure is set. The first 1 byte 30a of this table 30 is used as a lock byte, and the remaining 15 bytes 30b are the storage section 30b for delivery information.
It is said that.

The CPU 21 interrupts the CHP 23 and supplies the address of the table 30 to the CHP 23.

When the CHP23 receives an I / O operation request from the CPU21, the CPU2
Based on the address instructed from 1, MSU25 via MCU24
In order to access the table 30 of FIG. 4, a CS & F request is issued as shown in FIG. According to this CS & F request, the bank priority shown in FIG. 7B is taken, the memory 12 in the MUS 10 is read as shown in FIG. 7C, and the first 8 bytes of the table 30 are read at once.

The comparator 15 compares the lock byte 30a included in the table 30 with the comparison data as shown in FIG. 7D, and the contents of 8 bytes of the table 30 are also fetched data shown in FIG. Is supplied to the CHP 23 and stored in the buffer 23a in the CHP 23.

When the condition code of the comparator 15 indicates a match,
Data in which the lock byte of the read 8 bytes is replaced with the write data is written in the memory 12. After the lock byte is rewritten, the remaining 8 bytes of the table 30 are read from the memory 12, and these 8 bytes are CH
It is stored in the buffer 23a of P23.

When the condition code from the MSU 10 indicates a match, the CHP 23 uses the contents of the table 30 stored in the buffer 23a to execute the following processing as shown in FIG. 4 (F).

As described above, by using the CS & F request, the table 30 is generated at substantially the same timing as the condition code.
Since the fetch data from is stored in the buffer 23a, the CHP 23 can immediately shift to the execution of the processing requested by the CHU 21, and high-speed processing becomes possible.

In addition, the CHP23 only has to issue the CS & F request instead of the conventional two requests, the CS request and the fetch request, so that the load of the CHP23 is reduced and the load of the MCU24 that controls the request to the memory is reduced. , Efficiency is improved.

In the above embodiment, the main storage device 10 is described as being divided into banks 11 _{1 to} 11 _n , but regardless of this,
The main storage device 10 does not have to be divided into a plurality of banks. In this case, when the CS & F request is issued, the memory priority is taken instead of the bank priority, and access to the main storage device 10 by another data processing device is prohibited.

The memory block read from the memory 12 at one time is not limited to 8 bytes and may be any number of bytes.

〔The invention's effect〕

As described above, according to the memory access method of the present invention,
The processing of the data processing device with respect to the area occupied by the storage device is speeded up, the number of requests issued to the memory is reduced, and the efficiency of the data processing device and the memory control device is improved, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a main memory device applied to the memory access method of the present invention, FIG. 2 is a block diagram of an embodiment of a system to which the method of the present invention is applied, and FIG. FIG. 4 is a block diagram of an example of the main storage device applied to the conventional system, FIG. 5 is a block diagram of an example of the main storage device applied to the conventional system, and FIG. FIG. 7 is a diagram showing the operation timing of a request, and FIG. 7 is a diagram showing the operation timing of a conventional CS request and fetch request. In the figure, 10 is a main memory, 12 is a memory, 13 is a read control circuit, 14 is a write control circuit, 15 is a comparator, 21, 22 is a central processing unit, 23 is a channel processor, 24 is a memory control unit, 30 indicates a table.

Claims (1)

[Claims] 1. A memory access system for a system, wherein a plurality of data processing devices (21-23) access requests to a storage device (10) are controlled by a memory control device (24). A lock byte, which is a part of the data read from the predetermined area (30) and indicates whether the predetermined area (30) is occupied, and comparison data supplied from the memory control device (24) together with a specific request. And a write circuit supplied from the memory control device (24) together with the specific request as a lock byte according to a comparison result of the comparison circuit (15). A control circuit (14) for writing to the storage device (10) is provided in the storage device (10), and a predetermined request of the storage device is given by a specific request issued from any of the plurality of data processing devices (21 to 23). The band (30) data that includes a lock byte read from (25), and said comparator circuit (15) comparing the result of (26), fed to a data processing apparatus that issued the particular request,
At the same time as referring to and rewriting the lock byte,
A memory access method characterized by fetching.