JPS628245A - Virtual memory system - Google Patents

Abstract

PURPOSE:To eliminate the necessity to reduce a virtual space with adding a tag by constituting each different virtual space according to a data type represented by the tag. CONSTITUTION:A tag check part 530 discriminates the data type from the tag part 120 of a virtual address 110 inputted from a control part 510, and outputs a data type discriminating signal to the control part 510. The control part decides a process according to the data type discriminating signal. An address conversion part 540 judges whether a page represented at the virtual address 110 is existed or not at a main memory. When it is existed at the main memory 20, the part converts the virtual address 110 to an actual address 210, and when it is not, it outputs a page fault signal. The control part 510 transfers the page requested to access by the page fault signal from a secondary memory device 30 to the main memory 20 and allocates an RPN part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a virtual storage system, and particularly to a virtual storage system in a computer system that processes data with tags.

[Conventional technology]

Traditionally, computer systems have adopted a virtual memory method to execute programs in an address space larger than the real memory capacity, and the logical address space (virtual space) visible to the program is the real memory determined by the physical real memory capacity. It became possible to enlarge the address space (real space) (Hiroshi Muraoka - Author: Computer Architecture, Kindai Kagakusha, Computer Science University Course, p.
p.

77-90.1981).

On the other hand, in conventional general-purpose computers, there is no distinction between instructions and data, and the type of data is determined by the program that processes the data6.For example, whether the bit pattern of certain data represents a character or a numeric value is , differs depending on the logical meaning of the program processing the data. Therefore, in order to dynamically perform processing using data types, it is necessary to manage the data types using a program, which poses problems in terms of descriptive ability and performance.

Therefore, a tag architecture was devised that assigns logical meaning to the data itself by adding a tag representing the data type to the data (G).

J. Myers: Advances in C.
computer architecture, A
Willey-1nterscience pu
bli-cation+pp, 37-45.1978
).

(Problem to be solved by the invention) However, in order to add tags to conventional data formats, it is necessary to extend the word length of the computer, shorten the word length of the data without changing the word length of the computer, or One possible method is to add a tag indicating the data type to the address being pointed to, but the first and second methods are not compatible with conventional computers and require sharing of hardware resources, data, etc. The disadvantage is that it becomes difficult.

On the other hand, with the third method, if the sum of the virtual address of the virtual memory method and the bit length of the added tag is smaller than the word length of the conventional computer, there is not much problem, but due to the expansion of the virtual space, If the bit width of the address becomes large, tags cannot be added, and therefore, in order to add tags, the size of the virtual space must be limited, which is a drawback.

Means for Solving Problem C] The virtual storage system of the present invention includes a central processing unit that processes tagged data, a main memory that stores the data in real addresses, and 2 that stores the data in virtual addresses. It has a secondary storage device, and a plurality of virtual spaces configured differently on the secondary storage device depending on the data type represented by the tag.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 5 is a schematic block diagram showing an embodiment of the virtual storage system according to the present invention.

The central processing unit 10 that processes tagged data is connected to a main memory 20 that stores data in real addresses, and the main memory 20 is connected to a secondary storage device 230 that stores data in virtual addresses. The virtual space stored on the secondary storage device 30 and the real space stored on the main memory 20 are both divided into units called pages. Pages in the virtual space are processed by the central processing unit 1
0 is loaded into a page in real space as needed, and accessed from the central processing unit 10 using a real address.

Such virtual storage schemes are well known and will not be discussed in further detail here.

In the virtual storage system of the present invention, the virtual space is divided into a plurality of parts depending on the data type, as shown in FIG. This division unit is called a segment. If there are 2″ data types,
The virtual space is divided into 2'' segments. Each segment is further divided into the aforementioned page units.

FIG. 3 shows an example of the format of a virtual address for constructing a virtual space such as that shown in FIG. 2. This virtual address 110
The tag part 120, PID (PageI de
It is composed of three parts: an nLification part 130 and an offset part 140. Tag section 12
0 defines the data type of the data pointed to by the virtual address 110 and at the same time represents a segment number in the virtual space. The PID section 130 represents the page number within the segment indicated by the tag section 120. The offset section 140 represents address deviation within the page indicated by the PID section 130.

FIG. 4 shows the format of the real address converted corresponding to the virtual address 110 of FIG. The real address 210 is
RPN (Real Page Number) section 22
0 and an offset section 230. The RPN section 220 represents a page number in real space. The offset section 230 is the RPN section 220
This represents the address deviation within the page as shown by , and is the same as the offset section 140 in FIG.

On the other hand, the tag section 120 shown in FIG.
0 identifies the data type, and that information is used by the corpse to process the accessed data.

FIG. 1 shows an example of internal blocks of the central processing unit 10. As shown in FIG. A control unit 510 controls each block and is connected to each block via a data bus and a control path. The calculation unit 520 performs data calculation based on the data and control information input from the control unit 510. The tag check unit 530 identifies the data type from the tag unit 120 of the virtual address 110 input from the control unit 510. ,
A data type identification signal is output to control section 510. Control unit 5
10 determines processing for the data according to the data type identification signal detected from the tag check unit 530. The address conversion unit 540 determines whether the page indicated by the virtual address 110 input from the control unit 510 exists in the main memory 20. If it is in main memory 20,
The virtual address 110 is converted to a real address 210, and if the address does not exist in the main memory 20, a page fault signal is output to the control unit 510. When the control unit 510 detects a page fault signal from the address conversion unit 540, the control unit 510 transfers the page requested for access from the secondary storage device 30 to the main memory 20, and transfers the page to which the access request has been made from the secondary storage device 30 to the main memory 20.
The RPN section 220 shown in FIG. 4 is assigned in correspondence with the ID section 130.

Next, a process in which tagged data is actually calculated will be explained using a specific example. Here, a case is shown in which addition of integer data and floating point number data is executed. First, a virtual address (VA+) pointing to the first data to be calculated (assumed to be an integer X) is input to the tag check unit 530 to identify the data type.

In this case, the signal representing integer data < f ixnum
>0 is detected Next, the virtual address (VAz) indicating the second data to be calculated (assumed to be a floating point number Y) is also input to the tag check unit 530, and the signal <fltnum representing floating point number data is inputted to the tag check unit 530. > is detected.

The control unit 510 determines that the first data type identification signal<Hxnum
] and the second data type identification signal <fltnus>, it is recognized that they do not match, and in this case, it is decided to convert the first data to a floating point number. Therefore, in order to read the first data, the virtual address VA is input to the address conversion unit 540. Here, assuming that no page fault signal occurs, the virtual address V
Obtain the real address RA + for A + . The control unit 510 controls the main memory 2 according to the real address RAI.
The first data X is read from 0, and then the integer X is converted into a floating point number X'. floating point number X'
is temporarily stored, for example, in an internal register of the calculation unit 520. Next, the control unit 510 inputs the virtual address ■A2 to the address conversion unit 540 in order to read the second data, obtains the real address RA2 in the same manner as described above, and then reads the second data Y from the main memory 20. Read out. Finally, the control unit 510 instructs the arithmetic unit 520 to add the floating point number X′ stored in the internal register with the successive second data Y, and converts the calculation result Z into floating point data. Store it in an internal register or main memory 20.

What should be noted here is the virtual address VA.

Integer data X pointed to by and virtual address V A
When the floating point number data Y pointed to by t and the calculation result are stored in the main memory 20, Z means that they are stored in a separate segment in the virtual space. That is, each segment is occupied by data having one common data type. This means that even though tags are added to data, the virtual space can have the same size as when no tags are added.

〔Effect of the invention〕

As explained above, the present invention constructs different virtual spaces depending on the data type represented by the tag.
Adding tags has the effect of providing a virtual storage system that does not require reducing the size of the virtual space.

[Brief explanation of drawings]

Figure 1 is an internal block diagram of the central processing unit in the virtual storage system of the present invention, Figure 2 is a configuration diagram of the virtual space, Figure 3 is a diagram showing the format of virtual addresses, and Figure 4 is the format of real addresses. FIG. 5 is a block diagram showing the configuration of the virtual storage system of the present invention. In the figure, 10...Central processing unit, 20...Main memory, 30...Secondary storage device, 110...Virtual address, 120...Tag section, 130 ...P2O part, 140.230 ...Offset part, 210...
... real address, 220 ... RPN section, 510 ... control section, 520 ... calculation section, 530 ... tag check section, 540 ... address conversion section. 1st concave 2nd @

Claims (2)

[Claims] (1) A central processing unit that processes tagged data, a main memory that stores the data in real addresses, and a secondary storage device that stores the data in virtual addresses, each according to the data type represented by the tag. A virtual storage system comprising: a plurality of virtual spaces configured differently on the secondary storage device. (2) The central processing unit performs data calculations using a tag check means for identifying a data type by regarding a part of a virtual address pointing to data as a tag, and an address conversion means for converting a virtual address into a real address. 2. The virtual storage system according to claim 1, further comprising a calculation means and a control means for controlling each of said means.