JPS5960647A - Memory access control method - Google Patents

Abstract

PURPOSE:To reduce the operating time and improve the accessing speed to a memory by accessing the memory by using the content of an index register as an address signal and forming the next access address while the instruction is executed. CONSTITUTION:When, for example, an instruction for accessing #1 memory M is given and the #1 operand of the (2) is given as the offset value to be used for forming an address to be accessed in the next instruction, the memory M is accessed by using the content of an index register IDR as an address because an operand is set in the index register IDR in advance, #0 data of the (6) are read out after t2 and used for the #1 instruction. During the execution of the instruction, operation is performed by an arithmetic circuit ALU and the operated result is set in the index register IDR as the next address by the #1 set signal of the (4).

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention provides a processor having an index register that accesses the result of an operation between an offset value as an operand and the contents of the index register as a memory address when executing a memory access instruction. This paper relates to a memory access control method.

Prior Art and Problems In a processor that processes digital signals according to a certain algorithm, for example, analyzes and recognizes audio signals, access to the memory M is conventionally performed using the configuration shown only in the main part in FIG. It was something. That is, a certain value is set in advance in the index register IDR by a set signal set by an instruction, and when an instruction accesses the memory M, an offset value is given as an operand Op, and this offset value and the index register ID
The contents of R are subjected to calculations such as addition in the calculation circuit ALU, and the result of the calculation becomes the address of memory M.
Data DATA is read from.

FIG. 2 shows an example of a time chart, in which (al is an instruction, fb) is an operand, (C1 is an output signal of the arithmetic circuit, (dl is successive data in the memory), and #0. #1, #2, . . . indicate corresponding contents. When the offset value of #1 is given as an operand by the instruction #1 that accesses memory M, the arithmetic circuit ALU reads #l of tc+ in FIG. Outputs the calculation result.The output signal is used as an address to store the memory M
When access is performed, memory M is accessed as shown in Figure 2 (
#l data of di is output. tl is arithmetic circuit A
This is the time due to the operation of L U, and t2 is the memory access time °ζ, and data from the memory M is obtained after a time t l +t 2 after the operand Op is given. In order to increase the speed of such memory access operation, the calculation time tl of the calculation circuits AI and U must be increased.
Although it is necessary to shorten the memory access time t2,
Each has certain limits.

OBJECTS OF THE INVENTION An object of the present invention is to speed up memory access by first calculating and determining a memory address. Examples will be described in detail below.

Embodiment of the invention FIG. 3 is a block diagram of main parts of an embodiment of the invention.
Similarly to the figure, the gate circuits, various registers, arithmetic units, etc. of each part of the processor are omitted from illustration, and the same reference numerals as in FIG. 1 indicate the same parts. In the present invention, the arithmetic circuit A1. Intex register ID of operation result of U
R is set, and the contents of the index register IDR are used as the memory M address signal. When an instruction to set a certain value in the index register IDR is executed, the index register IDR is first cleared by the clear signal clr, and the operand Op and the contents of the index register IDR are set to 0 in the arithmetic circuit A.
When input to LJ and added by arithmetic circuit ALU,
Since it is added to 0, its output is the operand O
p, the operand Op is input to the index register IDR, and the operand OP is input to the index register IDR by the set signal set.
・To be done.

When an instruction is issued to access the memory M, the contents of the index register IDR become an address signal for the memory N4, and the memory M is accessed. On the other hand, the contents of the index register IDR and the offset value as the operan Fop are input to the arithmetic circuit ALU, and the arithmetic result is sent to the index register IDR as a set signal s.
Set by et. The offset value in this case is selected so that the address for accessing the memory M by the next instruction can be obtained.

FIG. 4 shows an example of a time chart of the embodiment of the present invention, in which (1) is an instruction, (2) is an operand, and (3) is a time chart.
) is the output signal of the arithmetic circuit ALU, (4) is the set signal,
(5) shows the contents of the index register IDR, and (6) shows the successive data in the memory. Also #O, #1. ...
The corresponding contents are shown in each case. Given an instruction to access memory M in #1, #1 in operan (2)]
is given as an offset value to form the address to be accessed by the next instruction. Since the operand has already been set to intex register IDR, memory M is accessed using its contents as an address. Then, at time t2f&, data #0 in (6) is read out and used for instruction #1. The arithmetic circuit ALU performs an arithmetic operation within this instruction execution time, and the address is set in the index register IDR as the next access address by the #1 set signal in (4). That is, since the calculation for the next instruction is performed at time t1 within the instruction execution time T, faster access is possible compared to the conventional example in which memory access is performed using the calculation result as an address.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention provides an index register I
The memory M is accessed using the contents of D R as an address signal, and the offset value and the contents of the index register are operated on to form the next access address within the execution time of the instruction. Since it is set according to the set signal, it is possible to shorten the calculation time and speed up memory access compared to the conventional case where the calculation result is used as the address signal at that point. It will be possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main part of the conventional example, FIG. 2 is a block diagram of the main part of the conventional example shown in FIG. Figure 1 shows a time chart 1 of an embodiment of the invention. A1. , U is a /1iiW circuit, IDR is an index readestor, M is a memory, op is an operand, set is a set signal, and clr is a clear signal. Tokusou Applicant Fujitsu Co., Ltd. Representative Patent Attorney Gobe Tamamushi and 3 others Figure 1 Or) Figure 3 Figure 2 Figure 4 T -11111Y-+7

Claims (1)

[Claims] In a memory access control method in a processor having an index register, an arithmetic circuit that performs an operation between an operand value and the contents of the index register;
Set the calculation result of the calculation circuit to cellar 1 by a signal,
1. A memory access control system, comprising: the index register that clears the set contents by a clear signal, and accesses the memory using the set contents of the index register as an address signal.