JPH05334074A - Microprocessor - Google Patents

Abstract

PURPOSE:To reduce the number of ineffectively used instruction memories and to decrease chip size and the number of chips in a microprocessor in which a horizontal type microprogram is employed. CONSTITUTION:For example, one word of the instruction memory 2 is constituted of 32 bits and 24 bits, and such selection that eight bits(32 bits-24 bits) are inputted from the instruction memory 2 at a multiplexer(MUX) 8 by a selection signal 11 from a selection signal output circuit 2a generated according to the value of a program counter(PC) 1, or no operation data(shown as (0) in figure) is inputted is performed. Therefore, it is possible to reduce the number of ineffectively used memories by constituting the instruction memory with plural bit length.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an instruction memory of a microprocessor which is used in a microprocessor and which employs a horizontal microprogram capable of simultaneously controlling a plurality of functions with one instruction.

[0002]

2. Description of the Related Art Microprocessor instruction formats are roughly classified into vertical type and horizontal type.

In the vertical type microprogram, the bit length of one word in the instruction memory is fixed at m bits, and one instruction requires one to a plurality of words of memory. By increasing the number of words that form one instruction, it is possible to execute complicated processing and increase the instruction set. This instruction format has an advantage that the invalid bits in one instruction can be reduced and the instruction memory can be effectively used. However, there is a problem that increasing the number of words increases the number of times of reading from the instruction memory and reduces the processing speed. Therefore, the practical maximum number of words for one instruction is limited. For example, μP
In the case of D70116 (made by NEC), it is 1 byte or more and 6 bytes or less.

In the horizontal microprogram, the bit length of one word in the instruction memory is fixed at n bits, and normally one word completes one instruction. One instruction is composed of operations, transfers, control fields, etc., and the bit length of one word is inevitably long. For example, in the case of μPD77230A (manufactured by NEC Corporation), one word consists of 32 bits. Since a plurality of operations are designated by one instruction, the program becomes slightly complicated, and knowledge of hardware specific to the microprocessor may be required in order to write an optimized program. However, obstacles related to program development have been improved as the development tools have become more sophisticated. Such a horizontal microprogram is suitable for speeding up because it can operate a plurality of fields independently and can easily decode and control an instruction for each field. However, even if there is a field that is not operated, one instruction is composed of the information of all fields, so there is a problem that an invalid bit often occurs during one instruction.

[0005]

In the microprocessor adopting the above-mentioned conventional horizontal type microprogram,
When designing an application program, all fields such as operation, transfer, and control fields in one instruction memory are not used, and some bits for operating one field may not be used effectively. There was a problem that could not be used effectively.

An object of the present invention is to provide a microprocessor capable of reducing the instruction memory that has not been effectively used in the conventional microprocessor adopting the horizontal microprogram by configuring the instruction memory with a plurality of bit lengths. To do.

[0007]

According to the present invention, an instruction memory for storing a horizontal microprogram for controlling a system, a program counter for designating a read address of the instruction memory, and a content of the instruction memory are decoded. In the microprocessor having an instruction decoder for controlling the operation of the processor, the instruction memory is composed of a one-word instruction memory having at least two kinds of bit lengths, and the instruction memory is configured according to the value of the program counter. It is characterized in that the decoder is provided with a selection means for instructing selection of whether to read data from the instruction memory or read data in which the field is a no-operation.

[0008]

In the instruction memory, the one-word instruction memory is composed of, for example, two kinds of bit length memories. Then, the instruction decoder selects whether to input the data for the bit of the difference between these two types of bit lengths from the instruction memory or to input the data "0" which makes the field no operation according to the instruction from the selection means. To do.

As a result, the instruction memory can determine the bit length of one word in conformity with the data, the memory capacity can be optimized, and the instruction memory can be reduced.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIGS. 3 (a) and 3 (b) are explanatory views showing an example of an instruction format thereof.

In the first embodiment, the program counter (P
C) 1, instruction memory 2, stack 3, instruction decoder 4 composed of a static circuit, interrupt detection circuit (INT) 5, stack pointer (SP) 6, multiplexer (MUX) 7, and main In the microprocessor provided with the bus 9, the instruction memory 2, which is a feature of the present invention, is a 1-word instruction memory having two or more bit lengths as shown in FIGS. 3 (a) and 3 (b). As a selection unit configured by a memory, the instruction decoder indicates whether to read the data from the instruction memory 2 or the data (“0”) that makes the field a no operation according to the value of the program counter (PC) 1. Of the selection signal output circuit (SG) 2a and the multiplexer (MUX) 8.

Next, the operation of the first embodiment will be described.

The program counter (PC) 1 is a register indicating the address of the instruction memory 2, and can perform an increment operation, rewriting by an instruction, saving data in the stack 3, and restoring data from the stack 3. The instruction memory 2 is a memory for storing a micro program, and outputs the content of the address designated by the program counter (PC) 1 to the instruction decoder 4. The stack 3 saves and restores the contents of the program counter (PC) 1 and the main bus 9
It is a register that can read and write data via, and write data is selected by a multiplexer (MUX) 7. The instruction decoder 4 decodes the microprogram and outputs a control signal to each unit in the microprocessor. The interrupt detection circuit (INT) 5 has an interrupt request signal 10
When the interrupt request signal 10 is detected by the circuit for detecting the
Set to 1. The stack pointer 6 is a counter capable of incrementing or decrementing the level of the stack 3.

One word of the instruction memory 2 has 32 bits and 2 bits.
When the instruction decoder 4 is composed of 4 bits and the instruction decoder 4 is composed of a static circuit, 8 bits (32 bits to 24 bits) are input from the instruction memory 2 or data for which the field is not operated (“0” in the figure). ) Is selected by the multiplexer (MUX) 8 which uses the value of the program counter (PC) 1 from the selection signal output circuit 2a as the selection signal 11.

For example, when the half of the instruction memory 2 is 32 bits and the rest is 24 bits, the memory capacity is
This is 87.5% compared to the case where the entire instruction memory 2 is composed of 32 bits.

FIG. 2 is a block diagram showing the second embodiment of the present invention, which is an example in which the instruction decoder 4 is constructed by a dynamic circuit. The input of the instruction decoder 4 is precharged to all the bits "1" once, and the output of the instruction memory 2 discharges the bit of "0", and then the decoding is started. In the case of the second embodiment, since the bit in which the memory cell does not exist retains "1", whether the data is input from the instruction memory 2 by setting the data for which the field is a no operation to "all 1". , The multiplexer (MUX) 8 of FIG. 1 for selecting whether to input data for which the field concerned is a no operation is unnecessary.

FIGS. 3A and 3B show examples of instruction formats of the microprocessor of the present invention. In this example, a 1-word instruction (FIG. 3A) including a calculation field 21, a control field 22, a transfer field (1) 23 and a transfer field (2) 24, and a calculation field 21, a control field 22 and a transfer field. 25
It includes two types of instructions having different word lengths from the one-word instruction (FIG. 3B).

Although two transfer fields are effectively used when performing complicated processing at high speed, one transfer field is often sufficient. Switching between these two formats is performed by a program counter (P
C) It is performed by changing the value of 1. In a region where two transfers are possible, it is possible to perform a process in which two transfers and one transfer coexist at high speed.

[0020]

As described above, the present invention has the effect of reducing the instruction memory that has not been effectively used by configuring the instruction memory with a plurality of bit lengths. For example, a microprocessor including an instruction memory can reduce the chip size, and the effect is particularly great when the instruction memory is composed of a read / write memory (RAM) having a large memory cell. Further, a microprocessor having an instruction memory externally has a great effect of reducing the number of memory chips.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing an example of an instruction format of a microprocessor of the present invention.

[Explanation of symbols]

 1 Program Counter (PC) 2 Instruction Memory 2a Selection Signal Output Circuit (SG) 3 Stack 4 Instruction Decoder 5 Interrupt Detection Circuit (INT) 6 Stack Pointer (SP) 7, 8 Multiplexer (MUX) 9 Main Bus 10 Interrupt Request Signal 11 Selection signal 21 Calculation field 22 Control field 23 Transfer field (1) 24 Transfer field (2) 25 Transfer field

Claims (1)

[Claims] 1. An instruction memory for storing a horizontal microprogram for controlling a system, a program counter for designating a read address of the instruction memory, and an instruction for decoding the contents of the instruction memory and controlling the operation of a processor. In the microprocessor including a decoder, the instruction memory includes a 1-word instruction memory including at least two kinds of bit length memories, and the instruction decoder stores data from the instruction memory according to a value of the program counter. A microprocessor having a selection means for instructing selection of whether to read data or to read data in which the field is a no-operation.