JPH0962504A - Instruction processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an instruction processor with which the length of instruction can be selected as needed and the execution time of instruction can be shortened. SOLUTION: An instruction memory part 10 is provided with a word length instruction memory area 11 for storing instruction codes equivalent to the number of data word length bits and an abbreviated instruction memory area 12 for storing instruction codes small in numbers than data word length bits. Based on an instruction address from an instruction executing part 31, an instruction length discriminating part 23 discriminates whether that instruction is an abbreviated instruction or not. When the discriminated result of the instruction length discriminating part 23 shows the abbreviated instruction, an instruction code extending part 22 inserts bits to the instruction codes inside the abbreviated instruction memory area and outputs them to the instruction executing part 31 as the instruction codes equivalent to the number of data word length bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction processing device in a computer for executing a program including an instruction set having a plurality of instruction lengths.

[0002]

2. Description of the Related Art Conventionally, RISC (Reduced Instruction Set)
Computer: A reduced instruction set computer type instruction processor that has (1) an instruction set consisting of only fixed length instructions that are the same as the data word length, and (2) fixed length instructions that are half the data word length. Either an instruction set consisting of only one or (3) an instruction set consisting of an instruction having the same data word length and an instruction having a half of the data word length.

[0003]

[Problems to be Solved by the Invention]
In (1), since the number of bits in the instruction is large, it is possible to specify many operations, many registers, allocate immediate data in a large range, and specify memory address values in a large range. It has the drawback of being large in size.

Further, in (2), since the instruction length is half that in (1), it is possible to make the object code size relatively small. However, operation specification, register specification,
Not only does the specified range of immediate data or the specified range of memory address values become smaller, which imposes a great limit on programming, and because of this restriction, the number of instructions in the object code increases, and the object code size does not decrease. There is a problem that the number of instruction execution steps increases.

On the other hand, (3) has an instruction set devised to compensate for the drawbacks of (1) and (2) above, and for instructions that give a complicated operation or give a large immediate value or memory address value, The instructions of type 1) and instructions that can be specified without requiring many bits have the advantage that the instructions of type 2 can be used in combination. However, in order to read out an instruction of multiple lengths, 2
In some cases, the number of times of instruction read access needs to be increased, which results in an increase in instruction read time, and in that the circuit in the instruction processing device becomes complicated for branch control and instruction decoding. However, there is a problem in that the instruction execution cycle time becomes long.

From such a background, it has been desired to realize an instruction processing device capable of selecting an instruction length as required and shortening an instruction execution time.

[0007]

In order to solve the above-mentioned problems, an instruction processing device according to a first aspect of the present invention specifies an arbitrary instruction address and receives an instruction code corresponding to the address. An instruction memory unit consisting of a word length instruction memory region for storing an instruction code equal to the number of bits of the data word length, an abridged instruction memory region for storing an instruction code of less than the number of bits of the data word length, and an instruction from the instruction execution unit An instruction length determination unit that determines whether the instruction is a shortened instruction or a word length instruction based on the address,
If the judgment result of the instruction length judgment unit is a shortened instruction,
An instruction to be output to the instruction execution unit as an instruction code equal to the data word length bit number by inserting the difference bit number between the instruction code in the shortened instruction memory area and the instruction code equal to the data word length bit number. And a code extension section.

According to the instruction processing device of the first aspect of the invention, the instruction length determination unit determines whether the instruction is a shortened instruction or a word length instruction based on the instruction address from the instruction execution unit. Is determined. The instruction code expansion unit determines the number of bits of the difference between the instruction code in the shortened instruction memory area and the instruction code equal to the number of bits of the data word when the determination result of the instruction length determination unit is the shortened instruction. Is inserted into the instruction execution unit as an instruction code equal to the data word length bit number.

In order to solve the above-mentioned problems, the instruction processing device of the second aspect of the present invention is the instruction processing device of the first aspect of the invention, in which the instruction is a shortened type instruction by comparison with a predetermined boundary address. It is characterized in that an instruction length judging unit for judging whether the instruction is a word length instruction is provided. With this configuration, the instruction length determination unit compares the instruction address from the instruction execution unit with the boundary address and determines whether the instruction is a shortened instruction or a word length instruction.

In order to solve the above-mentioned problems, the instruction processing apparatus of the third invention is the instruction processing apparatus of the first invention, in which the instruction is shortened by comparing a predetermined upper limit address and lower limit address. Or a word length instruction is provided. With this configuration, the instruction length determination unit compares the instruction address from the instruction execution unit with the upper limit address and the lower limit address, and determines whether the instruction is a shortened instruction or a word length instruction. .

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. << First Embodiment >> FIG. 1 is a block diagram showing a first embodiment of an instruction processing apparatus of the present invention. Prior to this explanation, an instruction format executed by the RISC type instruction processing apparatus will be explained.

FIG. 2 is an explanatory diagram of an instruction format executed by the RISC type instruction processing device. FIG. 2A shows an instruction format having the same instruction length (word length) as the data word length.
(B) shows an instruction format with an instruction length (half word length) that is half the data word length. 2A and 2B
In any instruction format, the instruction code is composed of an operation designation section, a destination operand designation section, a source 1 operand designation section, and a source 2 operand / immediate operand designation section. This instruction code takes the contents of the register specified by the source 1 operand and the register specified by the source 2 operand, or the immediate value itself specified by the immediate operand, as opposed to the instruction specified by the operation specification section. Specifies the operation of performing the specified process and storing the result in the register specified by the destination operand.

That is, when the operation designation is f, the destination operand register is dst, the content of the source 1 operand register is src1, the content of the source 2 operand register is src2, and the immediate operand is imm, f (src1, src2) → dst or
It means f (src1, imm) → dst.

Since the data word length is 32 bits here, a full set operation can be specified by using all the 32 bit fields in the word length instruction of (a). On the other hand, (b) is a halfword length instruction, and since each field of the instruction code is shorter than the word length instruction, only the operation can be specified within a limited range as compared with the word length instruction. That is, halfword length instructions are a subset of word length instructions.

In the illustrated example, in the word length instruction, the operation designation section is 8 bits, the destination operand designation section is 8 bits, and the source 1 operand designation section is 8 bits.
And the source 2 operand / immediate operand specification part is 8
In contrast to a bit, in a halfword length instruction, the operation specification part is 4 bits, the destination operand specification part is 4 bits, the source 1 operand specification part is 4 bits, and the source 2 operand / immediate operand specification part is 4 bits. Therefore, the operation designation is 256 → 16, the destination operand register number is 256 → 16, the source 1 operand register number is 256 → 16, and the source 2 operand register number is 256 → 16, or the immediate operand range is −128. It becomes -127->-8-7.
Therefore, with the halfword length instruction, the processing that can be designated by one instruction is greatly limited.

It is also conceivable to execute an instruction set including both the word length instruction of (a) and the half word length instruction of (b). In this case, an instruction requiring complicated designation is a word length instruction. The instructions that can be specified simply are halfword length instructions.

FIG. 3 is an explanatory view of storing a word length instruction / halfword length instruction mixed object code. Since the data word length is 32 bits, the word length instruction is 32 bits and the half word length is 16 bits. Further, the instruction read from the instruction memory once is 32 bits.
Since the object code includes a word length instruction and a halfword length instruction as shown in FIG. 3, the instruction code boundary is a 4-byte boundary (a byte address that is a multiple of 4) and a 2-byte boundary (a multiple of 2). Byte address). However, since the instruction reading is in units of 32 bits, the word length instruction may extend over two consecutive words. At this time, in order to read this word command, it is necessary to read the command twice, resulting in an increase in the command reading time. In particular, when the branch destination is a word instruction and the instruction is stored in this way, it becomes impossible to prefetch the instruction, which is a serious problem.

Therefore, in the present invention, a memory area for a word length instruction and a memory area for a shortened instruction shorter than the word length instruction are separately provided, and an instruction is issued from any one of the memory areas according to conditions. By taking out the instruction, the instruction length is selected as required and the instruction execution time is shortened.

FIG. 4 is an explanatory diagram of the format and instruction execution state of the word length instruction in the instruction set processed in the first embodiment. FIG. 5 is an explanatory diagram of a format of a short-form instruction and an instruction execution state in the instruction set processed in the first embodiment.

First, a description will be given of a state stored in an instruction memory described later, that is, a static state before the instruction is executed. In the present embodiment, the word length instruction is 32 bits and the shortened instruction is 21 bits. However, this is only an example in the present invention, and the word length instruction is M bits in the present invention.
When the shortened instruction is N bits, M and N are M> N
It is applicable to any value that satisfies

In both the instruction formats shown in FIGS. 4 and 5, as in the example described with reference to FIG. 2, the instruction code includes an operation designation section, a destination operand designation section, a source 1 operand designation section, and a source 2 operand / It consists of an immediate operand specification part. This instruction code inputs the contents of the register specified by the source 1 operand and the register specified by the source 2 operand or the immediate value itself specified by the immediate operand,
The operation specified by the operation specifying unit is performed on this, and the operation of storing the result in the register specified by the destination operand is specified. That is, the operation designation is f, the destination operand register is dst, and the source 1
When the content of the operand register is src1, the content of the source 2 operand register is src2, and the immediate operand is imm, f (src1, src2) → ds
It means t or f (src1, imm) → dst.

Since the format of FIG. 4 is a word length instruction, a full set operation can be specified by using all 32-bit fields. On the other hand, the format of FIG. 5 is a shortened type instruction, and since each field of the instruction code is shorter than the word length instruction, only the operation can be specified within a limited range as compared with the word length instruction.
That is, the short instruction is a subset of the word length instruction.

In the illustrated example, in the word length instruction, the operation designation section is 8 bits, the destination operand designation section is 6 bits, the source 1 operand designation section is 6 bits,
And source 2 operand / immediate operand specification part is 1
In contrast to 2 bits, in the short instruction, the operation specification part is 5 bits, the destination operand specification part is 4 bits, the source 1 operand specification part is 4 bits, and the source 2 operand / immediate operand specification part is 8 bits. Therefore, the operation designation is 256 → 32, the number of destination operand registers is 64 → 16, and the source 1
The number of operand registers is 64 → 16, and the number of source 2 operand registers is 64 → 16 (the source 2 operand designation field is 12 bits → 8 bits, but the register designation part is lower 6 bits → lower 4 bits) , Or the immediate operand range is -2048 to 20
47 → -128 to 127.

Therefore, the program using the word length instruction can be configured by using the full set of instructions, but the program using the abbreviated instruction uses only the instruction in the range satisfying the above restrictions. Need to be configured.

On the other hand, the instruction execution unit, which will be described later, does not have a function of distinguishing between the word length instruction and the abbreviated instruction, and all the instructions are word length instructions, that is, instructions that specify a full set operation. It consists only of the ability to execute code. Therefore, all the instructions given to the instruction execution unit need to have an instruction length of 32 bits. Therefore, in the present embodiment, when the instruction code read from the instruction memory is a word length instruction, it is sent to the instruction execution unit as it is, and when the instruction code read from the instruction memory is a shortened instruction, it is It has a function to insert a bit into and to convert a short instruction into a word length instruction. Specifically, a bit having a value of 0 is inserted into a shortened instruction and this is executed, and such a configuration will be described below with reference to FIG.

[Structure] In FIG. 1, the instruction processing device is
The instruction memory unit 10, the instruction code conversion unit 20, and the instruction execution unit 30 are included. The instruction memory unit 10 is composed of two areas, a word length instruction memory area 11 and a shortened instruction memory area 12. The word length instruction memory area 11 is a memory area for storing an instruction code equal to the data word length bit number, and the shortened instruction memory area 12 is a memory area for storing an instruction code smaller than the data word length bit number. Further, it is assumed that the word length instruction memory area 11 is connected to the outside of the LSI including the CPU, and the shortened instruction memory area 12 is connected to the inside of the LSI including the CPU. Therefore, a 32-bit word length instruction is read from the word length instruction memory area 11 and input to the LSI,
A 21-bit short instruction is read from the short instruction memory area 12 inside the LSI.

The word length instruction memory area 11 and the shortened instruction memory area 12 are arranged in different instruction address spaces. Therefore, whether the instruction code is read from the word length instruction memory area 11 or the shortened instruction memory area 12 is identified by the content of the instruction address output from the instruction execution unit 30.

In this embodiment, the instruction address is calculated in word length instructions. Therefore, regardless of whether the instruction to be read is a word length instruction in the word length instruction memory area 11 or a shortened instruction in the shortened instruction memory area 12, the instruction address is an address based on the size of the word length instruction. It is decided by calculation. In this embodiment, the instruction address is a byte address and has 21 bits, that is, 2 as the entire instruction address space.
It has a size of megabytes. Word length Instruction length is 32
Bits and abbreviated instruction length are 21 bits, but since instruction addresses are calculated in units of 32 bits as described above, the total is 2 megabytes of instruction address space regardless of word length instructions or abbreviated instructions. 5
Up to 12k (2 ¹⁹ ) instructions can be arranged.

The instruction code conversion unit 20 is a feature of the present invention and is an instruction length determination unit 21 and an instruction code expansion unit 2.
And 2. The instruction length determination unit 21 has a function of determining, based on the instruction address from the instruction execution unit 30, whether the instruction is a shortened instruction or a word length instruction. The instruction code extension unit 22 includes an instruction length determination unit 21.
If the result of the determination is that the instruction is a shortened instruction, the instruction code in the shortened instruction memory area 12 is expanded to a word length and output to the instruction execution unit 30 as an instruction code having a length equal to the word length instruction code. have.

FIG. 6 is a block diagram of the instruction length determination unit 21. The instruction length determination unit 21 uses the boundary address register 21a.
And a comparison circuit 21b. The boundary address register 21a is a register that holds the value of the instruction address boundary between the word length instruction memory area 11 and the shortened instruction memory area 12. Further, the comparison circuit 21b is composed of a subtraction circuit, and the boundary register 21a is converted from the input instruction address.
The input boundary address is subtracted, and if the subtraction result is negative, the shortened instruction flag is asserted and becomes "1".

FIG. 7 is a block diagram of the instruction code extension unit 22. The instruction code extension unit 22 is composed of a plurality of multiplexer circuits (mux). The number of these multiplexer circuits is (the number of bits of the word length instruction)-
It is equal to (the number of bits of the shortened instruction). Also,
The instruction code expansion unit 22 is configured such that an instruction code input is input to one of the multiplexer inputs and a ground level, that is, “0” is input to the other input, and the instruction length determination unit 21 is used as a selection signal for the multiplexer circuit.
The short instruction flag from is input. Each multiplexer circuit is configured to select each instruction code when the shortened instruction flag is "0" and select the ground level, that is, "0" when the shortened instruction flag is "1".

The output of the multiplexer circuit is output to the instruction executing section 30 as an extended instruction code. Then, as the selection signal for the multiplexer circuit,
The short instruction flag is input from the instruction length determination unit 21.

The instruction executing section 30 also includes an instruction memory section 1.
An arbitrary instruction address is designated with respect to 0, and the instruction code corresponding to the address is received from the instruction code conversion unit 20. As described above, two types of identification, that is, a word length instruction and a shortened instruction, are identified. There is no function to perform, and all the instructions are composed only of a word length instruction, that is, a function to execute an instruction code that specifies a full set of operations.

[Operation] As shown in FIG. 1, the instruction address is input from the instruction execution unit 30 to the instruction length determination unit 21. The instruction length determining unit 21 determines that the instruction address is the word length instruction memory area 11 and the shortened instruction memory area 12
The instruction length is determined by checking which of the two is shown. Here, when the instruction address indicates instruction reading from the shortened instruction memory area 12, that is, reading of the shortened instruction, the shortened instruction flag is asserted from the instruction length determination unit 21 and becomes “1”. When the shortened instruction flag is “1”, the instruction code expansion unit 22 expands the instruction code input from the shortened instruction memory area 12 and outputs it to the instruction execution unit 30. On the other hand, when the shortened instruction flag is “0”, the instruction code input from the word length instruction memory area 11 is output to the instruction execution unit 30 as it is.

The instruction length determination in the instruction length determination unit 21 is performed as follows. A boundary address between the word length instruction memory area 11 and the shortened instruction memory area 12 is set in the boundary address register 21a shown in FIG. In this embodiment, the address space of the shortened instruction memory area 12 is 0 to 2
²⁰ -1 bytes, the address space of the word length instruction memory area 11 as a 2 ^{20-2 21} -1, the boundary address and 2 ^20. That is, the instruction address (byte address) is 00 0000 0000 0000 0000 0000 0000 to 01 1111 1111 1111 1111 1111 (binary number), and the abbreviated instruction memory area 12 is arranged and the instruction address is 10 0000 0000 0000 0000 0000 0000 It is assumed that the word length instruction memory area 11 is arranged at 1111 1111 1111 1111 1111 (binary number). In this case, the boundary address is set to 10 0000 0000 0000 0000 0000 (binary number), and the start address of the word length instruction memory area 11 is set.

A boundary address is set in the boundary address register 21a by executing an instruction. Instruction execution unit 30
When a write command to the boundary address register 21a is executed at, the boundary address value to be set in the data bus is output, and the boundary address register write signal is asserted. As a result, the boundary address to be set is set in the boundary address register 21a. The boundary address register 21a is configured to be set to the maximum address, that is, 11 1111 1111 1111 1111 1111 (binary number) immediately after the power is turned on. Therefore, the program from immediately after the power is turned on to the setting of the boundary address in the boundary address register 21a needs to be stored in the short instruction memory area 12. In this case, the program needs to be composed of only the short instruction. is there.

The newly set boundary address becomes valid from the instruction immediately after the instruction set in the boundary address register 21a. The comparison circuit 21b includes the instruction execution unit 3
The boundary address set in the boundary address register 21a is subtracted from the instruction address input from 0. If the result is negative, (instruction address <boundary address)
It is recognized that the instruction address indicates the area of the shortened instruction memory area 12, and the shortened instruction flag is "1".
Asserted to. If the subtraction result is not negative, it is recognized that the instruction address indicates the area of the word length instruction memory area 11, and in this case, the shortened instruction flag is not asserted, that is, "0". Then, the shortened instruction flag is input to the instruction code expansion unit 22.

The instruction code expansion unit 22 operates based on the shortened instruction flag from the instruction length determination unit 21. For example, when the shortened instruction flag is “0”, it indicates that the instruction address is the word length instruction memory area 11 (external memory). Therefore, the word length instruction memory area 1
A word length instruction with a length of 1 to 32 bits is read. Then, the read instruction code is stored in the instruction code expansion unit 2
2 is input, but since the shortened flag is "0", the multiplexer circuit outputs the input instruction code as it is to the instruction execution unit 30. In addition, the instruction code [2
8 to 24], the instruction code [21 to 18], the instruction code [15 to 12], and the instruction code [7 to 0] are transmitted as they are as instruction codes from the bus line. Therefore, in this case, as shown in FIG. 4, the word-type instruction is directly transferred from the word length instruction memory area 11 to the instruction execution unit 30.
Will be sent to

On the other hand, when the shortened instruction flag is "1", the instruction address indicates the shortened instruction memory area 12, so that the shortened instruction having a length of 21 bits from the shortened instruction memory area 12 (internal memory). Is read. The read instruction code is input to the instruction code expansion unit 22.
The output of the word length instruction memory area 11 and the output of the shortened instruction memory area 12 are bus-coupled, and the bus line is driven from the memory designated by the instruction address for read access. Therefore, the shortened instruction memory area 1
Since the instruction read from 2 is a shortened instruction, only 21 bits of the 32-bit bus line are driven.

The shortened instruction memory area 12 includes instruction codes [28-24], instruction codes [21-18], among instruction codes [31-00] which are 32-bit bus lines.
Instruction code [15-12] and instruction code [7-
0] only. Remaining instruction code [31-2
9], instruction code [23-22], instruction code [17-
16], and the instruction codes [11-8] are not driven,
It is electrically in a high impedance state. These are input to the multiplexer circuit, but the input value is undefined. In this case, since the short instruction flag which is the selection signal of the multiplexer is "1", the undefined value input from the bus line is not selected, and the other input of the multiplexer, that is, the ground level, that is, " 0 "is selected and output.

Therefore, the 21-bit shortened instruction read from the shortened instruction memory area 12 is the instruction code [28
.About.24], instruction code [21-18], instruction code [15-12], and instruction code [7-0], drive the bus lines, pass through the instruction code expansion unit 22 as they are, and pass them to the instruction execution unit 30. Is output. "0" is given from the instruction code extension unit 22 to the remaining instruction codes [31 to 29], instruction code [23 to 22], instruction code [17 to 16], and instruction code [11 to 8]. It is output to the instruction execution unit 30. As a result, as shown in FIG. 5, the shortened type instruction is bit-inserted and is output with the same length as the standard length instruction.

[Effect] As described above, in the first embodiment, the word length instruction memory area 11 and the shortened instruction memory area 12 are provided, and for the instruction code read from the shortened instruction memory area 12, Since bits are inserted and output to the instruction execution unit 30 as a bit length equal to that of the word length instruction memory area 11, the following effects can be obtained.

That is, in the case of a program in which the object size is a problem, for example, a program to be stored in the LSI built-in memory, if it is composed of only the shortened instruction and stored in the shortened instruction memory area 12. , That problem can be solved. Further, in the case of a program in which the instruction execution time is a problem, that is, a program in which the number of instruction execution steps is desired to be minimized, if this is constituted by only the word length instruction and stored in the word length instruction memory area 11, You can solve the problem.

Further, by calculating the instruction address only with the size of the standard length instruction as a unit, it is possible to simplify the instruction address calculation and read the instruction code without fail with one instruction memory access. Further, since the instruction execution unit 30 only needs to execute the instruction having the word instruction length, the complexity of the internal circuit and control can be avoided.
Moreover, the instruction code expansion unit 22 can convert the short instruction into the word length instruction only by the operation of the one-stage multiplexer, so that the increase in the instruction execution cycle time can be minimized.

Moreover, the shortened instruction memory area 12 is RO
By storing it as M inside the LSI, it is invisible from the outside, so the number of bits of the shortened instruction memory area 12 can be set arbitrarily, and the minimum necessary configuration can be achieved. Cost and power consumption can be reduced.

That is, in the instruction processing device of the first embodiment,
In the same CPU, an object code is generated using a full set of instruction codes in order to configure a program that emphasizes instruction execution speed, and an instruction length is reduced in order to configure a program that emphasizes object code size. By making it possible to generate the object code using the instruction code of the specified subset, and by arranging the two kinds of object codes created by the instruction code in different places in the instruction address space, both can be read at the time of instruction reading. It is possible to identify and execute one application program including both.

The object code composed of the abbreviated instruction has an advantage that the object code size when it is stored in the ROM or the like built in the LSI can be reduced. Also,
In this case, the short instruction is embedded in the LSI,
The number of bits can be arbitrarily determined independently of the external bus size or the memory data width.

Further, when a source program is created by using a high-level language such as C language, an object code generating function composed of word length instructions and an object generating function composed of abbreviated instructions are prepared. A method of deciding which object code to adopt by compiling an actual source program and evaluating the object size is useful. According to this method, it is possible to create the internal ROM in the LSI after evaluating how much the object code size formed by the shortened instruction can be reduced for each application program.

<< Second Embodiment >> FIG. 8 is a block diagram of a second embodiment of the instruction processing apparatus of the present invention. The difference between the second embodiment and the configuration of the first embodiment is that instead of the boundary address register 21a in the instruction length determination unit 21 of the first embodiment, an upper limit address register in the instruction length determination unit 23,
And the upper limit address register is provided, and the register write signal from the instruction execution unit 31 is provided with the upper limit address register write signal and the lower limit address register write signal instead of the boundary address register write signal. Other than that, the configuration is the same as that of the first embodiment.

FIG. 9 is a block diagram of the instruction length determination unit 23 in the second embodiment. The instruction length determination unit 23 includes an upper limit address register 23a, a lower limit address register 23b, a comparison circuit (subtractor) 23c, a comparison circuit (subtractor) 23d, and a logical product circuit 23e.

In the second embodiment, the restriction on the arrangement of the word length instruction memory area 11 and the shortened instruction memory area 12 in the instruction address space described in the first embodiment is relaxed. In the first embodiment, “shortened instruction memory area 12 <word length instruction memory area 11” in the instruction address space
However, in the second embodiment, “first word length instruction memory area 11a <shortened instruction memory area 12 <second word length instruction memory” is used in the instruction address space. It is possible to make an arrangement such as the area 11b ". The first and second word length instruction memory areas 11a and 11b are memories for storing an object code composed of only standard length instructions, like the word length instruction memory area 11. Assuming that the first and second word length instruction memory areas 11a and 11b have arbitrary sizes, the upper limit address register 23a and the lower limit address register 3b can be set, so that the shortened instruction memory area 12 is set in the instruction address space, It can be placed at any place.

[Operation] The basic functions and operations of the second embodiment are the same as those of the first embodiment. In the second embodiment, the upper limit address register 23a and the lower limit address register 23b are provided in order to arrange the shortened instruction memory area 12 described in the first embodiment at any place in the instruction address space. A value larger than the upper limit address of the shortened instruction memory area 12 by 1 is set in the upper limit address register 23a,
The lower limit address of the shortened instruction memory area 12 is set in the lower limit address register 23b.

These address values are set by a program, the necessary write address values are output to the data bus input from the instruction execution section 31, and further, when the values are set in the upper limit address register 23a, the upper limit is set. When the address register write signal is asserted and the lower limit address register 23b is set to a value, the lower limit address register write signal is asserted.

Immediately after the power is turned on, the upper limit address register 2
The maximum value of the instruction address space is set in 3a, and the start address of the instruction address space is automatically set in the lower limit address register 23b by hardware. Therefore,
The program from immediately after the power is turned on to the setting of the boundary address in the upper limit address register 23a and the lower limit address register 23b needs to be stored in the short instruction memory area 12, and in this case, the program is composed of only the short instruction. There is a need.

The newly set boundary address is valid from the instruction immediately after the instruction set to the boundary address. The comparison circuit 23c subtracts the upper limit address set in the upper limit address register 23a from the instruction address input from the instruction execution unit 31. When the result is negative, "instruction address <upper limit address", the output of the comparison circuit 23c is asserted to "1", and is input to the AND circuit 23e. The comparison circuit 23d includes the instruction execution unit 3
The lower limit address set in the lower limit address register 23b is subtracted from the instruction address input from 1. When the result is 0 or a positive result, “lower limit address ≦ instruction address”, the output of the comparison circuit 23d is asserted to “1” and input to the AND circuit 23e. When the two inputs to the logical product circuit 23e are both "1", "lower limit address≤instruction address <upper limit address" is satisfied, and it is recognized that the instruction code access to the shortened instruction memory area 12 is made. It At this time, the short instruction flag is asserted to "1" and output from the AND circuit 23e.

If other than the above, it is recognized that the word length instruction memory area 11 is shown. In this case, the short instruction flag is not asserted, that is, "0". The shortened instruction flag is input to the instruction code expansion unit 22. Here, the operation of the instruction code extension unit 22 is the same as that of the first embodiment, and when the abbreviated instruction flag is "0", the instruction code (standard length instruction) that is input.
Is output as is, and the shortened instruction flag is "1".
In the case of, the bit is inserted (“0” is inserted) in the input instruction code (shortened instruction) and output.

[Effects] The effects of the first embodiment are also valid as they are in the second embodiment. Further, in the second embodiment, the restriction on the arrangement of the shortened instruction memory area 12 (which stores the object code composed of the shortened instruction) in the instruction address space in the first embodiment is relaxed, and the shortened embodiment is shortened. The restriction that the address of the short instruction memory area 12 <the address of the word length instruction memory area 11 is removed, and in the second embodiment, the short instruction memory area 12 can be arranged at any place in the instruction address space.

[0058]

As described above, according to the instruction processing apparatus of the first invention, the word length instruction memory area for storing the instruction code equal to the data word length bit number and the instruction code less than the data word length bit number. And a shortened instruction memory area for storing the data word length by inserting a difference bit number between the instruction code in the shortened instruction memory area and the instruction code equal to the data word length bit number. Since the instruction code equal to the number of bits is output to the instruction execution unit, the instruction length can be selected as necessary and the instruction execution time can be shortened.

According to the instruction processing device of the second invention,
Since it is determined whether the instruction is a short-form instruction or a word length instruction by comparison with a predetermined boundary address, in addition to the effect of the instruction processing device of the first invention, the configuration is The cost can be reduced easily and the power consumption can be reduced.

Further, according to the instruction reading apparatus of the third aspect of the present invention, it is determined whether the instruction is a shortened instruction or a word length instruction by comparing a predetermined upper limit address and a lower limit address. Therefore, the word length instruction memory area and the shortened instruction memory area can be arranged at arbitrary positions in the instruction address space.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of an instruction processing device of the present invention.

FIG. 2 is an explanatory diagram of an instruction format executed by a RISC type instruction processing device.

FIG. 3 is an explanatory diagram of storing a mixed object code of word length instruction / halfword length instruction.

FIG. 4 is an explanatory diagram of a format of a word length instruction and an instruction execution state in an instruction set processed by the instruction processing device according to the first exemplary embodiment of the present invention.

FIG. 5 is an explanatory diagram of a format of a short-form instruction and an instruction execution state in an instruction set processed in the first embodiment of the instruction processing device of the present invention.

FIG. 6 is a configuration diagram of an instruction length determination unit in the first embodiment of the instruction processing device of the present invention.

FIG. 7 is a configuration diagram of an instruction code extension unit in the instruction processing device of the present invention.

FIG. 8 is a configuration diagram of a second embodiment in the instruction processing device of the present invention.

FIG. 9 is a configuration diagram of an instruction length determination unit in the second embodiment of the instruction processing device of the present invention.

[Explanation of symbols]

 10 instruction memory unit 11 word length instruction memory region 12 shortened instruction memory region 21, 23 instruction length determination unit 22 instruction code expansion unit 30, 31 instruction execution unit

Claims (3)

[Claims] 1. An instruction execution unit for designating an arbitrary instruction address and receiving an instruction code corresponding to the address, a word length instruction memory area for storing an instruction code equal to the number of data word length bits, and a data word length. Based on the instruction address from the instruction execution unit, an instruction memory unit consisting of an abbreviated instruction memory area for storing an instruction code smaller than the number of bits, and whether the instruction is a abbreviated instruction or a word length instruction. A difference between the instruction length determining unit to determine and the instruction code in the shortened instruction memory area when the determination result of the instruction length determining unit is a shortened instruction and the instruction code equal to the data word length bit number. An instruction code expansion unit for outputting to the instruction execution unit an instruction code equal to the data word length bit number by inserting the number of bits of Processing equipment. 2. The instruction processing device according to claim 1, further comprising an instruction length determination unit that determines whether the instruction is a shortened instruction or a word length instruction by comparing with a predetermined boundary address. An instruction processing device characterized by being provided. 3. The instruction processing apparatus according to claim 1, wherein an instruction length for determining whether the instruction is a shortened instruction or a word length instruction by comparing a predetermined upper limit address and a lower limit address. An instruction processing device comprising a determination unit.