JP3058524B2 - Program control unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program controller for processing an interrupt and a return from an interrupt.

[0002]

2. Description of the Related Art In a conventional program processing device, a so-called bank system is used in which a program address is divided into two and managed in upper bits and lower bits in order to reduce the internal structure and speed up processing. In many cases, was adopted. For example, when the program address is 24 bits, the upper 8 bits of the program address are stored in the code bank register and the lower 16 bits are stored in the program counter. By doing so, it is only necessary to save the lower program address in the subroutine call in the same bank, so that the speed of execution and the saving area can be reduced.

FIGS. 4A and 4B are explanatory diagrams of a state of a stack at the time of an interrupt in a conventional program controller. FIG. 4A shows a state of a stack before an interrupt occurs, and FIG. 4B shows a state of a stack after an interrupt occurs. I have. When an interrupt occurs, all 24 bits of the return address (retCBR
, retPC) and the 16-bit program status word (retPSW) at the return destination are saved on the stack. Therefore, in the conventional program control device, when an interrupt occurs, three words of information are saved on the stack.

A conventional program processing apparatus generally employs a so-called interrupt table system in which the start address of an interrupt program is switched according to the type of interrupt as a system for determining a branch destination at the time of an interrupt. This interrupt table method has the advantage that it is only necessary to prepare an interrupt program according to the type of interrupt and to register its start address in the table, and it is not necessary to determine the type of interrupt by the program.

FIG. 5 is a diagram for explaining the contents of an interrupt table in a conventional program control device. The interrupt table is a 24-bit code bank number consisting of an 8-bit code bank number and a 16-bit in-bank address for each type of interrupt. Stores the start address of the interrupt program.
In such a conventional program control device, the interrupt program may be arranged in any bank and may be arranged anywhere in the bank, but the interrupt table contains an interrupt start address for each interrupt. Because the table must be prepared, the number of types of interrupts increases the size of the table.

[0006]

However, in the above-mentioned conventional program processing apparatus, since an interrupt may occur regardless of which bank the program is executed in, the program address is required to return to the original program. All the bits must be saved, and the amount of data saved at the time of an interrupt increases. Therefore, there is a problem that the interrupt response speed cannot be increased even though the program address is divided by the bank method.

In the above-mentioned conventional program processing device,
In order to be able to place an interrupt program in any bank, it is necessary to prepare all bits of the program address in the interrupt table, so there was a problem that the scale of the interrupt table increased as the types of interrupts increased . Further, even if the program being executed and the interrupt program are in the same bank, there is a waste in redesignating the bank, and there is a problem that the execution speed is reduced.

That is, in the above-described conventional program processing apparatus, processing such as a subroutine call in the same bank can be performed in the same manner as when there is no bank, but it is necessary to save and restore all bits of the program address at the time of interruption. Therefore, the processing speed is reduced and the area for saving the program address is increased. The present invention has been made in view of such circumstances, and has as its object to provide a program control device that can speed up interrupt processing and return processing from interrupts.

[0009]

Means for Solving the Problems The invention of claim 1 is a memorandum.
Program address consisting of upper and lower bits
A program controller that outputs an interrupt
Bank register that stores the bank number when performing
And the bank number for normal processing.
The two bank register and the second bank register during normal processing
The bank number stored in the
Is stored in the first bank register when an interrupt occurs.
Selector that outputs the bank number of the
And the program that outputs the lower bits of the program address
Program counter and a return address when an interrupt occurs.
Only the lower bits output by the program counter are scanned.
A retracting means for retracting to the tack .

According to a second aspect of the present invention, there is provided a program control device.
Is the interrupt status register in which information indicating the interrupt status is registered
And the memory has a plurality of interrupt programs.
And the value registered in the interrupt status register,
Decide which of the multiple interrupt programs to branch to
And an interrupt processing program for
Register is where the interrupt processing program is located.
Stores the bank number in the memory, the program
The counter is a program counter when an interrupt occurs.
The lower-order bit output by is saved by the saving means.
Program that indicates the start area of the interrupt processing program
The configuration is such that the lower bits of the address are set .

[0011]

According to the first aspect of the present invention, the first bank register is provided.
Stores the bank number when performing the interrupt processing. No.
The two-bank register indicates the bank number for normal processing.
Stored. The selector selects the second bank during normal processing.
The bank number stored in the
And outputs it, and stores it in the first bank register when an interrupt occurs
The output bank number is output as the upper bit. Step
The program counter uses the lower bits of the program address.
Is output. The evacuation means returns the return address when an interrupt occurs.
Lower bits output by the program counter as
Only save to the stack.

According to the second aspect of the present invention, the program system
The control device has an interrupt status register in which information indicating the interrupt status is registered.
A plurality of interrupt programs.
RAM and the value registered in the interrupt status register.
To which of the multiple interrupt programs to branch
And an interrupt processing program for determining
Bank registers are provided with interrupt processing programs
The bank number on the memory is stored, and the program
When an interrupt occurs, the ram counter
The lower bits output by the counter are saved by the saving means.
Program that indicates the start area of the interrupt processing program
The lower bit of the RAM address is set.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram of a program processing device according to an embodiment of the present invention.
, A second code bank register 2, a selector 3, a program counter 4,
OM5, general-purpose register 6, program state word 7,
Arithmetic unit 8, operand address register 9, RAM
10, an interrupt acceptance control unit 11, an interrupt status register 12, an overall control unit 13, and an internal data bus 14. The first code bank register 1 holds the upper 8 bits of the program address 24 bits, constantly supplies the contents to one input terminal of the selector 3, and stores the internal data based on a control signal from the overall control unit 13. Reading and writing of data are performed via the bus 14. The second code bank register 2 holds the upper 8 bits of the program address 24 bits, constantly supplies the contents to the other input terminal of the selector 3, and stores the internal data based on a control signal from the overall control unit 13. Reading and writing of data are performed via the bus 14. The selector 3 selects one of the data from the first code bank register 1 and the data from the second code bank register 2 based on the control signal from the overall control unit 13 and stores the selected data in the ROM 5. Supply. The program counter 4 holds the lower 16 bits of the program address 24 bits and always supplies the contents to the ROM 5. The ROM 5 stores an instruction, and the instruction is read by a 24-bit program address from the selector 3 and the program counter 4. General purpose register 6
Stores data and addresses necessary for executing the program. The program status word 7 stores a flag of a calculation result by the calculator 8 and an interrupt permission flag. Operand address register 9 stores the address of the data to be accessed. The RAM 10 stores data, and reads and writes data based on the contents of the operand address register 9. The interrupt acceptance control unit 11 accepts the generated interrupt and registers it in the interrupt status register 12. The overall control unit 13 controls the entire program control device.

FIG. 2 is an explanatory diagram of the state of the stack at the time of the interrupt. FIG.
(B) shows the state of the stack after the occurrence of the interrupt. When an interrupt occurs, the lower 16 bits (retPC) of the return destination program address and the 16-bit program status word (retPSW) at the return destination are saved on the stack.

FIG. 3 is an explanatory view of the arrangement of the interrupt processing program. The interrupt processing program is arranged at a fixed address in the bank. When an interrupt occurs, the process branches to an interrupt processing program at a fixed address, so that an interrupt table is unnecessary. In this interrupt processing program,
The contents of the interrupt status register 12 are read to determine which interrupt is requested, and the process branches to one of the interrupt programs A, B, and C according to the determination result.

Next, the operation will be described. Now, the state before the interrupt is generated, the first code bank register 1
Is selected by the selector 3, and the second code bank register 2 is cleared. Therefore, 24
The bit program address is formed by the upper 8 bits of the first code bank register 1 and the lower 16 bits of the program counter 4. The state of the stack is as shown in FIG. 2A, and the interrupt permission flag of the program state word 7 is set.

When an interrupt occurs in this state, the contents of the program counter 4 and the contents of the program state word 7 are respectively saved on the stack. Then, the selector 3 selects the second code bank register 2 based on a control signal from the overall control unit 13, and a fixed address determined by hardware is stored in the program counter 4. The fixed address is not particularly limited, and a value that can be easily created by hardware can be selected. When an interrupt occurs, a program address is created by the second code bank register 2 and the program counter 4. Since the contents of the second code bank register 2 before the interruption are zero, when the interruption occurs, the operation branches to the fixed address of the bank 0. There is an interrupt processing program at the branch destination. The interrupt processing program reads the contents of the interrupt status register 12, determines the type of interrupt, and branches to a program corresponding to the type of interrupt. When an interrupt occurs, the interrupt enable flag of the program state word 7 is cleared, and the next interrupt is not accepted until the enable flag is set by the program. Multiple interrupts that accept other interrupts during execution of an interrupt program can be made by setting an interrupt enable flag in the program status word 7 in the interrupt processing program. However, when an interrupt occurs again, the selector 3 returns to the state before the first interrupt occurs according to the control signal from the overall control unit 13, and selects the first code bank register 1. Therefore, before performing the multiple interrupts, the contents of the code bank register opposite to the currently used code bank register are saved by a program, and then the interrupt enable flag is set.

Returning from an interrupt is the reverse of the operation at the time of the interrupt. Program status word 7 saved on the stack
And the contents of the program counter 4 are returned to the respective registers, and the selector 3 selects the original first code bank register 1 according to the control signal from the overall control unit 13. In the above embodiment, the initial value of the second code bank register 2 is set to zero, but this value may be anything.
The bank in which the interrupt processing program is arranged can be set arbitrarily.

In the above embodiment, the number of code bank registers is two, but the number is not limited.

[0020]

According to the present invention as described above, according to the present invention, split
First bank that stores the bank number when performing the write process
Store the register and the bank number for normal processing
The second bank register and the second bank register during normal processing.
The bank number stored in the
And outputs it, and stores it in the first bank register when an interrupt occurs
Select the bank number that outputs the bank number
Output the lower bits of the program address.
Program counter and the return address when an interrupt occurs.
Only the lower bits output by the program counter
And a save means for saving the data on the stack. When an interrupt occurs, the only data to be saved is the contents of the program counter, and the branch destination at the time of the interrupt is fixed. Less,
The speed of the interrupt processing and the return processing from the interrupt can be favorably increased.

At the time of interruption, the first bank register
On the memory where the interrupt processing program is located
A bank number is stored in the program counter.
Is output by the program counter when an interrupt occurs.
After the lower bits to be input are saved by the saver,
Address indicating the start area of the embedded processing program
If the lower bits are set, the position where the interrupt processing program is arranged can be set by the value set before the occurrence of the interrupt, so that the same effect as that of the interrupt table method can be obtained by simple hardware.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a program processing device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a state of a stack at the time of interruption.

FIG. 3 is an explanatory diagram of an arrangement of an interrupt processing program.

FIG. 4 is an explanatory diagram of a state of a stack at the time of interruption in a conventional program control device.

FIG. 5 is an explanatory diagram of the contents of an interrupt table in a conventional program control device.

[Explanation of symbols]

 1 first code bank register 2 second code bank register 3 selector 4 program counter

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-3-53337 (JP, A) JP-A-60-57440 (JP, A) JP-A-62-135937 (JP, A) JP-A-4- 195562 (JP, A) JP-A-2-39239 (JP, A) JP-A-62-274434 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/46 G06F 13 / 24 G06F 9/40 G06F 9/42 G06F 9/36 G06F 12/06 G06F 12/02

Claims (3)

(57) [Claims] 1. A memory comprising: an upper bit and a lower bit;
Control device that outputs different program addresses
And the first bank storing the bank number for performing the interrupt processing.
Register and a second bank storing a bank number for performing normal processing.
And during normal processing, stored in the second bank register.
Outputs the bank number as upper bits, and when an interrupt occurs,
Upper bank number stored in the first bank register
Selector that outputs as bits and program that outputs lower bits of program address
Counter and program counter as return address when an interrupt occurs
Saves only the lower bits output by
A program control device, comprising: a retreat unit . 2. The program control device indicates an interrupt state.
The memory has an interrupt status register in which information is registered, and the memory stores a plurality of interrupt programs based on a plurality of interrupt programs and values registered in the interrupt status register.
Which interrupt program to branch to
And a first bank register is provided in the memory on which the interrupt processing program is arranged.
The program counter is output by the program counter when an interrupt occurs.
After the lower bits to be saved are saved by the saver,
Below the program address indicating the start area of the logical program
2. The program control device according to claim 1, wherein an order bit is set . (3) Multiple interrupt programs and multiple interrupt programs
Interrupt processing to determine which of the programs to branch to
Upper and lower bits in the memory where the
Program that outputs a program address consisting of
System control device, The van on the memory where the interrupt processing program is located
A first bank register that stores a bank number; The second bank storing the bank number for performing normal processing
Register, During normal processing, it is stored in the second bank register.
Outputs the bank number as upper bits, and when an interrupt occurs,
Upper bank number stored in the first bank register
A selector for outputting as a bit, The program that outputs the lower bits of the program address
A ram counter, When an interrupt occurs, the program counter is used as the return address.
Saves only the lower bits output by
With evacuation means, The program counter is: When an interrupt occurs, the
After the lower bits to be saved are saved by the saver,
Below the program address indicating the start area of the logical program
Bit is set A program characterized by comprising
Ram control device.