JPS59142791A - Access control system of stack memory - Google Patents

Abstract

PURPOSE:To perform fast stack access by setting up plural stack pointers and preventing the data saving of the stack pointers and a loading step from entering in a stack access time. CONSTITUTION:When a stack 14 is accessed, the number of a pointer in use is inputted as a signal APN to a control circuit 18, which performs the access by generating a selection signal SLT so that the pointer value coincident with the pointer number in a pointer register 22 is supplied as an address to the stack 14. The circuit 18 searches the data pointer number part of the register 22 on the basis of a signal PPN, and when a corresponding number is not found, a specific address given to the pointer of a main storage MS is accessed to read its contents, which are registered in the register 22 together with the pointer number. If there is another a pointer number and value beside the entry, they are saved in a specific area of the main storage MS. Those values are loaded and saved under the control of an LRU (Least Recenthy Used) circuit 20.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a stack memory access control system and is intended to enable high-speed stack access.

Prior Art and Problems Stacks are used in computers to temporarily store data read from main memory or to temporarily save register contents when an interrupt occurs. The stack is essentially a normal memory, with addresses and data storage areas, but there are some restrictions on how it can be accessed. That is, while a normal memory is accessed randomly, a stack uses a method of accessing sequentially, that is, using a certain address and then accessing that address by +1 or -l. FIG. 1 is a block diagram showing an outline of a conventional stack memory device, in which 10 is a central processing unit, 12 is a pointer register, 14 is a stack (memory), and 16 is a data register. When accessing the stack 14, the central processing unit 1
0 sends the address to register 12 through line 11,
The stack 14 is accessed according to the address, that is, the contents of the register 12, and in the case of reading, the data sequentially output from the stack 14 is taken into the central processing unit 10 via the register 16, and in the case of writing, the central processing unit 10 reads the data from the register 16.
The data sent to is written to the stack 14. The next access is often made by the central processing unit using line ρ2 to instruct the pointer register 12 to increment or decrement its contents, using an address that is one greater or one less than the above address. Accessing an address that is far apart from the ±°1 address is performed by the central processing unit 10 placing the address in a pointer register.

A stack access places an address into a pointer register or ±1s the contents of that register.

The conventional method is insufficient in terms of high-speed access to the stack because it requires a two-step operation in which the stack is accessed using the address of the register. Since the stack works in conjunction with the central processing unit, it is desired that it can be accessed as quickly as possible without interfering with the high-speed operation of the central processing unit.

OBJECTS OF THE INVENTION The present invention aims to enable even faster access to the stack, by preparing a plurality of stack pointers,
During a quick access by one stack pointer, the data of the other stack pointer is prefetched, and as soon as the stack access by that one stack pointer is completed, the data is prefetched by the other stack pointer. In this way, it is possible to save the data of the quick 7 pointer and prevent the load steering knob from entering the quick access time, thereby making quick access possible.

Structure of the Invention The present invention provides an access control method for a quick memory that is provided with a quick pointer and is accessed by an address stored in the pointer. When accessing the stack, a pointer number is specified and the stack address of the pointer with that number is output, and before the stack access, it is checked whether the pointer number is in the stack pointer.・
The feature is that the stack address of the pointer is retrieved from the external memory and stored in the stack pointer together with the pointer number.This will be explained in detail below with reference to an embodiment. do.

Embodiment of the Invention FIG. 2 shows an embodiment of the invention, in which 14 is the stack described above. The architecture has a control stack for saving status and a data disk for temporarily storing data, and this example assumes the latter. When the screen is for control, the pointer is called control pointer register C3R, and when it is for data, it is called data pointer register DSR. Here, data pointer register, data pointer, etc.) will be simply abbreviated as pointer as appropriate. Reference numeral 18 denotes a circuit for controlling the short memory device, which includes a data pointer register 22, LRIJ (Least Receiver
tly 1Jsed) circuit 20, multiplexer 24
, and controls the screen 14. The data pointer register 22 is called a pointer register in FIG. 1, but in the conventional system shown in FIG.
On the other hand, the method of the present invention shown in FIG. 2 is characterized in that there are a plurality of number of rotations. Assuming that this register is hypothetical, it is possible to use a memory that has high-speed write/read capability (memory, etc.), and there is no limit to the number of registers because it requires a plurality of strictly independent registers.

Since there are multiple pointer registers, this invention is useful! Numbers are given to distinguish between ten marks. The data 4 is the inter-number, and as shown in FIG. Of course, this is to be an identification code, and any other number or code may be used). The content of the pointer is an address, which is called the \deshima data pointer value. In FIG. 3, the pointer 01 points to address 2000, and M5's ! The ink points to address 6000 and dies. The following is based on G. this address 2000
．． 3000. . . . refers to the address of Suf.7ri14, and as shown in Figure 3, Data Pro Tsuk A
, B...... forcefully at"res 2000, 3000.
When stored in a predetermined memory area starting from . . . , pointers 1, 2 . . . to the data blocks A, B, . . . The pointer value of ... is 200
0,3000. It becomes... In this example, about 10 data blocks are stored in the stack 14, and pointers are assigned pointer numbers 1, 2, . . . corresponding to each data dub block. It is assumed that there are 10 points, and that the pointer register 22 can store 4 pointers. The control circuit 18 is connected to the main memory MS via a data bus DB, etc., and can access the main memory MS by sending a read/write instruction R/W and an address ADD. PPN and APN are input signals, the former indicating a brief fetch instruction data pointer number and the latter indicating a data pointer number to be accessed. SLT is a selection signal for the multiplexer 24, WE is a write enable signal for the stack 14, DI is input data, and Do is output data.

In this device, when the central processing unit accesses the stack 14, the number of the pointer used in the access is inputted to the control circuit 18 as the signal APN, and the control circuit 18 inputs the pointer number of the pointer in the pointer register 22 that matches the pointer number. A selection signal SL'r for the multiplexer 24 is generated so that the value is applied to the stack 14 as an address, thus performing stack access. The control circuit 18 also searches the data pointer number section of the pointer register 22 based on the signal PPN indicating the number of the data boink to be briefetched, checks whether or not the pointer number instructed to be briefetched exists, and determines whether or not it exists. However, if it does not exist, a predetermined address given to the pointer (number) in the main memory MS is accessed and its contents, that is, the value of the pointer is read. This value is registered in the pointer register 22 together with the pointer number. If there are other data pointer numbers and values in the entry of the pointer register 22 to which this registration is made, these are saved in a predetermined area of the main memory MS given to the pointer. Load these data pointer numbers and values,
The LRU circuit 20 manages the entries to be saved.
This is an algorithm that places the most recently used pointer first, so newly prefetched pointer numbers and values are stored in the oldest pointer number and value entries by freeing them.

A pointer refetch is performed during a stack access at a pointer. It is clear what the next pointer is by looking at the contents of the program, so that the central processing unit can send the signal PPN indicating the briefetch instruction data pointer number to the control circuit 18. Specifically, prefetching is performed by a microprogram. If the next pointer is prepared in the pointer register 22 during stack access, the selection signal SLT allows the multiplexer 2 to
4, the next pointer on the stack 14 can be accessed, and at the time of access by the next pointer, the pointer value of the next pointer is loaded, thereby obtaining the stack access address. Since no processing is required, stack access can be speeded up. In addition, in this multiple pointer method, a pointer can be assigned to each data block in the stack, so the programmer can consider the contents of the pointer register 12 as in the conventional method. There is no need to create a program (by inserting the above), and the program can simply read the data block using the pointer, making it easier to create the program. Also, since only a portion of the pointer is brought to the pointer register and the rest is saved in the main memory, the pointer register only needs to have a small capacity.

As described in detail, the present invention provides advantages such as reducing stack pointer loading and saving overload and speeding up stack access.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an overview of a stack memory device.
FIG. 2 is a program diagram showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the contents of a pointer register. In the drawing, 10 is a central processing unit, 12 is a pointer register, 14 is a stack memory, 16 is a data register, 18
20 is a control circuit, 2o is an LRU circuit, 22 is a pointer register, and 24 is a multiplexer. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi

Claims (1)

[Claims] In a stack memory access control method that includes a stack pointer and is accessed by the address stored in the pointer, a plurality of stack pointers are provided, each pointer stores a stack address together with a pointer number, and the pointer number is specified when accessing the stack. outputs the stack address of the pointer with the corresponding number, and before accessing the stack, checks whether the pointer number is in the stack pointer, and if not, retrieves the stack address of the stack pointer from external memory. A stack memory access control method characterized by storing a pointer number in a stack pointer.