JPH1196107A - Request management circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make easily manageable both of memory read and I/O read and to improve the use efficiency and throughput of a system bus. SOLUTION: A request management circuit 100 includes a memory read management table 120 for managing memory read requests and an I/O read management table 130 for managing I/O read requests. A read response control circuit 150 clears the table 120 or 130 in accordance with a request number and a response sort respectively transferred through a request number line 330 and a response sort line 340 prior to a response to a read request. A request buffer 140 controls whether a new read request is to be issued or not in accordance with the contents of the tables 120, 130.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a request management circuit, and more particularly to a request management circuit for managing a read request issued from a processor.

[0002]

2. Description of the Related Art Conventionally, in this type of technology, a request for a certain input / output device (hereinafter, a request issued on a bus is sometimes referred to as a "transaction" in particular) is executed during execution of another request. A split-type transaction to access is used. For example, in Japanese Patent Application Laid-Open No. 8-95905, a bus interface circuit capable of executing a split-type transaction is provided so that transactions for a plurality of input / output devices can be executed simultaneously. Also, Japanese Patent Laid-Open No. 6-14 / 1994
In No. 9730, a bus converter corresponding to a split-type bus and a means for associating a read transaction with its response are provided to suppress a decrease in bus use efficiency due to transaction competition.

On the other hand, a read transaction and its response are associated with each other by giving a number to the read transaction and indicating the number when transferring response data. However, the number of read transactions that can be managed depends on the number of logical circuits. Limited by In other words, although the read transaction and its response are separated by the split bus and a new read transaction can be issued without waiting for the preceding read response, the number of issued transactions is limited by the amount of logic circuits, and the number of read transactions is limited. Once the transaction has been issued up to the upper limit, no more read transactions can be issued. Here, the response performance of recent memory devices has been increasing due to the improvement in access speed, but the response performance of input / output devices is much worse than that of memories due to the hierarchization of input / output buses. If both a read transaction to the memory and a read transaction to the I / O device are treated as a read transaction, the read transaction to the I / O device with a slow response speed will stay for a long time on the system bus, This is a factor that hinders the issuance of transactions, especially read transactions to memory.

[0004]

In the above-mentioned prior art,
The read request for the memory and the read request for the input / output device are treated as the same read request without distinction. Generally, the response speed of an input / output device is slower than that of a memory, so that a read request to the input / output device may stay for a long time. This becomes more remarkable due to a reduction in the response speed of the input / output device due to the multilayered input / output bus.

SUMMARY OF THE INVENTION It is an object of the present invention to separately manage a read request for a memory and a read request for an input / output device, thereby facilitating the management of both the memory read and the input / output read, and improving the system bus use efficiency and throughput. To make it happen.

[0006]

In order to solve the above-mentioned problems, a request management circuit according to the present invention comprises a memory read management table for managing a read request for a memory and an input / output read management table for managing a read request for an input / output device. And

Further, another request management circuit of the present invention further includes a read response control circuit for clearing the memory read management table or the input / output read management table in response to a read request.

Further, another request management circuit of the present invention holds a request from a processor, and when the memory read management table is full and the request is a memory read request, or when the input / output management table is Is full and the request is an input / output read request, further includes a request buffer for suppressing issuance of the request.

In another request management circuit according to the present invention, the memory read management table stores a valid bit corresponding to each memory read request by a number assigned to each memory read request, The table stores valid bits corresponding to each input / output read request in the order in which the input / output read requests were issued.

In another request management circuit according to the present invention, the input / output device belongs to one of a plurality of input / output control circuits, and the input / output read management table stores the plurality of input / output control tables. One set of management tables is included for each circuit.

Further, the information processing system of the present invention comprises a processor, a memory, an input / output device, a system bus, a request management circuit for connecting the processor and the system bus, A memory control circuit that connects the system bus and the input / output device that connects the input / output device,
The request management circuit includes a memory read management table for managing a read request for the memory and an input / output read management table for managing a read request for the input / output device.

Further, in another information processing system according to the present invention, the request management circuit further includes a request buffer for holding a request from the processor, and the request buffer is such that the memory read management table is full and If the request is a memory read request, or if the input / output management table is full and the request is an input / output read request, issuing of the request is suppressed.

Further, another information processing system of the present invention comprises:
A plurality of the input / output control circuits are connected to the system bus,
The input / output read management table includes a set of management tables for each of the plurality of input / output control circuits.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, in an embodiment of the present invention, a request management circuit 100
0 and the system bus 300 as a bridge circuit. The input / output control circuit 500 and the memory control circuit 400
Together with the system bus 300. An input / output bus 550 is connected to the input / output control circuit 500, and a plurality of input / output devices 551 to 553 are connected to the input / output bus 550.
Is connected.

Referring to FIG. 2, the request management circuit 1
Reference numeral 00 denotes a decoder 110 for decoding a request from a processor, a command generation circuit 115 for generating a command for a request issued to an address / command line 310 (ADR / CMD) of the system bus 300, and a request before issuance. Request buffer 14
0, a memory read management table 120 for managing issued read requests, and an input / output read management table 1
30 and the request number line 330 of the system bus 300
And a read response control circuit 150 for processing response information of the response type line 340 (ID / CODE).

Referring to FIG. 3, a memory read management table 120 includes a request number (ID) field 1 for assigning a number to a memory read request and managing the number.
22 and an address field 123 for holding an address
And a valid bit 124, and a logical product (AND) circuit 125 for generating a logical product of the valid bits. The output of the AND circuit 125 is the memory read management table full signal 1
21 is provided to the request buffer 140.

Referring to FIG. 4, the input / output read management table 130 includes a valid bit 132 and a logical product (AND).
And a circuit 133. The output of the AND circuit 133 is provided to the request buffer 140 as an input / output read management table full signal 131.

Referring to FIG. 5, request buffer 1
Reference numeral 40 denotes a command field 141, an address field 142, a valid bit 143, and a logical product (AND)
It includes circuits 144, 145 and 147 and a logical sum (OR) circuit 146.

Referring to FIG. 6, the read response control circuit 150 outputs the memory read management table clear signal 1
And a logical product (AND) circuit 153 for outputting 51. Although only one AND circuit 153 is shown,
Actually, the number of AND circuits corresponding to the maximum number of request numbers is provided, and any one of the AND circuits corresponding to the request number line 330 is selected by the decoder 154.
Whether the memory read request or the input / output read request corresponds to the response type line 340 is determined by the AND circuit 15.
Either the signal line to each input terminal of No. 3 or the signal line 152 is selected by the decoder 155.

Next, the operation of the embodiment of the present invention will be described.

Referring to FIG. 1, when the processor 200 issues a read instruction, the request management circuit 100 issues a read request to the system bus 300. If the target of the read instruction is the memory 450, the memory control circuit 400 responds and the input / output devices 551 to 55
If it is 3, the input / output control circuit 500 issues a read request to the lower input / output bus 550, and any of the input / output devices 551 to 553 responds. Returns a response to

Referring to FIG. 2, decoder 110 decodes a read instruction from processor 200 to identify whether the target is a memory or an input / output. The command generation circuit 115 generates a read request command corresponding to the target, and stores the read request command in the request buffer 140.

Referring to FIG. 5, request buffer 1
At 40, the command is the command field 141
The address of the read request is held in the address field 142, and the valid bit 143 is set.

Referring to FIG. 2, the request management circuit 1
At 00, a read request is issued to the address / command line 310 (ADR / CMD). If the read request is a read request to the memory, the read request is issued to the memory read management table 120; It is managed at 130.

Referring to FIG. 3, in the memory read management table 120, numbers are assigned to memory read requests in the order in which they were issued, and the request number (ID)
It is stored in the location (entry) of the number shown in the field 122. At that time, the address is in address field 1
23, and the valid bit 124 is set. The memory read request is sent to the memory read management table 12
When issued to the upper limit of 0, the logical product (AND) circuit 1
25, the memory read management table full signal 1
21 becomes effective.

Referring to FIG. 4, in the input / output read management table 130, input / output read requests are stored in the order in which they were issued, and a valid bit 132 is set. When the I / O read request is issued up to the upper limit of the I / O read management table 130, a logical product (AND)
The input / output read management table full signal 131 detected by the circuit 133 becomes valid.

Referring to FIG. 5, request buffer 1
At 40, the memory read management table full signal 12
1 becomes valid, and when the command held in the command field 141 is a memory read request, the output of the logical product (AND) circuit 145 becomes valid. On the other hand, when the input / output management table full signal 131 becomes valid and the command held in the command field 141 is an input / output read request, the output of the logical product (AND) circuit 144 becomes valid. When one of the outputs of the logical product (AND) circuits 144 and 145 becomes valid, it is detected by the logical sum (OR) circuit 146 and the issue of the read request is suppressed by the logical product (AND) circuit 147.

Referring to FIG. 2, the request number and response type transferred by the request number line 330 and the response type line 340 (ID / CODE) prior to the response to the read request are processed by the read response control circuit 150, The memory read management table 120 is issued by the memory read management table clear signal 151.
Or the input / output read management table clear signal 15
2 to the input / output read management table 130.

Referring to FIG. 6, the response type line 340 is
Indicates whether the response to the read is a memory read or an input / output read. That is, if the response is to the I / O read, the I / O read management table clear signal 15
2 becomes effective. In the case of a response to a memory read, the request number line 330 indicates the number assigned to the memory read request, and the number corresponds to the decoder 154.
AND circuit 153
Thereby, the corresponding memory read management table clear signal 151 becomes valid.

Referring to FIG. 3, when the memory read management table clear signal 151 becomes valid in the memory read management table 120, the valid bit 124 of the corresponding number is cleared. On the other hand, referring to FIG. 4, when the I / O read management table clear signal 152 becomes valid in the I / O read management table 130, the valid bit 132 issued first is cleared.

As described above, according to the embodiment of the present invention, the read requests are managed separately in the memory read management table 120 and the input / output read management table 130, so that the stayed input / output read requests can be replaced with new ones. An event that hinders the generation of a memory read request can be prevented.

Next, another embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 7, in another embodiment of the present invention, another input / output control circuit 600 is connected to system bus 300, and this input / output control circuit 600 is connected to input / output bus 650 via input / output bus 650. Except that the input / output devices 651 and 652 are connected, the overall configuration is the same as that of the embodiment described with reference to FIG.

Referring to FIG. 8, a request management circuit 100 according to another embodiment of the present invention comprises a read response control circuit 750, an input / output read management table 73,
The configuration is the same as that of the request management circuit described with reference to FIG. 2 except that the number of paths is 0 and the number of paths of the request buffer 740 is plural.

Referring to FIG. 9, an input / output read management table 730 according to another embodiment of the present invention manages input / output read requests for each input / output device control circuit. That is, it has a plurality of sets of effective bits and AND circuits. The number of this set is the request management circuit 1
00 corresponds to the number of input / output control circuits to be managed. Each of the logical product (AND) circuits outputs an input / output read management table full signal 731 corresponding to each set. The reason for managing each I / O device control circuit is that
Since the I / O device control circuit maintains the order of read and response for the I / O devices under its control, the management at the level of the request management circuit 100 is sufficient if managed for each I / O device control circuit. is there.

Referring to FIG. 10, request buffer 740 has an AND circuit corresponding to the number of input / output read management table full signals 731. That is, an input / output read request corresponding to the input / output control circuit whose table is full is provided by a logical product (AND) circuit 744.
OR 745, and a logical sum (OR) circuit 747
And input to one terminal of a logical product (AND) circuit 748. As a result, the issue of the input / output read request is suppressed.

Referring to FIG. 11, read response control circuit 750 includes a logical product (AND) circuit 753 for outputting memory read management table clear signal 151 and a logical product (AND) for outputting input / output read management table clear signal 752. A circuit 755 is included. AND circuit 75
3 and 755 each have only one AND circuit corresponding to the maximum number of request numbers, and one of the logical AND circuits corresponding to the request number line 330 is illustrated. The circuit is selected by the decoder 754. Either a memory read request or an input / output read request is selected by the decoder 756 from one of the AND circuits corresponding to the response type line 340.

Next, the operation of the other embodiment of the present invention will be described.

Referring to FIG. 7, a read instruction from the processor 200 is issued from the request management circuit 100 to the system bus 300 as a read request. If the target of the read instruction is the memory 450, the memory control circuit 400 responds. If the target is an input / output device, the input / output control circuit 500 or 600 issues a read request to the input / output bus 550 or 650 further below. Input / output devices 551-553 or 651
To 652 respond, and the input / output control circuit 500 or 600 returns a response to the system bus 300.

Referring to FIG. 2, the request management circuit 1
At 00, the decoder 110 decodes the read instruction from the processor 200 to identify whether the target is a memory or an input / output, and further identifies which input / output device is under the control of the input / output device control circuit. . The command generation circuit 115 generates a read request command corresponding to the target by the command generation circuit 115, and stores the read request command in the request buffer 740.

Referring to FIG. 10, in the request buffer 740, the command is stored in the command field 741.
The address of the read request is held in the address field 742, and the valid bit 743 is set.

Referring to FIG. 8, the request management circuit 1
At 00, a read request is issued to the address / command line 310 (ADR / CMD). If the read request is a read request to the memory, the read request is issued in the memory read management table 120. It is managed in the table 730.

Referring to FIG. 9, in the input / output read management table 730, since the input / output read requests are managed in the unit of the input / output device control circuit, the order in which the requests are issued to the corresponding table on the input / output device control circuit side. And the valid bit 732 or 734 is set. When the I / O read request is issued up to the upper limit value of the I / O read management table 730, a logical product (AND)
The input / output read management table full signal 731 detected by the circuit 733 or 735 on the corresponding input / output device control circuit side becomes valid.

Referring to FIG. 10, in the request buffer 740, the memory read management table full signal 1
21 is valid, and when the command held in the command field 741 is a memory read request, the output of the logical product (AND) circuit 746 is valid. On the other hand, when the input / output management table full signal 731 is valid and the command held in the command field 741 is an input / output read request, the logical product ( AND) The output of the circuit 744 or 745 becomes valid. When any of the outputs of the logical product (AND) circuits 744 to 746 becomes valid, it is detected by the logical sum (OR) circuit 747, and the logical product (AND) circuit 748 suppresses the issuance of the read request.

Referring to FIG. 7, the request number and response type transferred by the request number line 330 and the response type line 340 (ID / CODE) prior to the response to the read request are processed by the read response control circuit 750. The memory read management table 120 is issued by the memory read management table clear signal 151.
To the input / output read management table 730 by the input / output read management table clear signal 752.

Referring to FIG. 11, in read response control circuit 750, response type line 340 indicates whether the response to the read is a memory read or an input / output read, and request number line 330 is a response to the memory read. If present, the number assigned to the memory read request indicates which input / output device control circuit is the response to the input / output read. In the response to the memory read, the number is decoded by the decoder 754, and the corresponding memory read management table clear signal 751 is output by the logical product (AND) circuit 753.
Becomes valid, the number of the input / output device control circuit is decoded by the decoder 754 in response to the input / output read, and the corresponding input / output read management table clear signal 752 is made valid by the logical product (AND) circuit 755. .

Referring to FIG. 9, in the input / output read management table 730, when the input / output read management table clear signal 752 becomes valid, the earliest valid bit 732 or 734 corresponding to the input / output device control circuit is issued. Clear

As described above, according to another embodiment of the present invention, it is possible to cope with a system further including a plurality of input / output control circuits.

[0050]

As is apparent from the above description, according to the present invention, the memory read and the input / output read can be managed separately, and the bus use efficiency and the throughput can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a request management circuit according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a memory read management table according to the embodiment of the present invention.

FIG. 4 is a block diagram showing an input / output management table according to the embodiment of the present invention.

FIG. 5 is a block diagram showing a request buffer according to the embodiment of the present invention.

FIG. 6 is a block diagram illustrating a read response control circuit according to the embodiment of the present invention.

FIG. 7 is a block diagram showing another embodiment of the present invention.

FIG. 8 is a block diagram showing a request management circuit according to another embodiment of the present invention.

FIG. 9 is a block diagram showing an input / output read management table according to another embodiment of the present invention.

FIG. 10 is a block diagram showing a request buffer according to another embodiment of the present invention.

FIG. 11 is a block diagram showing a read response control circuit according to another embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Request management circuit 110 Decoder 115 Command generation circuit 120 Memory read management table 130 I / O read management table 140 Request buffer 150 Read response control circuit 200 Processor 300 System bus 310 Address / command line 330 Request number line 340 Response type line 400 Memory control Circuit 450 Memory 500 I / O control circuit 550 I / O bus 551-553 I / O device 600 I / O control circuit 650 I / O bus 651, 653 I / O device 730 I / O read management table 740 Request buffer 750 Read response control circuit

Claims (8)

[Claims] 1. A request management circuit, comprising: a memory read management table for managing a read request for a memory; and an input / output read management table for managing a read request for an input / output device. 2. The request management circuit according to claim 1, further comprising a read response control circuit that clears the memory read management table or the input / output read management table in response to a response to the read request. 3. Holding a request from a processor,
If the memory read management table is full and the request is a memory read request, or if the input / output management table is full and the request is an input / output read request, issue of the request is suppressed. The request management circuit according to claim 1, further comprising a request buffer. 4. The memory read management table stores a valid bit corresponding to each memory read request by a number given to each memory read request, and the input / output read management table issues an input / output read request. 2. The method according to claim 1, wherein the valid bits corresponding to the respective input / output read requests are stored in the specified order.
Request management circuit as described. 5. The input / output device belongs to any one of a plurality of input / output control circuits, and the input / output read management table includes a set of management tables for each of the plurality of input / output control circuits. The request management circuit according to claim 1, wherein the request management circuit includes: 6. A processor, a memory, an input / output device, a system bus, a request management circuit connecting the processor and the system bus, a memory control circuit connecting the system bus and the memory, In an information processing system including an input / output control circuit that connects the system bus and the input / output device, the request management circuit includes: a memory read management table that manages a read request for the memory; and a read request for the input / output device. And an input / output lead management table for managing the information. 7. The request management circuit further includes a request buffer for holding a request from the processor, wherein the request buffer is provided when the memory read management table is full and the request is a memory read request. 7. The information processing system according to claim 6, wherein when the input / output management table is full and the request is an input / output read request, the issuance of the request is suppressed. 8. The system according to claim 1, wherein a plurality of said input / output control circuits are connected to said system bus, and said input / output read management table includes a set of management tables for each of said plurality of input / output control circuits. 6. The information processing system according to item 6.