JP2740579B2 - Display control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for controlling a flat panel display.

As a display device such as a data processing device, C is used.
Although the RT display device is widely used, since this display device has a certain depth dimension, it is often difficult to secure an installation space in a small office or the like.

Therefore, a flat panel type display using EL, plasma, liquid crystal or the like is used instead of a CRT display device.

[0004]

2. Description of the Related Art FIG. 6 shows a configuration of a conventional example.
In this device, the CRT output from the data processing device 60 is used.
The display data is displayed on the liquid crystal display 10.

In FIG. 1, CRT display data output from a data processing device 60 is converted into a writing unit (one word) in the display memory unit 12 by the interface unit 20 and then written into the display memory unit 12, and thereafter, Are read out from the display memory unit 12 to the interface unit 18 and displayed on the liquid crystal display 10.

The write address and the read address of the display memory section 12 are indicated by the outputs of the write counter section 28 and the read counter section 14, respectively, and the counter outputs are sent to the display memory section 12 via the address selector section 62. Given to.

The write counter 28 and the read counter 14 are controlled by the write controller 30 and the read controller 16, respectively, and their control is synchronized with the CRT display and the display on the liquid crystal display 10, respectively. It is done.

As a result, a display similar to that of a CRT display device can be performed on the liquid crystal display 10 without changing the software of the data processing device 60.

FIG. 7 illustrates the configuration of the write counter unit 28 when the number of dots in the horizontal direction is a power of two. In this case, the write counter unit 28 is replaced by a horizontal counter 70 and a line counter 72. Can be configured.

[0010]

However, when the resolution is dynamically switched in response to a plurality of resolutions as in a multi-scan type CRT display device, a vertical counter and other auxiliary circuits are required. The configuration becomes large.

The present invention has been made in view of the above-mentioned conventional circumstances, and an object of the present invention is to provide an apparatus which can switch resolutions and has a simple circuit configuration.

[0012]

In order to achieve the above object, a display control device according to the present invention is configured as shown in FIG.

A display memory unit 12 shown in FIG. 1 stores data displayed on the flat panel display 10, and a read counter unit 14 specifies a read address of the display memory unit 12.

The reading control unit 16 controls the display 10
The first interface unit 18 gives the data read from the display memory unit 12 to the display 10 in synchronization with the display timing.

The second interface unit 20 is a CRT
The display data is converted into a format for the display memory unit 12 and supplied to the display memory unit 14, and the display clear unit 22 clears the stored contents of the display memory unit 12 when reset end or a command to switch the resolution is given. I do.

Further, the line counter 24 stores the current C
The RT display line is specified, the conversion memory unit 26 stores the write start address corresponding to each CRT scan line for a plurality of resolutions, and writes the address corresponding to the output of the line counter 24 from the address group for the designated resolution. Output start address.

The write counter unit 28 generates a write address of the display memory unit 12 by a counter operation based on the address indicated by the output of the conversion memory unit 26, and the write control unit 30 controls the timing of CRT display. The counting operations of the line counter 24 and the write counter 28 are controlled in synchronization.

[0018]

The counting operation of the line counter unit is controlled by the write control unit in synchronization with the timing of the CRT display. As a result, an output indicating the current CRT scanning line is sent from the line counter unit to the conversion memory unit. Given.

In the conversion memory 26, a write start address group corresponding to the output of the line counter section 24 is read out of a write start address group prepared for a designated resolution, and the write start address is written in the write counter section 28. Sent to

The count operation of the write counter unit 28 is controlled by the write control unit 30 in synchronization with the timing of the CRT display, and the write address separated by the count value from the write start address corresponding to the current CRT scan line. Is sent from the write counter unit 28 to the display memory unit 12.

Therefore, it is possible to sequentially write the write address of the CRT display data converted by the interface unit 20 to an address position determined by a specified resolution.

Therefore, on the display memory of the display 10, data for CRT display can be displayed line by line in an area corresponding to the designated resolution.

When an instruction to switch the resolution is given to the display clear unit 22 and a different resolution is specified to the conversion memory unit 26, the screen of the display 10 is cleared and a new resolution is set. Then, the data for CRT display is read from the display memory unit 12 to the display 10 via the interface unit 18.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a display control device according to the present invention will be described below with reference to the drawings.

However, description of the same members as in the conventional example will be omitted. The display is performed in an interlaced manner.

FIG. 2 illustrates the configuration of the embodiment.
The CRT display data output from the data processing device 60 is displayed on the liquid crystal display 10 (see FIGS. 1 and 6) at 1120 × 780 dots (high resolution) or
It is dynamically switched and displayed at 4 × 768 dots (low resolution).

The CRT display data is sent to the data processing device 6
0 to the interface unit 20 and the write unit (1
After being converted to a word (word), it is provided to the display memory unit 12 via the clear data generation unit 80 of the display clear unit 22.

The vertical synchronizing signal and the horizontal synchronizing signal output from the data processing device 60 are input to the write control unit 30, and the data conversion operation of the interface unit 20 is controlled by the write control unit 30 accordingly. You.

In the write control section 30, the line counter section 24 is also controlled. The line counter section 24 is reset by a vertical synchronizing signal and counts up at the end of each horizontal display period.

As a result, a count value indicating the current CRT scanning line is obtained by the line counter unit 24, and is supplied to the conversion memory unit (ROM) 26 (lower side).

FIG. 3 illustrates the contents stored in the conversion memory unit 26. The data a, b, c, and
e, f..., low-resolution display data A, B, C,
.. Are stored in the conversion memory unit 26.

FIGS. 4A and 4B show display areas when high-resolution display and low-resolution display are performed. As can be understood from FIG. The head position of the field is the data a, b, c, d, e, f..., A, B, C, D,
E, F...

In FIG. 2, a signal FIELD indicating an odd field and a signal MODE (upper side) for designating a resolution (high resolution, low resolution) are input from the data processing device 60 to the conversion memory unit 26. MODEs and corresponding data groups "a, b, c, d, e, f ...",
Of the “A, B, C, D, E, F...”, Those corresponding to the current scanning line indicated by the output of the line counter unit 24 are selectively output in accordance with the signal FIELD.

The data (write start address) output from the conversion memory unit 26 is given to a write counter unit 28, and the write counter unit 28 performs write control via the selector 82 of the display clear unit 22. Controlled by the unit 30.

That is, the output data of the conversion memory unit 26 is loaded into the write counter unit 28 at the beginning of each horizontal display section, and the count value is incremented every time the display memory unit 12 is written during the horizontal display period. Controlled.

As a result, in the display area of FIG. 4A or FIG. 4B, the operation of scanning from left to right is repeated from top to bottom. At 28 is performed.

Further, a signal RE for instructing the end of reset is provided.
A signal MODE for instructing switching between SET and resolution is input from the data processing device 60 to the clear start detection circuit 84 of the display clear unit 22, and the horizontal synchronization signal HSYNC is input to the clear control circuit 26 of the display clear unit 22. I have.

The output of the clear start detecting circuit 84 is supplied to a clear control circuit 86, which controls the selector 82.

The clear data generation circuit 80 is also controlled by the clear control circuit 86, and the output of the clear end detection circuit 88 is given to the clear control circuit 86.

In this embodiment, the data processing device 60
When the signal RESET and the signal MODE are input to the clear start detection circuit 80, the input of the selector 82 is switched by the clear control circuit 86 from the write control unit 30 side to the clear control circuit 86 side.

The clear data generation circuit 80 is controlled by the clear control circuit 86, and zero clear data is sent from the clear data generation circuit 80 to the display memory unit 12 instead of the output data of the interface unit 20.

The clear control circuit 86 is connected to the selector 8
After resetting the write counter unit 28 via the second unit 2, the write counter unit 28 is sequentially incremented, and the sequentially incremented one is sent out by the write counter unit 28 via the selector 82, and as a result, All addresses are sequentially specified by the output of the write counter unit 28.

Accordingly, zero clear data of the clear data generation circuit 80 is written to all addresses of the display memory unit 12, and the display of the display 10 is cleared.

This clear operation is performed by the clear end detecting circuit 88.
When the detection is detected from the output of the write counter unit 28, the input of the selector 82 is switched to the write control unit 30 side after waiting for the horizontal synchronization signal HSYNC by the clear control circuit 86, and the zero clear data generating operation is performed. The end is instructed to the clear data generation circuit 80.

FIG. 5 is a flowchart for explaining the operation at this time. When the power is turned on, a reset end instruction is input, or a resolution switching instruction is input, the display memory unit 12 is activated. Is cleared to zero (step 500).

Then, the write address is output from the write counter 28 in synchronization with the CRT scan line, and the display 10 dynamically switches to a plurality of resolutions.

As described above, according to the present embodiment, it is possible to provide a device which can realize CRT compatibility compatible with a plurality of resolutions and has a simple circuit configuration.

The display memory section 12 is cleared to zero when the reset end or the instruction to switch the resolution is input, so that the data displayed up to that point can be prevented from being displayed as dust data.

A 16-bit ROM can be used for the conversion memory unit 26. In this case, the signals FIELD and MODE are input to the upper side of the ROM address, and the output of the line counter unit 24 is input to the lower side of the ROM address. .

The conversion memory unit 26 stores an 8-bit RO
It is also possible to adopt a configuration in which an 8-bit ROM is accessed twice using M and an 8-bit latch.

Further, when the address space of the display memory unit 12 is large (when the number of display bits is extremely large),
A large-capacity ROM is used for the conversion memory unit 26.

When a large-capacity conversion memory unit 26 is used, it is preferable to store memory select information in addition to the write start address.

It is easy to change the storage contents of the conversion memory unit 26 and the control method thereof so as to correspond to the non-interlaced system, more resolutions, and to support multi-gradation display and color display.

It is not always necessary to perform the display clearing operation every time the resolution is changed.
Data and patterns are available.

[0055]

As described above, according to the present invention, it is possible to realize an apparatus which can handle a plurality of resolutions and has a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating the configuration of an embodiment.

FIG. 3 is an explanatory diagram of storage contents of a conversion memory unit.

FIG. 4 is an explanatory diagram of a display address.

FIG. 5 is a flowchart illustrating a display operation of the embodiment.

FIG. 6 is a diagram illustrating the configuration of a conventional example.

FIG. 7 is an explanatory diagram of a configuration of a write counter unit in a conventional example.

[Explanation of symbols]

 Reference Signs List 10 display 12 display memory unit 14 read counter unit 16 read control unit 18, 20 interface unit 22 display clear unit 24 line counter unit 26 conversion memory unit 28 write counter unit 30 write control unit 60 data processing unit 62 address selector unit 80 Clear data generation circuit 82 Selector 84 Clear start detection circuit 86 Clear control circuit 88 Clear end detection circuit

Claims (1)

(57) [Claims] 1. A flat panel display (1)
Display memory unit (1) for storing data displayed in (0).
2), a read counter unit (14) for specifying a read address of the display memory unit (12), and a read control unit (16) for controlling the read counter unit (14) in synchronization with the display timing of the display (10). A first interface unit (18) for providing data read from the display memory unit (12) to the display (10), and converting CRT display data into a format for the display memory unit (12). The second interface unit (2) provided to the display memory unit (12)
0), a display clear unit (22) for clearing the storage contents of the display memory unit (12) when a reset end or resolution switching instruction is given, and a line counter unit (24) for specifying the current CRT display line. And a conversion memory for storing a write start address corresponding to each CRT scan line for a plurality of resolutions and outputting a write start address corresponding to the output of the line counter unit (24) from an address group for the designated resolution. (26), a write counter (28) for generating a write address of the display memory (12) by a counting operation based on an address indicated by an output of the conversion memory (26), and a CRT display. The write control unit (3) that controls the counting operation of the line counter unit (24) and the write counter unit (28) in synchronization with the timing.
0), and a display control device.