JPS61254981A - Multiwindow display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to multi-window display control in a display system, in which characters, figures, etc., as well as multi-gradation images, moving images, etc. can be simultaneously displayed on a single display screen. The present invention relates to a display control device for displaying images.

(Prior Art) High-performance display devices such as workstations are required to have a function of displaying a plurality of screen images on one display device (for example, a CRT) by dividing the screen or superimposing them. In order to display multiple screen images on one CRT, the dot images of multiple screens are developed in a memory called a window buffer. An image of the entire display screen in which these screen images are superimposed or displayed simultaneously is created in a memory called a frame buffer. An image of the entire display screen is created by transferring the whole or part of the screen image developed on the window buffer to a specified area on the frame buffer. The entire 7-frame computer is equipped with a CRT.
Multi-window display can be realized by reading out in synchronization with raster scanning.

Several methods have been proposed to achieve these functions, depending on the physical arrangement of the frame buffer and window buffer. However, as mentioned above, the entire or part of the multiple screen images developed on the window buffer is converted into a 7-frame buffer based on data regarding the position of the images within the display screen and the state of overlap between the screen images. By transferring the images above, it can be logically assumed that all display screen images are created using the same method.

Fig. 2 is a diagram showing an example of a conventional multi-window display system, in which 1 is a window buffer in which multiple screen images are expanded, 11, 12, 13 are each screen image, 1
11, 121, 131 are screen images 11, 12.13
Partial image of 2 is a 7-frame PDF, 21.22.
23 is a partial display image generated by transferring partial images 111, 121, and 131 to a 7-frame buffer; 3 is a CRT synchronization signal generation circuit CRTC131 is an access control signal line for frame buffer 2; 32 is a CRT
4 is an image mover that transfers image data from window 7a 1 to 7ram 7a 2, 5 is a CRT, 51 is a display screen of CRT 5, 115,
125, 135 are partial display images 112, 122.1
32 is displayed, 711 is frame buffer 2
output signal line, 20 is a color lookup table, 7
12 is an output signal line of the color lookup table 20;
R.G.

B is a D/A converter for red, green, and blue.

(Problems to be Solved by the Invention) In the embodiment shown in FIG. 2, the dot image of the screen expanded on the window buffer 1 is transferred to the frame buffer 2 and thereby actually displayed on the CRT.

Therefore, the display screen is updated by transferring a partial image of a specific screen image in the window buffer 1 to the 7-frame buffer 2 using the bit mover 4. The update speed of the display screen is determined by the speed of drawing or writing dot images into the window buffer 1 and the speed of image transfer from the window buffer 1 to the frame buffer 2.

Normally, the transfer time for an image of about 1000 x 100 O is 3
It is 0 to 40 ms. For color display, if the frame buffer consists of multiple planes, transfers must be performed as many times as the number of planes. if,
12 assuming the frame buffer is 4 planes
It takes a time of 0 to 160 m5 to transfer Vc to the wind buffer color frame buffer.

Furthermore, it takes time to write the dot image to the window buffer. That is, since it takes at least 120 m5 to update the display screen, it is impossible to display a moving image in the embodiment of FIG. 2.

Further, in order to display a multi-gradation screen like a natural image, the number of planes of the frame buffer is required to be eight or more. Therefore, the update time for one screen further increases to more than 480 m5, making it completely impossible to display moving images.

Furthermore, the process of creating display data for videos, natural images, etc. is different from graphs, tables, or single-color text displayed on conventional color displays.

In general, a huge amount of data processing is required, and the characteristics are different from those for business use such as simple line drawings or graphics display for CAD, and it is difficult to handle it on devices with the same display architecture.

The present invention aims to improve the above-mentioned problems.

(Means for Solving the Problems) In order to solve the above-mentioned drawbacks, the present invention defines a window to be displayed in a specific area on the display screen, and the raster scanning timing of the CRT matches the display position of the window. When a match is detected, the display of the data read from the 7-frame buffer is stopped, and data input from another device or circuit is displayed instead.

(Function) The present invention provides a multi-window display system that displays a plurality of screens on one display device (for example, CRT).
In addition to displaying graphics and characters on the window,
The present invention is characterized in that screen information to be displayed on the display screen of a display device is read out from a source other than the refresh memory and displayed for the purpose of displaying moving images, natural images, etc. at the same time. Screen information consisting of characters, graphics, etc. is developed as a dot image on a refresh memory (same meaning as a frame buffer), and is displayed by reading the memory in synchronization with raster scanning of a CRT.

On the other hand, moving images and natural images are stored in the -H buffer memory. Define the size and position of the window for displaying videos and natural images on the display screen, and then display the CRT according to the definition.
The main feature is that the contents of the buffer memory, rather than the contents of the refresh memory, are displayed on the CRT when the raster scan of the window matches the display position of the window. Conventional multi-window display has been realized by creating a display screen image composed of a plurality of screen images on a frame buffer and reading out the frame buffer. In contrast, the present invention provides a mechanism for detecting coincidence between the window display timing and raster scanning, and is able to display images with completely different characteristics, such as moving images and natural images, on a single display device in multiple windows, which is different from the conventional method. is different.

(Embodiment) FIG. 1 shows an embodiment of the present invention, in which 6 is a multi-window control unit, 7 is a multiplex circuit, 80.81.
82 and 83 are source data input signal lines of various windows input to the multiplex circuit 7, 621.622
, 623, and 624 are control signal lines for notifying signals for controlling a control circuit (not shown) that generates the source of data input through the mace data input signal line.

Multi-window control unit) MWU 6 has a CRT
Set data representing the position and size of the window to be displayed on the display screen of step 5. Multi-window control unit [
6 notifies the multiplex circuit 7 of the selection of the source data input signal line for inputting the data to be displayed on the window, triggered by the detection of coincidence between the raster scanning timing of the CRT and the position of the window. Upon receiving the notification, the multiplex circuit 7 selects one of the source data input signal lines and displays the data sent from that signal line in the corresponding window. Therefore, source data input signal lines 80, 81, 82 . By loading images with completely different properties such as moving images, natural images, or videotex output images on 83, various types of multi-window displays are possible.

FIG. 3 is a diagram showing a detailed embodiment of the multi-window control unit 6, in which 311 is a signal line for notifying the X coordinate value among the 7 frame buffer access signal lines, and 312 is a signal line among the frame buffer access signals i. A signal line for notifying the Y coordinate value; 313 is a display dot clock signal line for indicating one dot sample timing on the display screen; 611, 612;
, 613° 614 are address window detection circuits that detect the raster scanning timing corresponding to the position of the window displayed on the display screen; 621, 622, 623° 624
are address window detection circuits 611, 612, 613.
614 is an output signal line; 68 is a multiplex circuit in which data representing the overlapping relationship on the display screen of windows is set and controls the overlap between windows; 61 is an output signal line of the multiplex circuit 68;

Prior to the operation of this circuit, the position and size of the window on the display screen are set for the address window detection circuits 611, 612, 613, and 614, respectively. The multiplex circuit 68 is set with data indicating the relationship between overlapping images on the window display screen. CRTC3
In order to read out the frame buffer in accordance with the raster scanning timing of the CRT, a 7 frame buffer address is generated on the signal lines 311 and 312. The address value is detected by address window detection circuits 611, 612, 613 and 6.
14 and is used to detect that the dot position within the window has raster scan timing. if,
If raster scanning is detected within any window on the display screen, the detection of a match is signaled by address window detection signal lines 621, 622, 623.
Alternatively, the multiplex circuit 68 is notified via 624. Data representing overlapping windows is set in advance in this circuit, so if CRTC raster scanning is scanning a location where multiple windows overlap, the window detection signal line A plurality of address window detection signal lines are simultaneously notified to the multiplex circuit 68, and only the address window detection signal line of the uppermost window is selected. The output of the selected signal line is notified to the multiplex circuit 7 (shown in FIG. 2) via the signal line 61.

In the multidalex circuit 7, according to the data notified via the signal line 61, the first data input signal lines 80, 81 .
Select one of 82 or 83. In the above description, for the sake of simplicity, the number of first data input signal lines and the number of address window detection circuits in FIG. 3 are four, but it goes without saying that a larger number may be used.

FIG. 4 shows a detailed embodiment of the address window detection circuit 611, in which CMP 1 , CMP 2 , CMP
3. CMP4 is a comparison circuit, Dl t D2 is a comparison data input terminal of each comparison circuit, Q and Q are output terminals of each comparison circuit, and when the value of input terminal D1 is greater than the value of input terminal D2, Q is a logic "'1" is output, and when the value of the input terminal D1 is less than the value of the input terminal D2, a logic "O" is output. Mutual is the opposite state of Q. R is a reset terminal of each comparison circuit, and when the input value becomes logic "1", the output terminal Q becomes logic "O".
”.CLK is the clock terminal of each comparison circuit, and CR
The display dot clock output from TC3 is input. 611a, 611b, 611c are two-manual AND circuits, 6211, 6212, 6213, 6214 are signal lines forming the address window detection signal line 621, X is the X coordinate of the upper left point of the window on the display screen, and Y3 is the same. The y coordinate, X8, is the X coordinate of the lower right point of the window on the display screen, and Ye is the y coordinate. Display dot clock signal line 3
13 clock, the comparator circuit starts up and calculates the frame buffer address (X, Y), the coordinate values ('xstys) and (Xe, Y) of the two vertices of the window on the color display screen.
Compare e). Comparison circuit CMPI is X8 and X i
CMP 2 is X @ and X, CMP 3 is Y3 and Y CM
P4 compares Ye and Y. Note that the window includes two vertices (X8pY8) and (xe, Y, ). Therefore, the comparison circuits CMP 2 and CMP 4 actually compare Xe+1 and X and Ye+1 and Y, respectively. In the example of FIG. 4, the output terminals of the comparison circuits CMP 1 and CMP 3 both represent the dots included in the frame puffer address (X, Y) column of logic "1", so the AND circuit 611a The condition is satisfied, and the state of the output signal line 6211 of the circuit is logic ``1''.
”. As raster scanning progresses, the 7-frame spot address (x, y) where CRTC3 is generated changes, and when this address (x, y) indicates the position of a dot outside the window, CMP2, Either output terminal Q of CMP 4 is turned on.Therefore, CMP 1 or CM
Since P 3 is reset, CMP 1 or CMP
The output terminal Q of No. 3 becomes a logic "0" state. Therefore, the output terminal of the AND circuit 611a becomes a logic "0" state. That is, the logic ``'1 of the output terminal of the piece circuit 611a
” state is logic “0” indicating that the raster scan is in the window.
” state indicates that it is out of window.

The output terminals Q of CMP 2 and CMP 3 are both logic "1n"
What is the state of raster scanning at window addresses Y8 and Ye?
There are X3 and X inside. represents something that is not in

This is used to control a circuit that sends data to a source data input signal line, which will be described later. CMP 2 and CMP
The reason why the output terminals Q of 4 are both in the logic “1” state is that
Raster scanning is done at window addresses Y8, Ye and X8.
and is outside of Xe, indicating that raster scanning within the window has been completed. This state is notified to the outside through the output signal line 6213 of the melon circuit 611C. The multiplex circuit 68 has signal lines 6211, 5212, 6213. and 6214 and other signal lines are selected depending on the overlapping state of the windows. By the way, FIG. 4 shows one embodiment of the address window detection circuit, and it goes without saying that other methods may be used.

Furthermore, the size of the window can be arbitrarily changed by changing the value set in the comparison circuit.

FIG. 5 is a diagram showing an embodiment of a circuit for supplying various data to source data input signal lines, in which 8 is a buffer memory, 9 is a memory control circuit, 81 is a source data input signal line, and 91 is a multiplexer. circuit, 922 is a memory access signal line, and 811 is an external synchronization signal line o o
ddQ, odd 1, evenQ.

5ven 1 is a component of a buffer memory, and in this embodiment, since normal television signals are stored, each is a field memory, and 933 is an input signal line from the outside.

The refresh frequency of the 7'4 screen used for workstations, etc. is 60Hz non-interlaced or 90Hz interlaced to prevent screen flickering.
In addition, since the resolution is high, the readout clock for display pixels is 59 MHz to 78 MHz. On the other hand, the readout clock of a normal television signal is at most 10.7
It is about 4 MHz. High-speed normal television signal
Displaying on a high-speed display requires a buffer to control the time relationship. Buffer memory 8 in Figure 5
plays the role of matching signals of two different time systems.

A television signal is input from an external input signal line 933, and the multiplex circuit 91 determines whether the signal is input to the odd or even buffer memory depending on whether the signal is for an odd field or an even field. Also, oddQ and odd of the buffer memory
Switching between 1 and 1 is performed by alternately specifying buffer memories. Reading of written field memory can be achieved by alternately reading odd and even buffers that are not being written.

The instruction to read the buffer memory is transmitted through the output signal line 621 of the address window detection circuit 611. The memory control circuit 9 reads out the data of the odd field or even rod field according to the instruction notified through the output signal line 621. Note that for reading, among the field memories, the field memory that is not being written is accessed. That is, if the read clock frequency is significantly lower than the clock frequency of the input signal, the same content may be read out one or more times while writing to one field memory. However, this makes it possible to display an image signal whose frequency relationship is completely different from that of a CRT display signal in one window on the display screen. FIG. 6 shows a detailed embodiment of the memory control circuit MCU 6 of FIG. FFQ,FFI,F
F2゜FF3, FF4 are flip defo knobs, 9a
t 9 b p 9 e p9d, 9e, 9f, 9g
, 9h is a melon circuit, 91 is a NOT circuit, D is an FFI,
FF2. FF3. The input terminal of FF4, CLK is the clock terminal of each 7-lip 70-bit, Q and Q are the output terminals of each 7-lip flop, 92 is an address generation circuit when reading the buffer memory, 93 is an address generation circuit when writing the buffer memory, 911 is the output of the address generation circuit 92, which is a buffer memory read access signal line, and 912 is the output of the address generation circuit 93, which is a buffer memory write access signal line. Input signal lines 6211, 6212, 621
3.6214 constitutes the output signal line 621 of the address window detection circuit 611. 8111 and 811
2 is a control signal line that is similarly notified from a circuit (not shown) that generates source data, and 931 specifies whether the field to be written into the buffer memory is odd or even.
A field designation control line 932 is a buffer switching control line that notifies whether the buffer currently being written is 0 or 1.

The operation of this circuit is to determine whether the currently input television signal is an odd field or an even field, based on a synchronizing signal from a data input device notified through a control signal line 8111. The determination result is notified to the input terminal of FF3 from buffer write address generation circuit 93 via control line 931. Further, the buffer write address generation circuit 93 notifies the data input terminal of the FF 4 through the control line 932 of the number (0 or 1) of the writable buffer memory.

FF3 and FF4 sample the states of the two control lines. The states of the output terminals Q of FF3 and FF4 are AND
The circuit 9e#9ft9gp9h is notified and generates control signals for the four selections. control line 93
In the state of 1, logic "1" designates an odd field, logic "o" designates an even field, and in the state of the control line 931, logic "1" designates an even field.
1" is the buffer 1, and logic "0" is the buffer 0 designation state. If the states of the control lines 931 and 932 are both logic "1", the output of the AND circuit 9e becomes logic "1". .The output of AND circuit 9ft9g, 9h is logic "0"
It is. Therefore, the buffer write address generation circuit 93 is instructed to write the field data to number 0 of the odd field buffer as a buffer. The actual write address is generated using control signal lines 8111 and 8112. The trigger for changing the control line 932 is given in the following order. odd O-+ e
ven O−+ odd l →even l −+
odd O@ Buffer memory read control will be explained. Control signal lines 6211, 6212, 6213, 6214 and AN
The output signal lines of the D circuits 9a, 9b, 9c, and 9d control address generation when reading the buffer memory. The input states of the four melon circuits are determined by the states of the input terminals of FFI and FF2. The state of the input terminal of FF1 is FF4.
This is the opposite of the situation at the input terminal. The reason is to prohibit reading from the buffer memory during writing. The writing period is the period from the start to the end of writing one field of data. The state of the input terminal of FF2 changes to odd and 6 when one field worth of data is read out.
Change vans alternately. The FFQ uses the signal control line 62I3 as a clock input and alternately changes its output state every time a clock/bus pulse is applied. The signal control line 6213 is a control line from the address window detection circuit 611, and is used to notify the end of the raster scan within the window when the raster scan is outside the window addresses Y3, Ye, and U Xe (!: Xe). Therefore, the generation of the information notified on the control signal line is synchronized with the time when the reading for the bow yield is completed, so the information notified on the signal control line is generated in either buffer memory. Taking this as a trigger, the buffers to be read are alternately switched between odd and 6van.

If the state of the control line 932 is logic "1", FF1
The state of the input terminal of is logic "0".In addition,
If the state of the output terminal of FFQ is logic "1", the output terminal of AND circuit 9d becomes logic "1", which instructs the buffer read address generation circuit 92 to read out the number 1 of the odd field buffer. Become. Actual address generation is performed using the output signal line 621 from the address window detection circuit 611. The details of the buffer read/write address generation circuit are not directly related to the present invention and will therefore be omitted here.

FIG. 6 is one example, and it goes without saying that other implementation methods may be used.

In the above description, the embodiment has been described using a television signal as an example of the image signal connected to the source data input signal line, but it goes without saying that other signals such as facsimile, videotex, etc. may also be used.

(Effect of the invention) As explained above, the position of the window on the display screen is
Detected at RT raster scan timing, and triggered by C
It has the advantage that by switching the input signal line to the RT, not only characters and figures but also moving images and multi-gradation natural images can be displayed in a multi-window. Therefore, by applying the present invention to the display section of a conventional workstation, there is an advantage that the scope of application is widened not only for OA work but also as a display terminal for television receivers or videotex.

[Brief explanation of drawings]

Fig. 1 shows an embodiment of the present invention, Fig. 2 shows a conventional multi-window display system, Fig. 3 shows a detailed embodiment of multi-window control, and Fig. 4 shows an address window. A detailed embodiment of the detection circuit, FIG. 5 shows a circuit embodiment for supplying various data to the source data input signal line, and FIG. 6 shows a detailed embodiment of the memory control circuit MCU. 1... Wind buffer, 11, 12, 13゜14.
... Screen image, 111, 121, 131 ... Partial image, 2 ... Frame buffer, 21, 22.2
3... Partial display image, 3... CRTC131.
...Access control signal line, 32...Synchronization signal line, 4.
...Pit machine, 5...CRT, 51...Display screen, 115,125°135...Window, 711.
... Frame buffer output (1 line, 712... Color lookup table output signal line, 20... Color lookup table, R, G, B...~D/A converter, 6... Multi Window control unit, 7...
・Multiplex circuit, 80, 81, 82.83...
Source data input signal line, 621, 622, 623, 6
24... Control signal line, 311... Signal line for notifying the X coordinate value, 312... Signal line for notifying the Y coordinate, 31
3... Display dot clock signal line, 611, 612,
613゜614...Address window detection circuit, 62
1,622°623.624...Output signal line, 68.
・・Multiplex circuit, CMP 1, CMP 2
, CMP 3, CMP 4...comparison circuit, D
I+D2...Comparison data input terminal of comparison circuit, Q, Q
...Output terminal of the comparison circuit, R...Reset terminal of the comparison circuit, CLK...Clock terminal of the comparison circuit, 611
a, 611b, 611c...2-man power AND circuit, 62
11,6212,6213゜6214... Component of the address window detection signal line 621, Xs... X coordinate of the upper left point of the window, Ys... X of the upper left point of the window
Coordinates, Xe...X coordinates of the lower right point of the window, Ye...
- X coordinate of the lower right point of the window, 8... Buffer memory, 9... Memory control circuit, 81... Source data input signal line, 9I... Multiplex circuit, 922...
・Memory access signal line, 811... external synchronization signal line, oddQ, oddl, evenQ, evenl
- Buffer memory components, 933...external input signal lines, FFO, FFI, FF2. FF3. FF4
---Flip-flop, 9a. 9 b, 9 c, 9 d, 9 e, 9
f, 9 g, 9 h--AND circuit, 91
...NOT circuit, D...Flip-flop input terminal, CLK...Flip-flop clock terminal, Q
, Q...7 output terminal of Ritzo flop, 92... Address generation circuit when reading buffer memory, 93...
Address generation circuit when writing buffer memory, 911.
...Buffer memory read access signal line, 912...
・Buffer memory write access signal line. Patent applicant Nippon Telegraph and Telephone Corporation Patent application agent Patent attorney Megumi Yamamoto - I
Zufu 3 Koshu 4 Leap gathering time

Claims (1)

[Scope of Claims] A window buffer that stores a plurality of screen images developed into dots in order to simultaneously display the plurality of screen images on a display device that displays dot images by raster scanning; In a multi-window display system having a frame buffer that stores a display screen image composed of screen images, (a) displaying a window displayed on the display screen of a display device of the type that performs the raster scanning and displays the image; An output signal line of a circuit that outputs a screen image to be displayed on the window is connected to a display circuit of a CRT in synchronization with the timing at which a control device of the display device raster scans a position on the screen, or a plurality of windows are connected. means for selecting the output signal line of the circuit corresponding to the plurality of corresponding windows when the windows are arranged so as to be overlapped on the display screen; and (b) means selected by the means (a). Of the output signal lines,
A multi-window display control device comprising: means for selecting and displaying only the output signal line corresponding to the window arranged at the highest position on a display screen.