JPS62217288A - Display control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a display control method, and in particular to a method for displaying a display screen by dividing the display screen in order to display a plurality of screens on the display screen of one raster scan type display device. The present invention relates to a display control method.

(Prior Art) FIG. 6 is a block diagram showing a conventional display device, in which a CRT is used as the display device. In the figure, 1 is a processor that controls the entire device, 2 is a DMA controller, 3 is a CRT controller that generates addresses to be scanned for screen display, 4 is a selector, and 5 is a memory that stores display data for multiple screens. R for video
A M, 6 is a frame buffer that stores display data for one screen, 7 is a shift register, and is a P/S conversion circuit that converts input parallel data into serial data and outputs it; 8 is a P/S conversion circuit that converts the input parallel data into serial data and outputs it, and 8 converts the display data onto the display screen. This is a CRT for displaying images. ,9
8 to 9C are address buses, 10a.

Job is a data bus, and 11 is a serial data line. DM
The A controller 2 controls data transfer between the video RAM 5 and the frame buffer 6. The selector 4 receives the address from the address bus 9a or the CRT controller 3.
A display address inputted from address bus 9bii is selected, and the address is supplied to video RAM 5 and frame buffer 6 via address bus 9c.

FIGS. 7(a) to (C) are explanatory views of the operation of the apparatus shown in FIG. 6. FIG. 4(a) shows an example of display data in the video RAM 5. Further, FIG. 6B shows the storage state of display data in the frame buffer 6.

FIG. 4(c) shows the display state on the display screen of the CRT 8.

FIGS. 8(a) to 8(C) are explanatory diagrams during scrolling, and FIGS. 8(a) to 8(c) show the same locations as FIGS. 7(a) to 7(C).

Next, the operation will be explained.

Two display data (1) and (2) are stored in the video RAM 5, as shown in FIG. 7(,).

At this time, when creating the screen shown in FIG. 7(c), the data in the solid line portions of display data (1) and (2) in the video RAM 5 is transferred to the frame buffer 6 under the control of the DMA controller 2. The data is transferred and stored as shown in FIG. 7(b). On the other hand, the CRT controller 3 generates a display address for scanning the frame buffer 6, and the selector 4. Frame buffer 6 is accessed via address bus 9c.

The frame buffer 6 transfers the display data shown in FIG. 7(b) stored in accordance with the input display address to the data bus 1.
It is output to the P/D conversion circuit 7 via 0b. The display data converted from parallel data to serial data by the P/D conversion circuit 7 is transferred to the CRT 8 via the serial data line 11.
The image is displayed on the display screen of the CRT 8 as shown in FIG. 7(c).

When changing the screen displayed in this way to the display screen shown in FIG. 8(c), that is, when scrolling one of the divided rectangular areas, the video RAM 5 is Display data (1) shown in Figure 8(a)
The displayed data is within the solid line area.

The frame buffer 6 is controlled by the DMA controller 2.
and stored as shown in FIG. 8(b). The stored display data is then transferred to the CRT 8 via the P/S conversion circuit 7 in accordance with the display address from the CRT controller 3 and displayed on the display screen as shown in FIG. 8(c).

(Problems to be Solved by the Invention) However, in the conventional method, when scrolling one divided rectangular area, the video R
Because the display data must be transferred from AM5 to the frame buffer allo again.

There was a problem that scrolling took a long time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display control method that solves the above-mentioned problems and makes it possible to quickly change the display screen such as scrolling.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a storage means for storing data for a plurality of screens, and a part of the data of any screen read from the storage means. In a display control method for displaying a plurality of screens on one display screen, the display control method includes a buffer means for storing data for each scene, and a display means for displaying data from the buffer means on a display screen, and the display means displays data from the buffer means on a display screen. The first readout corresponds to the scanning speed of the display means.
a second controller that reads data from the storage means in accordance with the scanning speed of the display means, and a second controller that monitors the scanning position on the display screen of the display, and the scanning position is within a prespecified area. and a selection means for selecting data from the first controller and the second controller and outputting the selected data to the display means based on the determination result of the determination means, The content displayed in the area is changed by changing the reading start position from the area.

(Operation) According to the present invention, since the display control method is configured as described above, the technical means operates as follows.

First, part of the data of an arbitrary screen is stored in the buffer means from the storage means. The first controller reads data from the buffer means in accordance with the scanning speed of the display means and outputs it to the selection means. The second controller reads data from the storage means in accordance with the scanning speed of the display means and outputs it to the selection means.

That is, the first controller and the second controller perform reading in synchronization. The determining means determines whether the data read from the storage means is within a prespecified area, and outputs the determination result to the selecting means. The selection means selects data from the storage means and outputs it to the display means when the determination result indicates that the data is within the area. Further, when the determination result indicates that the data is outside the area, the selection means selects the data from the buffer means and outputs it to the display means.

The display means divides and displays the data from the selection means on the display screen as a result. When changing the display of a designated area, such as by scrolling, it can be quickly done by simply changing the reading start position (start address) from the storage means using the second controller. Therefore, the problems of the prior art described above can be solved.

(Embodiment) FIG. 1 is a configuration diagram showing an embodiment of a display device to which the method of the present invention is applied. In the same figure, the same reference numerals as in FIG. 6 indicate the same components, 90 to 9g are address buses, 10c to 1Of are data buses, and 12a is for reading display data from the frame buffer and displaying it. a first CRT controller that generates a display address of;
12b is a second CRT controller that reads display data from the video RAM 5 and generates display addresses for display; 13 monitors the absolute scanning position on the display screen of the CRT 8, and monitors whether it is within an arbitrary rectangular area; Area determination circuits 148 to 14c are selectors that determine outside the area. ,
Sl is the first CRT controller IZa and the second CRT
A horizontal synchronization signal for horizontal synchronization of the controller 12b, S
Similarly, 2 is a vertical synchronizing signal for vertically synchronizing the CRT controllers 12a and 12b, and S3 is an area inside/outside notification signal sent from the area determining circuit 13 to the selector 14c.

The selector 14a receives the address from the address bus 9C or the address from the first CRT controller i2a.
The display address input via d is selected and supplied to the frame buffer 6 via the address bus 9e.

The selector L4b selects an address from the address bus 9c or a display address input from the second controller 12b via the address bus 9f, and supplies the selected address to the video RAM 5 via the address bus 9g. Data bus 10c is connected to processor 1. The frame buffer 6I is connected between the video RAM 5 and the area determination circuit 13. The selector 14c selects the data bus lO from the frame buffer 6.
Display data input via d or video RAM
Display data inputted from No. 5 through the data bus 10e is selected based on the area inside/outside notification signal S3, and the selected display data No. 1 is transferred to the P/S conversion circuit 7 through the data bus 10f.

FIG. 2 is an internal configuration diagram of the area determination circuit 13.

This area determination circuit 13 includes an area designation register 131, a vertical counter 132, a horizontal counter 133, and a y5 comparator 13.
4, y0 comparator 135, X, comparator 136, X, comparator 137, and AND gate 138. The area specification register 131 specifies an arbitrary rectangular area ('J s t )' on the display screen of the CRT8.
e). The horizontal counter 133 counts the dot clock Cp, in which one pulse is input for one pixel, and calculates the horizontal count number Xc, which indicates the horizontal scanning position on the display screen of the CRT 8, by the Xs comparator 136 and the xe comparator 137. Eight outputs. The vertical counter 132 counts the pulses output when the horizontal counter 133 counts a predetermined number of times to obtain a vertical count number X that indicates the scanning position in the vertical direction on the display screen of the CRT 8. y
9 comparator 134 and y8 comparator 135.

y, the comparator 134 is an element of the area designation register 131, and the vertical count number y. and outputs the comparison result to the AND gate 138. Similarly, the Xe comparator 135 compares the element ye with the vertical count number ye, and outputs the comparison result to the AND gate 138. Also, X
, the comparator 136 has an element X, and a horizontal count number Xe,
The Xe comparator 137 calculates the element xe and the horizontal count number x
c and outputs the comparison result to the AND gate 138. The AND gate 138 is connected to each comparator (134 to 1
37), and calculates the logical product of the comparison results and sends the area/outside notification signal S.
Output as 3.

FIG. 3 shows each element V a + of the area specification register 131.
It is an explanatory diagram of the contents of V e +xg, xe, and is a CRT
It can be seen that any rectangular area on the display screen of No. 8 can be specified.

Table 1 shows y, comparator 134. y, comparator 1.35.
X, comparator 136. χ. FIG. 3 is an explanatory diagram of each function of the comparator 137, and shows that a "low" or "high" state is output depending on the comparison result.

Table 1: Comparator Function Table FIGS. 4(a) to 4(d) are explanatory diagrams of the operation of the device of this embodiment. 5A shows an example of display data in the video RAM 5, and FIG. 1B shows a storage state of display data in the frame buffer 6. Further, (c) in the same figure shows the specified position of a rectangular area on the display screen of the CRT 8 by the area specifying register 131 in the area determination circuit 13, and (d) in the same figure shows the specified position of the rectangular area on the display screen of the CRT8.
The display state on the display screen of T8 is shown.

FIGS. 5(a) and 5(b) are explanatory diagrams during scrolling; FIG. 5(a) shows the state of display data (1) in the video RAM 5, and FIG. 5(b) shows the display screen of the CRT 8. Shows the display state above.

Next, the operation will be explained.

The video RAM 5 is as shown in FIG. 4(a).

Two display data (1) and (2) are stored. The data in the solid line portion of the display data (2) in the video RAM 5 is transferred to the frame buffer 6 under the control of the DMA controller 2 and stored as shown in FIG. 4(b). Next, the first CRT controller 12a generates a display address for scanning the frame buffer 6, and accesses the frame buffer 6 via the selector 14a. On the other hand, the second CRT controller 12b is synchronized by the horizontal synchronizing signal S1 and vertical synchronizing signal S2 output from the first CRT controller 12a, and accesses the video RAM 5 via the selector 14b. The area to be accessed at this time is the area indicated by the broken line in the display data (1) shown in FIG. 4(a). This area has the size of the display screen of the CRT8. In addition, the area specification register 131 has information in FIG.
The rectangular area indicated by the broken line shown in c), that is, the area
is specified in advance via the data bus 10c. In this area (■), the second CRT controller 12b is the video RA.
This corresponds to the position where the solid line portion of display data (1) in M5 is scanned. By the way, the area determination circuit 13 counts pulses indicating the absolute position on the display screen of the CRT 8 using a vertical counter 132 and a horizontal counter 133, and updates the vertical count number yc and the horizontal count number xc. go. Therefore, y, comparator 134+y
e comparator 135. X, comparator 136? Xe comparator 1
37 is the area shown in Figure 4(c) by the function in Table 1.
Then, everything is in a "high" state, and the Antogame-1-138
The area in/out notification signal S3 is set to ``high'' via
Since at least one of the signals 137) becomes "low", the intra-area notification signal, which is the output of the AND gate 138, becomes "low".

By the way, the first CR is connected to one input of the selector 14c.
Display data (1) of the frame buffer 6 being accessed by the T controller 12a is input via the data bus 10d. Furthermore, the display data (2) of the video RAM 5 being accessed by the second CRT controller 12b is input to the other input of the selector 14c via the data bus Hoe. The selector lOc selects the display data (1) from the frame buffer 6 when the area inside/outside notification signal S3 from the area determination circuit 13 is "low", that is, when the area ■ shown in FIG. 4(c) is being scanned. and outputs it to the P/S conversion circuit 7 via the data bus 10f.

In addition, when the area outside/outside notification signal S3 is "high", that is, when the area ■ shown in FIG. Output to conversion circuit 7. The P/S conversion circuit 7 converts the input display data from parallel data to serial data and transfers it to the CRT 8 via the serial data line 11. C
The RT8 displays input display data on the display screen as shown in FIG. 4(d).

When it is desired to change the screen displayed in this way to a display screen as shown in FIG. The range to be displayed may be specified in the dashed line area of display data (1) shown in FIG. 5(a). This is performed by changing the scanning start address of the second CRT controller 12b. That is, Fig. 4 (
The start address in the case of the display screen shown in d) is the di of display data (1), as shown in FIG. 4(a).
The position of the character H11 is, but if you want to scroll as shown in Figure 5 (b), change the position to Figure 5 (a).
As shown in 5 display data (1), change the address to the character 11 K IT, and from this address to the second C
The video RAM 5 may be scanned by the RT controller 12b.

In this way, scrolling only within the divided rectangular areas on the display screen of the CRT 8 can be performed without the need to transfer display data from the video RAM 5 to the frame buffer 6 as in the conventional case.

Although vertical scrolling has been described in the above embodiments, horizontal scrolling is also possible.

In this case, by changing the start address from the address of the characters "I-(" in the display data (1) shown in Figure 4(,) to the address of the characters 11179, the horizontal direction for one character can be changed. You can scroll.

In the above explanation, the case where two CRT controllers and one area determination circuit are used is described, but if n CRT controllers are used and m area determination circuits are used,
It can be easily inferred that one of n CRT controllers can be assigned to each of n arbitrary rectangular areas.

(Effects of the Invention) As described in detail above, according to the present invention, the display screen can be divided and displayed, and scrolling within a certain arbitrary area can be executed without data transfer from the storage means to the buffer means, so that personal computers etc. It can be effectively used as a means to realize multi-windows used in For example, on a display screen where multiple windows are displayed overlapping each other, the window with the highest priority, that is, the display data within the area of the window that is located at the top of the overlapping windows and that you are currently viewing, will be instantly displayed. It is possible to scroll to. or.

In addition to scrolling, it is also possible to instantly display completely different display data within an area. These can be done by changing the area scanned by the controller that manages the area, that is, by changing the start address of the controller's scan.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an internal block diagram of the area determination circuit shown in FIG. 1, FIG. 3 is an explanatory diagram of the elements of the area designation register, and FIGS. (d) is an explanatory diagram of the operation of the device of the embodiment shown in FIG. 1, FIGS. 5(a) and (b) are explanatory diagrams of the scrolling operation of the embodiment of FIG. 1, and FIG. The configuration diagram, FIG. 7 is an explanatory diagram of the operation of the conventional device, and FIGS. 8(a) to (c) are explanatory diagrams during conventional scrolling. 1... Processor, 2... DMA controller. 5... Video RAM, 6... Frame buffer,
7...P/S conversion circuit, 8...CRT. 90~9g...address bus. 10 c = 10 f...data bus. 11...Serial data lines, 12a, 12b'', CRT controller. 13...Area determination circuit, 14a to 14c...Selector, Sl...Horizontal synchronizing signal, S2...Vertical synchronizing signal, S3... ...Inside/outside area notification signal. f1t!l9AJ area 51^V poem four times to the confirmation figure Fig. 2 Fig. 3 (a) (d) 5: Bit jl! RAM and (a) (b), heart V
F7'1^S〃Roll time 9z11 Figure 5 (a) (c) Ling Bing Mu's movement 4,000 tg F4I! ! Figure 7 (Q) (c) Japanese ship Sugeroll Time 9 Hina Shigakure Figure 8

Claims (1)

[Scope of Claims] Storage means for storing data for a plurality of screens; buffer means for storing a portion of data for one screen read from the storage means; a display control method for displaying a plurality of screens on one display screen, comprising: a first controller for reading data from the buffer means in accordance with a scanning speed of the display means; a second controller that reads data from the storage means in accordance with the scanning speed of the display means; and a second controller that monitors the scanning position on the display screen of the display and determines whether the scanning position is within a prespecified area. a determining means for selecting data from the first controller and the second controller based on the determination result of the determining means, and outputting the selected data to the display means; A display control method characterized in that the content displayed in the area is changed by changing the area.