JP4525382B2 - Display device and imaging device - Google Patents

Description

  The present invention relates to an image display device and an imaging device, and more particularly, a display device that transfers a plurality of image information by DMA transfer, generates composite image information from the plurality of image information by a combining unit, and displays a composite image. The present invention also relates to an imaging device provided with the display device.

  2. Description of the Related Art Conventionally, imaging devices such as digital cameras and digital video cameras have been provided with a small liquid crystal monitor or the like. On the small liquid crystal monitor or the like, a captured image is displayed and a shooting mode, a shooting date, a camera resolution, EV Various function information such as value, remaining battery level, optical or digital zoom level, and the like are combined and displayed. Such a display technique transfers various function display data stored in advance in a memory built in a control unit of a digital camera together with captured image data to a display control circuit, and displays icons on the top, bottom, left, and right of the monitor screen. And is displayed in text format, and is used to make it easier to visually grasp the current functional state of the imaging apparatus.

  In a digital camera or the like, a common data bus is used for transferring image data and function display data. For this reason, a DMA (Direct Memory Access) transfer technique is employed as a technique for efficiently transferring many processes. In this DMA transfer technology, when various modules constituting a digital camera request various data stored in a memory, each data is directly transferred without requiring a CPU (Central Processing Unit) data read / transfer instruction. Enables data transfer between modules and memory. For this reason, there is an advantage that the control load on the CPU and the amount of data transferred on the data bus are reduced, and the processing of the entire digital camera is accelerated. For example, in Patent Document 1, in a system in which various modules constituting a digital camera share a data bus, a cycle (cycle) in which each module performs data transfer is set in advance, and the priority order of transfer data is the cause. A technique for preventing a transfer delay of specific data is provided.

As a means for combining image data and function display data, for example, as disclosed in Patent Document 2, image data is stored in each of a plurality of VRAMs (Video Random Access Memory) having a storage area matched with a display area of a monitor. Is known, and image data is simultaneously read from these VRAMs, combined, and displayed on a monitor.
JP 2003-132007 A JP 2004-363994 A

  However, text data or icon data for function display such as the shooting mode and shooting date / time is stored in the VRAM as data for the display area of the monitor as an image for one frame. That is, function display data or the like is generally displayed on the periphery or part of the monitor, but is stored in a form having data for other display areas. Therefore, when the object image data and the function display data are combined by the combining circuit, the function display data transferred from the VRAM is an area where the function display is not performed on the monitor, that is, the object image without displaying the function display. Also in the area displaying only the function display data (all data “0”) is sent by DMA transfer, the traffic on the common data bus increases, and the data transfer takes time and is useless. There was a problem of power consumption.

  Furthermore, when the display position of text data, icon data, or the like is changed on the monitor, there is a problem that it takes time because the DMA transfer must be performed after rewriting the storage position of the VRAM.

  An object of the present invention is to enable a DMA transfer of only necessary display data by eliminating unnecessary data transfer in a display device and an imaging device, thereby achieving a reduction in transfer time and a reduction in wasteful power consumption. It is.

In order to solve the above-mentioned problem, the invention described in claim 1 includes a first storage unit that stores first image information, a second storage unit that stores second image information, and the first storage unit. And the first and second image information stored in the second storage means are DMA-transferred to obtain combined image information of the first and second image information, and the obtained by the combining means A display device including display means for displaying composite image information,
Position information storage means for storing display position information of the first image information;
A first DMA transfer means for DMA-transferring the second image information stored in the second storage means to the combining means in units of a predetermined amount of image information, and displaying by the display means;
When the display position of the display means by the first DMA transfer means becomes the display position stored in the position information storage means, the first image information stored in the first storage means is stored. And a second DMA transfer unit that DMA-transfers a predetermined amount of image information to the combining unit and causes the display unit to perform display.

  According to this configuration, the first and second DMA transfer means for performing the DMA transfer for the first image information and the second image information are independently provided, so that the DMA corresponding to the type and characteristic of each image information is provided. You can transfer. In addition, the image processing apparatus includes position information storage means for storing information on a display position at which the first image information is displayed on the display means, and the display position of the second image information on the display means based on the display position information. When the first image information and the display position of the first image information match, the first image information is transferred to the combining unit by the second DMA transfer unit, so that the combining timing of both data can be matched.

The invention according to claim 2 is the display device according to claim 1,
The display position information includes at least head display position information of the first image information displayed on the display means.

  Since the display position information includes the first display position information of the position where the first image information is displayed, the data of the area where the first image information is not displayed on the display means (data that is “0” as data) Need not be stored in the first storage means. Further, when transferring the first image information to the second DMA transfer means, it is possible to reduce the data in the area not displayed on the display means.

The invention described in claim 3 is the display device according to claim 1 or 2,
Each of the first and second DMA transfer means includes at least two buffer memories, and the at least two buffer memories alternately store and output the predetermined amount of image information. .

  The first and second DMA transfer means are provided with at least two buffer memories, which alternately read and transfer image data, so that while one buffer memory is transferring image data, the other The buffer memory can read the next image data.

According to a fourth aspect of the present invention, there is provided an imaging unit that captures subject image information by capturing a subject image, an image information storage unit that stores image information different from the subject image information obtained by the imaging unit, and the subject image Information and the different image information stored in the image information storage means are DMA-transferred to obtain composite image information from the subject image information and the different image information, and the composite image obtained by the composite means An imaging device comprising display means for displaying information,
Position information storage means for storing display position information of the different image information;
A first DMA transfer unit that DMA-transfers the subject image information to the combining unit by a predetermined amount of image information, and displays the image by the display unit;
When the display position of the display means becomes the display position stored in the position information storage means by the first DMA transfer means, the different image information stored in the image information storage means is converted into a predetermined amount of image information. And second DMA transfer means for performing DMA transfer to the combining means and displaying by the display means.

  According to this configuration, the first and second DMA transfer units that perform DMA transfer for subject image information acquired from the imaging unit and for different image information are independently provided, so that DMA transfer according to the characteristics can be performed. Further, the image processing apparatus includes position information storage means for storing display position information on which different image information is displayed on the display means, and based on the display position information, image information different from the display position of the subject image information on the display means. When the display positions coincide with each other, different image information is transferred to the combining unit by the second DMA transfer unit, so that the combining timing of both data can be matched.

  According to a fifth aspect of the present invention, in the imaging device according to the fourth aspect, the different image information stored in the image information storage means is a character, a symbol, an icon representing a function of the imaging device, or a combination thereof It is the image information which consists of.

  According to the invention described in claim 6, in the imaging device according to claim 4 or 5, the display position information includes at least head display position information of the different image information displayed on the display means. Features.

  Since the display position information includes the head display position information of the position where the different image information is displayed, the data of the area where the different image information is not displayed on the display means (data that is “0” as data) is stored in the image information. There is no need to memorize the means. Further, when different image information is transferred to the second DMA transfer means, the transfer data for the area not displayed on the display means can be reduced.

  According to a seventh aspect of the present invention, in the invention according to any one of the fourth to sixth aspects, the first and second DMA transfer units each include at least two buffer memories, and the two buffers The memory stores the predetermined amount of image information alternately and outputs the information alternately.

  The first and second DMA transfer means are provided with at least two buffer memories, which alternately read and transfer image data, so that while one buffer memory is transferring image data, the other The buffer memory can read the next image data.

  According to the first aspect of the present invention, the first and second DMA transfer means for performing the DMA transfer for the first image information and the second image information are independently provided, so that the type of each image information DMA transfer according to the characteristics can be performed. In addition, the image processing apparatus includes position information storage means for storing information on a display position at which the first image information is displayed on the display means, and the display position of the second image information on the display means based on the display position information. When the first image information and the display position of the first image information match, the first image information is transferred to the combining unit by the second DMA transfer unit, so that the combining timing of both data can be matched. As a result, only image data that needs to be combined can be DMA-transferred, the amount of data transferred by DMA and the amount of data stored in the storage means can be reduced, the storage means can be used effectively, and power consumption can be reduced. There is an effect that it is reduced.

According to the second aspect of the invention, since the display position information includes the first display position information of the position where the first image information is displayed, the data of the area where the first image information is not displayed on the display means. It is not necessary to store (data that is “0” as data) in the first storage means. Further, when transferring the first image information to the second DMA transfer means, it is possible to reduce the data in the area not displayed on the display means.
As a result, only image data that needs to be combined can be DMA-transferred, the amount of data transferred by DMA and the amount of data stored in the storage means can be reduced, the storage means can be used effectively, and power consumption can be reduced. There is an effect that it is reduced.

  According to the third aspect of the present invention, the first and second DMA transfer means are provided with at least two buffer memories, which alternately read and transfer image data, so that one of the buffer memories is an image. While the data is being transferred, the other buffer memory can read the next image data. Therefore, there is an effect that the transfer processing speed of the image information is improved.

  According to the invention described in claim 4, each of the first and second DMA transfer units that perform DMA transfer for subject image information acquired from the imaging unit and different image information is independently provided. It is possible to perform DMA transfer according to the type and characteristics of image information. Further, the image processing apparatus includes position information storage means for storing display position information on which different image information is displayed on the display means, and based on the display position information, image information different from the display position of the subject image information on the display means. When the display positions coincide with each other, different image information is transferred to the combining unit by the second DMA transfer unit, so that the combining timing of both data can be matched. As a result, only image data that needs to be combined can be DMA-transferred, the amount of data transferred by DMA and the amount of data stored in the storage means can be reduced, the storage means can be used effectively, and power consumption can be reduced. There is an effect that it is reduced.

  According to the invention described in claim 5, since the different image information is image information composed of characters, symbols, icons or a combination thereof representing the function of the imaging device partially displayed on the display means. It is not necessary to store data in an area not displayed on the means (data “0” as data) in the storage means, and the amount of data to be transferred by DMA can be reduced. In particular, the storage means can be effectively used. And has the effect of reducing power consumption

  According to the sixth aspect of the invention, since the display position information includes the head display position information of the position where the different image information is displayed, the data of the area where the different image information is not displayed on the display means (as data It is not necessary to store “0” data in the image information storage means. Further, when different image information is transferred to the second DMA transfer means, the transfer data for the area not displayed on the display means can be reduced.

  According to the seventh aspect of the present invention, the first and second DMA transfer means include at least two buffer memories, which alternately read and transfer image data, so that one of the buffer memories is an image. While the data is being transferred, the other buffer memory can read the next image data. For this reason, while one buffer memory is transferring image data, the other buffer memory can read the next image data, and there is an effect that the transfer processing speed of the image information is improved.

[First Embodiment]
The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 shows an external configuration of a digital camera 1 to which the present invention is applied. 1A mainly shows the configuration of the front surface (lens side) of the digital camera 1, and FIG. 1B mainly shows the configuration of the back surface.

  The digital camera 1 has a housing having a substantially rectangular shape, and includes a photographing lens 2, an optical finder window 4, a strobe light emitting unit 5, and a self-timer lamp 3 on its front surface, and a shutter 7 and A power key 6 is provided. On the back of the digital camera 1, a mode change switch 8, a menu key 9, a cross key 10, an optical viewfinder 11, a strobe charge lamp 12 and a display device 13 are provided.

  The mode switch 8 switches between a photographing mode for photographing a subject and a reproduction display mode for displaying an image acquired in the photographing mode on the display device 13. The menu key 9 is an input means used for selecting various menus. The cross key 10 is an input means used for selecting various menu functions and performing various operations according to the functions.

  The display device 13 can employ a TFT (Thin Film Transistor) liquid crystal panel, an EL (Electro Luminescence) element, or the like. In the first embodiment, the display device 13 is composed of a color liquid crystal panel with a backlight. . In the shooting mode, a monitoring image acquired through the shooting lens 2 is displayed as an electronic viewfinder, and in the playback display mode, the acquired electronic image is played back and displayed.

Next, the electronic circuit configuration of the digital camera 1 will be described with reference to FIG.
The digital camera 1 includes a control unit 15, a CCD 16, a CCD drive circuit 17, a CDS (Correlated Double Sampling) circuit 18, an A / D (Analog / Digital) conversion circuit 19, a DMA control circuit 20, a storage unit control circuit 21, and a storage unit. 22, YUV conversion circuit 23, resolution conversion circuit 24, compression / decompression circuit 25, recording medium control circuit 26, recording medium 27, display control circuit 28, display device 13, input unit 32, clock circuit 31, and data transfer between each element Are composed of buffers 30a to 30g for relaying and a data bus 33 for connecting these elements.

  The control unit 15 includes a CPU (not shown), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like. The control unit 15 controls the overall operation of the digital camera 1 based on a program stored in the ROM, and supplies control signals to various circuits via the data bus 33. The ROM stores function display data described later in advance. The function display data is read by operating the input unit 32 and stored in the storage unit 22.

  A CCD (Charge Coupled Device) 16 that is an image pickup device captures an optical image through the photographing lens 2 (see FIG. 1A) and acquires an analog signal of the subject image by photoelectric conversion. The analog signal of the subject image is read and read by the readout pulse supplied from the CCD drive circuit 17 based on the pulse signal output from the timing generator 29 that supplies the timing pulse signal to each part of the digital camera 1. The analog signal is sent to the CDS circuit 18.

  The CDS circuit 18 performs correlated double sampling of the analog image signal to remove noise and perform gain adjustment. The gain-adjusted signal is converted into a digital image signal by an A / D (Analog / Digital) conversion circuit 19 and sequentially sent to the buffer 30a and also sent to the storage unit control circuit 21 via the DMA control circuit 20 described later. .

  The storage unit control circuit 21 receives an instruction signal from the control unit 15 or a DMA control circuit 20 described later, and controls writing and reading of information to and from the storage unit 22. The storage unit 22 includes a large capacity storage element such as a DRAM (Direct Random Access Memory), an SDRAM (Synchronous DRAM), an EPROM (Erasable Programmable ROM), or a flash memory (Flash Memory). A storage area is provided for sequentially storing image signals sent from the CCD 16 and storing one frame of image signals. The storage unit 22 also generates YUV image data generated from image data into luminance (Y) and color difference (UV) signals, and resolution-converted YUV image data and YUV images generated by converting the resolution from the YUV image data. Storage areas for storing compressed YUV image data obtained by compressing or expanding data in units of frames are provided. In addition, a storage area for storing function display data stored in advance in the ROM of the control unit 15 and set by operating the input unit 32 is also provided.

  The image data for one frame from the CCD 16 stored in the storage unit 22 is immediately read out via the storage medium control circuit 21 and sent to the YUV conversion circuit 23 via the DMA control circuit 20 and the buffer 30b. The YUV conversion circuit 23 generates YUV image data including a luminance signal (Y) and a color difference signal (UV) from the image data. The generated YUV image data is sent to the storage unit control circuit 21 via the buffer 30c and the DMA control circuit 20, and stored in the storage unit 22.

  Further, when the shutter 7 is operated and a still image or a moving image is instructed, the YUV image data stored in the storage unit 22 is read out via the storage unit control circuit 21 and the DMA control circuit 20. And sent to the compression / decompression circuit 25 via the buffer 30f. The compression / decompression circuit 25 generates compressed image data based on a predetermined data compression / decompression standard. Here, the data compression / decompression standard is, for example, image information in the JPEG standard format for a still image, or motion JPEG or MPEG standard format for a moving image. The compressed image data converted by the compression / decompression circuit 25 is sent to the recording medium control circuit 26 via the buffer 30g and the DMA control circuit 20, and is recorded on the recording medium 27.

  The recording medium 27 is composed of a non-volatile memory that can be attached to and detached from the camera body. For example, the recording medium 27 is composed of a semiconductor memory such as an EPROM (Erasable Programmable ROM) or a flash memory, or a magneto-optical disk. A large number of still images or moving images can be recorded.

  The digital camera 1 displays the subject image acquired from the CCD 16 on the display device 13 as a monitoring image via the display control circuit 28 in the still image or moving image shooting mode. The display device 13 is composed of a color TFT (Thin Film Transistor) liquid crystal display element or the like, and displays images by arranging display pixels in a matrix in the horizontal and vertical directions. Further, the display device 13 serves as an electronic finder (monitor display) at the time of photographing by displaying the subject image acquired from the CCD 16. At this time, a function display indicating the camera function and the like such as shooting conditions and shooting date and time is also displayed superimposed on a part of the display surface.

  The monitoring image can be displayed by generating resolution-converted YUV image data having a resolution suitable for the image size of the display device 13 by the resolution conversion circuit 24 from the YUV image data stored in the storage unit 22. That is, the YUV image data stored in the storage unit 22 is read out via the storage unit control circuit 21 and sent to the resolution conversion circuit 24 via the DMA control circuit 20 and the buffer 30d. The resolution conversion circuit 24 generates image data (resolution conversion YUV image data) corresponding to the number of pixels (image size) of the display device 13 and sends it to the display control circuit 28 via the buffer 30e and the DMA control circuit 20. A subject image is displayed on the display device 13.

  As for data related to the function display of the digital camera, data such as characters, symbols or icons representing each function is stored in advance in the ROM or the like of the control unit 15. These data set in advance are temporarily stored in the storage unit 22 and then sent to the display control circuit 28 via the storage unit control circuit 21 and the DMA control circuit 20. Here, the subject image and the function display image are superimposed on the display device 13 by being synthesized with the resolution-converted YUV image data generated by the resolution conversion circuit 24.

  The clock circuit 31 clocks the current date and time data. The current date and time data clocked by the clock circuit 31 is also one of the data related to the function display of the digital camera. After being stored in the storage unit 22, it is transmitted to the display control circuit 28 via the storage unit control circuit 21 and the DMA control circuit 20, and synthesized with the resolution conversion YUV image data generated by the resolution conversion circuit 24. The subject image and the captured date and time image are displayed in a superimposed manner.

Next, the display control circuit 28 will be described.
The display control circuit 28 includes a first DMA interface control circuit 40, a second DMA interface control circuit 41, a code conversion circuit 43, a synthesis circuit 44, buffers 30h to 30k, and a display timing generator 45.

  The first DMA interface control circuit 40 is internally provided with a memory 42A for storing display position data indicating the position where the function display data is displayed on the display device 13, and the second DMA interface control circuit 41 includes Includes a memory 42B for storing display position data indicating a position where the YUV image data is displayed on the display device 13.

  The function display data for displaying various functions of the digital camera 1 stored in the storage unit 22 is sent to the first DMA interface control circuit 40. Similarly, resolution-converted YUV image data obtained from the CCD 16 stored in the storage unit 22 and subjected to various signal conversions is transmitted to the second DMA interface control circuit 41. Specifically, when the first DMA interface control circuit 40 transmits a DMA request signal and a DMA start address signal to the DMA control circuit 20, the DMA control circuit 20 displays the function from the storage unit 22 via the storage unit control circuit 21. Read data. Thereafter, the function display data and the DMA response signal are transmitted to the first DMA interface control circuit 40.

  On the other hand, when the second DMA interface control circuit 41 transmits the DMA request signal and the DMA start address signal to the DMA control circuit 20, the resolution conversion YUV image data and the DMA response transmitted from the resolution conversion circuit 24 via the DMA control circuit 20 are transmitted. The signal is received.

  The buffers 30h and 30i are supplied with the function display data from the first DMA interface control circuit 40 and store them, and send the stored function display data to the code conversion circuit 43. The code conversion circuit 43 receives the function display data sent thereto. This is converted into an image signal that can be displayed on the display device 13 and supplied to the synthesis circuit 44. The buffers 30h and 30i are configured to alternately transmit / receive function display data in a burst length unit L described later.

  Similarly, the buffers 30j and 30k are supplied with the resolution-converted YUV image data of the subject image data from the second DMA interface 41, and store the stored YUV image data to the combining circuit 44.

  The details of the timing of storing and reading the function display data in the buffers 30h and 30i and the timing of storing and reading the YUV image data in the buffers 30j and 30k will be described later.

  The synthesizing circuit 44 synthesizes the function display data transmitted from the code conversion circuit 43 and the subject image data, and generates image data for one frame that enables the superimposed display of both images. The synthesized image data is output and displayed on the display device 13 in synchronization with the drive timing of the display control circuit 28 controlled by the display timing generator 45 described later.

  The display timing generator 45 includes a horizontal counter 46, a vertical counter 47 and a decoder circuit 48. The horizontal counter 46 and the vertical counter 47 respectively generate a horizontal synchronizing signal and a vertical synchronizing signal based on the reference clock pulse supplied from the timing generator 29, and drive each element of the display control circuit 28 at a predetermined frame period. A synchronization signal to be supplied is supplied via the decoder circuit 48.

Next, the configuration of function display data and subject image data will be described.
FIG. 3A is a schematic diagram showing a state in which the function display data and the subject image data are displayed on the display device 13. “FINE MODE” indicates function display data in the current imaging mode of the digital camera 1, and indicates that shooting is performed with higher image quality than normal image quality (NORMAL MODE). “2005/02/14” also indicates function display data and indicates current year date information (February 14, 2005). These two function display data are combined with the subject image data and displayed. FIG. 3B shows a display state of only subject image data acquired from the CCD 16 and developed in the storage unit 22. FIG. 3C shows a display position where the function display data is displayed on the display device 13.

The subject image data is sequentially subjected to non-interlaced scanning in the horizontal direction on the display device 13 with the upper left corner coordinates C (X ₀ , Y ₀ ) on the screen shown in FIG. Is displayed.

On the other hand, since the function display data is partially displayed on the display device 13, A (X _i , Y _j ) and B which are predetermined coordinate positions on the screen shown in FIG. (X _m , Y _n ) are sequentially displayed as start coordinate positions.

  FIG. 4A shows an enlarged version of “FINE MODE” of the function display data stored in the storage unit 21. This data is divided into four in the horizontal direction and five in the vertical direction with reference to the burst length L of the DMA control circuit 20 at the time of transfer. Each burst length L is composed of eight words as shown in FIG.

Prior to the display, information indicating the display position of the function display data “FINE MODE” displayed on the display device 13 is stored in the memory 42 A of the first DMA interface control circuit 41. FIG. 4C shows the storage state. A (X _i , Y _j ) is stored as the display start position data, and the number of burst lengths L starting from this A and continuing in the horizontal direction is set to H (“4” in the example of FIG. 4C) or the vertical direction The numbers following are stored as AH and AV, respectively, with V (“5” in the example of FIG. 4C).

Similarly, “2005/02/14”, which is the other function display data, stores B (X _m , Y _n ) as scan start coordinate position data, and a series of burst lengths L starting from this B is stored. The numbers that continue in the horizontal direction are stored as BH and BV, respectively, where H is the number that continues in the horizontal direction and V is the number that continues in the vertical direction. Although not shown, the memory 42B of the second DMA interface control circuit 42 also stores the start coordinate position data C (X ₀ , Y ₀ ) and the horizontal and vertical numbers of the subject image.

The operation of the digital camera 1 having the above configuration will be described.
When the digital camera 1 is set to the shooting mode by the operation of the input unit 32, the control unit 15 displays the function display data ("FINE MODE" and the current time data "2005/02" stored in the ROM in advance. / 14 ") is stored in the storage unit 22. In addition, the subject image data acquired by the CCD 16 via the photographing lens 2 is stored in the storage unit 22, and then newly generated as resolution conversion YUV image data by the YUV conversion circuit 23 and the resolution conversion circuit 24. Remembered.

  Each data stored in the storage unit 22 is DMA-transferred to the first DMA interface control circuit 40 and the second DMA interface control circuit 41 via the DMA control circuit 20.

  FIG. 5A is a timing chart showing the scanning timing of the display area of the display device 13. T1, T2, T3 and T4 indicate one horizontal scanning period, respectively. Further, L1, L2, and L3 in T2, T3, and T4 indicate timings for displaying the function display data. FIG. 5B shows in detail the specific data processing timing of data output by the buffers 30h and 30i in the display timings L1, L2 and L3 of the function display data. Note that the remaining amounts of the buffers 30h and 30i in FIG. 5B indicate the input and output status of valid data.

  During the T1 scanning period (see FIG. 5A), no function display data is displayed, so no data is output. At this time, the first DMA interface control circuit 40 outputs a DMA request signal to the DMA control circuit 20 and transmits the address of the first word of the burst length L. The DMA control circuit 20 that has received the DMA request signal accesses the storage unit 22 via the storage unit control circuit 21 based on the address of the first word received simultaneously. Further, the DMA control circuit 20 holds the head address, generates an address in word units incremented (or decremented) in word units, and accesses the storage unit 22. One burst data (consisting of eight words) read by this access is burst transferred to the first DMA interface control circuit 40 together with a DMA response signal. The first DMA interface control circuit 40 to which the burst transfer has been performed first reads this data into the buffer 30h.

  Next, the first DMA interface control circuit 40 transmits the second DMA request signal and the address of the first word of the second burst data to the DMA control circuit 20. The DMA control circuit 20 reads burst data from the storage unit 22 and transmits it to the first DMA interface control circuit 40 in the same way as reading the first burst data. The first DMA interface control circuit 40 causes the buffer 30i to read the second burst data.

  As described above, the buffers 30h and 30i that have received the burst data are in a standby state until the display timing of the stored data.

  In the period T2, the first burst data is output from the buffer 30h at the timing when the display position data of the burst data coincides with the values of the vertical counter (vertical coordinate value) and the horizontal counter (horizontal coordinate value). Is done. When the output of the first burst data from the buffer 30h is completed, the first DMA interface control circuit 40 outputs the third DMA request signal and the start address of the third burst data to the DMA control circuit 20. The DMA control circuit 20 reads the third burst data from the storage unit 22 and transmits it to the first DMA interface control circuit 40 together with the DMA response signal, similarly to the burst data reading described above.

  On the other hand, the transmission of the second burst data from the buffer 30i is started at the same time as the buffer 30h finishes transmitting the first burst data. Thereafter, at the same time as the output of the second burst data is completed, transmission of the third burst data is started from the buffer 30h that has already read the third burst data. While the buffer 30h is transmitting the third burst data, the buffer 30i receives the fourth burst data and waits until the transmission timing. In this way, burst data is alternately output by the buffers 30h and 30i.

The second DMA interface control circuit 41 outputs a DMA request signal and a DMA start address signal to the DMA control circuit 20 from the start coordinate position data C (X ₀ , Y ₀ ) of the subject image, and a DMA response signal and resolution conversion. Subject image data information is received from the circuit 24. Similar to the first DMA interface control circuit 40, the subject image data is alternately output to the buffers 30j and 30k in units of burst length L.

  Thereafter, the function display data output from the buffers 30h and 30i and converted into a display image by the code conversion circuit 43 and the subject image data output from the buffers 30j and 30k are output to the combining circuit 44 to be combined image data. Is generated. Then, the composition circuit 44 outputs the composite image data to the display device 13 and performs composite image display in which the subject image and the function display image are superimposed on the screen. It should be noted that if the display color of the function display image and the subject image in the vicinity or overlapping thereof are similar or the same color, it is difficult to see the contents of the function display, so the function display image is displayed as a white character on a black background, for example. You may synthesize | combine so that it may fit in a to-be-photographed image.

  As described above, according to the digital camera 1 in the first embodiment, it is possible to display function display data only by DMA transfer of data only in a region for displaying function display data. For this reason, conventionally, even when the function display data is displayed on a part of the display screen, data transfer of the entire display area is required. However, only data transfer of the function display data display area is required. It is possible to display suitable function display data. As a result, the data transmission burden on the data bus 33 including the access to the storage unit 22 and the data processing burden on each element are greatly reduced, and there is an effect of effective use of memory bandwidth and power saving.

  Further, by providing the first DMA interface control circuit 40 with the memory 42A for storing the display position data of the function display data, each burst data can be transmitted and received independently. For this reason, even when the display position of the function display data on the display device 13 is changed, the function display data is displayed at a new display position without rewriting the entire function display data as in the prior art. It becomes possible. As a result, there is an effect that a data transmission burden and a processing burden of each element required for generating new data are eliminated.

  Furthermore, since the function display data and the subject data are provided with two buffers, and burst data is alternately transferred, the data is stored in the other buffer while one buffer reads the data. Data can be transferred and output. For this reason, it is possible to perform data transfer even during the data reading period of the buffer, and there is an effect of performing faster data transfer processing.

  In the first embodiment, two buffers for receiving data from the first and second DMA interface control circuits 40 and 41 are provided. However, two or more buffers are provided. Is also possible.

  In addition, a dedicated DMA interface control circuit and a buffer may be provided for each function display data. In this case, the data transfer amount of the function display data can be greatly reduced, and there is an effect of power saving by effective use of the memory bandwidth and reduction of access.

[Second Embodiment]
Next, a second embodiment to which the present invention is applied will be described.
In the digital camera 1 according to the first embodiment, two function display data “FINE MODE” and “2005/02/14” are displayed in different rows (coordinates having different vertical scanning directions). In this case, “FINE MODE” is displayed first, and then “2005/02/14” is displayed at different display timings, so that DMA transfer can be performed smoothly.

In the second embodiment, even when a plurality of function display data (function displays C and D) are displayed in the same scanning direction as shown in FIG. 6, the burst data of the function display data is compared to compare the rasters of the display device. Disclosed is a digital camera including a display device that reduces the amount of data transferred and achieves power saving by performing data transfer in accordance with scanning.
In addition, the part which has the same function as 1st Embodiment uses the same code | symbol, and abbreviate | omits description. Further, various function display data set by operating the menu key 9 and the like (see FIG. 1) and subject image data (resolution-converted YUV image data) obtained through the CCD 16 and subjected to various data processing are stored in the storage unit 22. Since the points stored in are the same as those of the digital camera 1 in the first embodiment, detailed description thereof is omitted.

FIG. 8 is a block diagram showing an electronic circuit configuration of the digital camera 49.
The memory 51A of the first DMA interface control circuit 50 stores various setting values of function displays C and D. More specifically, for each display area, the number of bursts in the horizontal direction, the number of lines in the vertical direction, the unit of burst length L, and display start coordinate data are stored.

Further, the first DMA interface control circuit 50 includes a coordinate counter 52 that updates the value of the display position coordinate based on various setting data stored in the memory 51A every time burst transfer is performed. The coordinate counter 52 is composed of an arithmetic element such as an accumulator. When burst read is performed, the coordinate data stored in the memory 51A of the first DMA interface control circuit 50 is sequentially updated.
FIG. 9 is a schematic diagram showing the update of the display position coordinate value and the like by the coordinate counter 52. In FIG. 9, C and D indicate function displays C and D, and x and y indicate coordinate values of each burst data in the display device 13.

The burst data of the function indications C and D stored in the storage unit 22 is read by the DMA control circuit 20 as follows based on the DMA request signal and the head address transmitted from the first DMA interface control circuit 50. It is like that.
FIG. 7 is an enlarged view of the portions of the function displays C and D extracted from the schematic diagram of the function display shown in FIG. When the data c2 is read following the reading of the data c1 which is the first burst data of the function display C, the data d1 and d2 which are the first burst data of the function display D are read. Read data c3 of display D. In this way, the data c12 are sequentially read in the same manner as the raster scan of the display device 13. The read burst data is transmitted to the first DMA interface control circuit 50 together with the DMA response signal.

The first DMA interface control circuit 49 outputs burst data alternately to the buffers 30h and 30i as in the first embodiment. When the remaining data amount of either the buffer 30h or 30i becomes 0, it is determined which burst data of the function display C or D is to be output. That is, as shown in FIG. 7, the burst read needs to be read in the order of data c1, c2, d1, d2, c3... In accordance with the raster scan of the display device 13. Therefore, it is necessary to perform processing for distinguishing burst data existing on the same scanning line in units of burst data in accordance with the scanning order regardless of the type of data such as function display C or D.
This process is performed by the first DMA interface control circuit 50 based on the display position coordinate data of both function display data stored in the memory 51A built in the first DMA interface control circuit 50. Specifically, it is performed by referring to the display position coordinate data of both function display data updated each time the burst read is repeated, and determining the start address of the burst data to be read from the DMA control circuit 20 next time. Hereinafter, this process will be described.

  FIG. 10 shows that the first DMA interface control circuit 50 controls the DMA control circuit 20 based on the display position coordinate data that is updated every burst read when the remaining data amount of any of the buffers 30h and 30i becomes zero. It is the flowchart which showed the process sequence which determines whether the head address of the DMA request signal to transmit is set to either function display C or D.

  First, when the remaining amount of data in the buffer 30h or 30i is 0 (step S1: YES), the first DMA interface control circuit 40 includes the display position coordinate data of the function displays C and D stored in the memory 51A. The y-coordinate values are compared (step S2).

  When the y-coordinate value of the function display C is lower (smaller) than the y-coordinate value of the function display D (step S2: YES), the head address data of the function display C and the DMA request signal are transmitted to the DMA control circuit 20. (Step S3).

  In step S2, if the y-coordinate value of the function display C is not lower (not smaller) than the y-coordinate value of the function display D (step S2: NO), it is determined whether both y-coordinate values are equal. (Step S4).

  If the y-coordinate values of function display C and D are equal in step S4 (step S4: YES), it is next determined whether the x-coordinate value of function display C is lower than the coordinate value of function display D. (Step S5).

  If the x-coordinate value of the function display C is low (small) at step S5 (step S5: YES), the head address data of the function display C and the DMA request signal are transmitted to the DMA control circuit 20.

  If the x-coordinate value of the function display C is not low (not small) in step S5 (step S5: NO), the head address data of the function display D and the DMA request signal are transmitted to the DMA control circuit 20 (step S6). ).

  Similarly, when the y-coordinate values of the function displays C and D are not equal in step 4 (step S4: NO), the head address data of the function display D and the DMA request signal are similarly transmitted to the DMA control circuit 20. (Step S6).

  After the head address data of the function display C and the DMA request signal are transmitted to the DMA control circuit 20 in step S3, the display counter coordinate data of the function display C is updated by the coordinate counter 52 (step S7).

  Similarly, after the head address data of the function display D and the DMA request signal are transmitted to the DMA control circuit 20 in step S6, the display position coordinate data of the function display D is updated by the coordinate counter 52 (step S8).

  The DMA control circuit 20 that has received the DMA request signal and the start address of the burst data of the function display C (or D) accesses the storage unit 22 via the storage unit control circuit 21, and displays the function display C (or D). Read burst data. Thereafter, it is transmitted to the first DMA interface control circuit 50 together with the DMA response signal.

  The first DMA interface control circuit 50 transmits the received burst data to the buffers 30h and 30i as appropriate. Similarly to the first embodiment, the buffers 30h and 30i alternately transmit burst data to the code conversion circuit 43 in accordance with the synchronization signal supplied from the display timing generator 45. The burst data whose signal format has been converted into the subject image data format (YUV format) by the code conversion circuit 43 is sequentially displayed by the synthesis circuit 44 and synthesized with the subject image data to be generated as synthesized image data. Thereafter, the image is transmitted to the display device 13 and displayed as an image in which the function display image (C, D, etc.) and the subject image are superimposed on the display screen.

  As described above, according to the digital camera 49 in the second embodiment, since the coordinate counter 52 for updating the display position coordinate data of the function display is provided in the first DMA interface control circuit 50, the burst data of the different function display data is stored. A comparison can be made. As a result, in the DMA transfer of function display data, which may cause complicated processing due to a plurality of function displays, in particular, the order of raster scanning of the display device 13 by one DMA interface control circuit and two buffers. It is possible to transfer burst data conforming to. As a result, it is possible to effectively use the circuit with a small circuit scale, reducing the memory bandwidth and the data transmission amount of the data bus 33, and enabling power saving.

  In the second embodiment, as in the first embodiment, the first and second DMA interface control circuits 50 and 41 are provided with buffers 30h and 30i, 30j and 30k, respectively. A configuration in which two or more buffers are provided is also possible.

[Third Embodiment]
In the third embodiment, the present invention is applied to a digital camera having a rotary display device. In the present embodiment, portions having the same functions as those of the digital cameras 1 and 49 shown in the first and second embodiments are denoted by the same reference numerals, and detailed description thereof is omitted.

FIG. 11 shows a digital camera 59 provided with a rotating display device.
FIG. 11A shows a front view of the digital camera 59. The display device 13 of the digital camera 59 is a vari-angle type that is pivotally connected to the housing using a hinge or the like, and as an electronic viewfinder, ensures a display position that is easy for the photographer to see. FIG. 11A shows a rotated state, and the display screen is displayed upside down and left and right opposite to the normal installation state. The photographer or the like observes an image similar to the normal installation state. FIG. 11B shows a rear view in which the display device 13 is accommodated. The display device 13 displays an image in a normal display state.
FIG. 12 shows a display screen such as a function display when the inverted display device is observed from a normal storage state. FIG. 12 corresponds to FIG. 6 in the second embodiment, and F, G, and H in the drawing correspond to function displays and correspond to C, D, and E, respectively, that are function displays in FIG. FIG. 13 shows the function displays E and F in particular extracted and enlarged manner. In the figure, f1, g1, etc. indicate burst data, and arrows indicate the scanning direction and order.
In the reading order of burst data of subject image data and function display data transmitted from the display control circuit to the display device 13, DMA transfer of individual burst data is performed from the forward direction in the same manner as in the normal display state. Thus, the word unit is exchanged, and the burst transfer start address itself is decremented in the reverse direction for each burst transfer.

FIG. 14 shows an electronic circuit configuration of the digital camera 59.
The configuration such as acquisition, storage or data conversion of the subject image data, and storage of the function display data is the same as in the first and second embodiments, and thus detailed description thereof will be omitted. The description will focus on the circuit 20 and the like.

  The display device inversion detection circuit 63 transmits a display device inversion signal to the CPU of the control unit 15 when the display device 13 is inverted by rotation and the display image is turned upside down. The control unit 15 receives this signal and transmits a DMA transfer reverse instruction signal to the display control circuit 28.

In the display control circuit 28, the first DMA interface control circuit 60 transmits the address indicating the burst data of the function display data to be read and the DMA request signal of this data to the DMA control circuit 20, and the function stored in the storage unit 22. The function display data of the displays F, G, and H are acquired and transmitted to the buffers 30h and 30i.
Further, as in the first and second embodiments, burst data is alternately output to the buffers 30h and 30i. When the remaining amount of data in either the buffer 30h or 30i is 0, it is determined which burst data of the function display F or G is to be output. That is, as shown in FIG. 13, since burst read is read in the order of data e6, e5, f6, f5, e4... In accordance with the raster scan of the display device 13, the burst to be read in accordance with this order. This is because it is necessary to distinguish data. The burst data determination process will be described later.

The memory 62A built in the first DMA interface control circuit 60 stores various setting values of the function displays F, G, and H. Specifically, for each display area, the number of bursts in the horizontal direction, the number of lines in the vertical direction, the unit of burst length L, and display start coordinate data on the display device 13 are stored.

The coordinate counter 64 counts the display position coordinate data of the function displays F and G stored in the memory 62A every time a burst read is performed, and sequentially updates them. When the coordinate counter 64 in the third embodiment receives the inversion detection signal from the display device inversion detection circuit 63, the coordinate counter 64 obtains the coordinate value of the last burst data of the function display F, G and H in the normal display state. It is counted as the first display position coordinate data. That is, display start position coordinate data that is upside down, left and right is generated from the display start position coordinate data in the normal display state (that is, the last burst data in the normal display state), and sequentially counted each time a burst read is performed. The display position coordinate data is updated. FIG. 15 schematically shows the update of the display position coordinate data by the coordinate counter 64. In FIG. 15, F and G indicate function displays F and G, and x and y indicate coordinate values of positions where each burst data is displayed on the display device 13.

  As in the first and second embodiments, the buffers 30h and 30i alternately receive function display data in burst units transmitted from the first DMA interface control circuit 60 and output the function display data to the code conversion circuit 43. is there.

Next, when the remaining data amount of either one of the buffers 30h and 30i is 0, the first DMA interface control circuit 60 performs processing regarding which burst transfer of the function display F or G is requested to the DMA control circuit 20. explain.
This processing is determined based on the display position coordinate data of both function display data stored in the memory 62A, as in the second embodiment. That is, by referring to the display position coordinate data of both function display data updated each time the burst read is repeated, the head address of the burst data acquired from the storage unit 22 through the DMA control circuit 20 is determined next. Done.
However, in the third embodiment, since the scanning direction of the display device 13 is reversed, the first address transmitted from the first DMA interface control circuit 60 to the DMA control circuit 20 is the address of the last burst data in the normal state. The difference is that the start coordinates of the display position coordinate data are different from each other, and the display position coordinate data is updated in the opposite manner to the normal state.

  FIG. 16 shows that the first DMA interface control circuit 60 controls the DMA control circuit 20 based on the display position coordinate data that is updated for each burst read when the remaining amount of data in either of the buffers 30h and 30i becomes zero. It is the flowchart which showed the process sequence which determines whether the head address of the DMA request signal to transmit is set as either function display F or G.

  First, when the remaining amount of data in the buffer 30h or 30i is 0 (step S11: YES), the first DMA interface control circuit 60 includes the function display F and G display position coordinate data stored in the memory 62A. The y-coordinate values are compared (step S12).

  If the value of the y coordinate of the function display F is lower (smaller) than the value of the y coordinate of the function display D (step S12: YES), the DMA request signal with the last burst data in the normal state of the function display F as the start address data At the same time, the data is transmitted to the DMA control circuit 20 (step S13).

  If the y-coordinate value of the function display F is not lower (not smaller) than the y-coordinate value of the function display G (step S12: NO), it is determined whether the two y-coordinate values are equal. (Step S14).

  If it is determined in step S14 that the y-coordinate values of the function display F and G are equal (step S14: YES), it is next determined whether the x-coordinate value of the function display F is lower than the coordinate value of the function display G. (Step S15).

  If the x-coordinate value of the function display F is low (small) in step S15 (step S15: YES), the DMA control circuit 20 together with the DMA request signal with the last burst data in the normal state of the function display G as the top address data. Send to.

  If the x-coordinate value of the function display F is not low (not small) in step S15 (step S15: NO), DMA control is performed together with the DMA request signal with the last burst data in the normal state of the function display D as the top address data. The data is transmitted to the circuit 20 (step S16).

  Similarly, when the y-coordinate values of the function indications F and G are not equal in step 14 (step S14: NO), the DMA request signal is set with the last burst data in the normal state of the function indication G as the start address data. At the same time, the data is transmitted to the DMA control circuit 20 (step S16).

  After the head address data of the function display F and the DMA request signal are output to the DMA control circuit 20 in step S13, the display position coordinate data of the function display F is updated in the coordinate counter 64 (step S17).

  Similarly, after the head address data of the function display G and the DMA request signal are transmitted to the DMA control circuit 20 in step S16, the display position coordinate data of the function display G is updated by the coordinate counter 64 (step S18).

  In this way, the function display data transmitted from the buffers 30h and 30i to the code conversion circuit 43 and the subject data output from the second DMA interface control circuit 61 are generated as combined image data by the combining circuit 44. The same composite image as that in the normal state is displayed on the display device 13 whose top, bottom, left and right are reversed.

As described above, according to the digital camera 59 in the third embodiment, the first address transmitted from the first DMA interface control circuit 60 to the DMA control circuit 20 based on the inversion detection signal from the display device inversion detection circuit 63. Is the last burst data in the normal state, the data transfer order can be reversed as the scanning direction is reversed. For this reason, even if the display device 13 is rotated, an image similar to that displayed in a normal state can be displayed.
As a result, even if the display device 13 is a vari-angle type, it is possible to effectively use the circuit with a small circuit scale, reducing the memory bandwidth and the data transmission amount of the data bus, and enabling power saving.

  The first, second, and third embodiments to which the present invention is applied have been described above, but the present invention is not limited to these various examples.

(A) is the schematic which showed the external appearance of the front part of the digital camera in 1st Embodiment. (B) is the schematic which showed the external appearance of the back part of the digital camera in 1st Embodiment. It is the block diagram which showed the electronic circuit structure of the digital camera in 1st Embodiment. (A) is the schematic diagram which showed the display screen of the display apparatus of the digital camera in 1st Embodiment. (B) is a schematic diagram showing the obtained subject data developed and the display start position. (C) is the schematic diagram which showed the display start position of the function display data. (A) is the schematic diagram which divided | segmented and showed the function display in 1st Embodiment in the burst length L. FIG. (B) is a schematic diagram showing one burst data further divided in units of words. (C) is the schematic diagram which showed the memory | storage state of the various setting values of function display data. (A) is the timing chart which showed the display timing of the synchronizing signal of an apparatus display, and function display data. (B) is a timing chart showing the timing of transfer and flow of function display data in the first DMA interface control circuit. It is the schematic diagram which divided | segmented the display screen of the display apparatus in 2nd Embodiment by the burst length L unit, and showed the display area of subject image data and function display data. It is the schematic diagram which showed the data transfer direction of the function display data in 2nd Embodiment. It is the block diagram which showed the electronic circuit structure of the digital camera in 2nd Embodiment. It is the schematic diagram which showed the display position coordinate data memorize | stored in the 1st DMA interface control circuit in 2nd Embodiment, and its update data. FIG. 9 is a flowchart showing a selection process of a leading address of burst data for making a DMA request in a first DMA interface control circuit in the second embodiment. (A) is the schematic which showed the external appearance of the front part of the state which the digital camera in 3rd Embodiment rotated the display apparatus. (B) is the schematic which showed the external appearance of the back part of the state in which the digital camera in 1st Embodiment accommodated the display apparatus. It is the schematic diagram which showed the screen displayed when the display apparatus of the digital camera in 3rd Embodiment was made into the rotation state from the direction which can be observed at the time of a normal accommodation state. It is the schematic diagram which showed the data transfer direction of the function display data displayed when the display apparatus of the digital camera in 3rd Embodiment was made into the rotation state from the direction which can be observed at the time of a normal accommodation state. It is the block diagram which showed the electronic circuit structure of the digital camera in 3rd Embodiment. It is the schematic diagram which showed the display position coordinate data memorize | stored in the 1st DMA interface control circuit in 3rd Embodiment, and its update data. FIG. 10 is a flowchart showing a selection process of a leading address of burst data for making a DMA request in a first DMA interface control circuit according to the third embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 49, 59 Digital camera 2 Shooting lens 3 Self-timer lamp 4 Optical finder window 5 Strobe light emission part 6 Power key 7 Shutter 8 Mode switch 9 Menu key 10 Cross key 11 Optical finder 12 Strobe charge lamp 13 Display device 15 Control part 16 CCD
17 CCD drive circuit 18 CDS circuit 19 A / D conversion circuit 20 DMA control circuit 21 storage unit control circuit 22 storage unit 23 YUV conversion circuit 24 resolution conversion circuit 25 compression / decompression circuit 26 recording medium control circuit 27 recording medium 28 display control circuit 30a , 30b, 30c, 30d, 30e, 30f, 30g, 30h, 30i Buffer 31 Clock circuit 32 Input unit 33 Data bus 40, 50, 60 First DMA interface control circuit 41, 61 Second DMA interface control circuit 42A, 51A, 62A Memory 42B, 62B Memory 43 Code conversion circuit 44 Composition circuit 45 Display timing generator 46 Horizontal counter 47 Vertical counter 48 Decoder circuit 52, 64 Coordinate counter 63, Display device inversion detection circuit

Claims (7)

A first storage means for storing first image information; a second storage means for storing second image information; and the first and second storage means stored in the first and second storage means. A display device comprising: combining means for transferring image information by DMA to obtain composite image information from the first and second image information; and display means for displaying the composite image information obtained by the combining means. And
Position information storage means for storing display position information of the first image information;
A first DMA transfer means for DMA-transferring the second image information stored in the second storage means to the combining means in units of a predetermined amount of image information, and displaying by the display means;
When the display position of the display means by the first DMA transfer means becomes the display position stored in the position information storage means, the first image information stored in the first storage means is stored. A second DMA transfer means for performing DMA transfer to the combining means for each fixed amount of image information and performing display by the display means;
A display device comprising:   The display device according to claim 1, wherein the display position information includes at least head display position information of the first image information displayed on the display unit.   Each of the first and second DMA transfer means includes at least two buffer memories, and the at least two buffer memories alternately store and output the predetermined amount of image information. The display device according to claim 1. Image capturing means for capturing subject image information by capturing a subject image, image information storage means for storing image information different from the subject image information obtained by the image capturing means, and storage in the subject image information and the image information storage means And combining means for obtaining the combined image information from the subject image information and the different image information by DMA transfer with the different image information, and display means for displaying the combined image information obtained by the combining means. An imaging device comprising:
Position information storage means for storing display position information of the different image information;
A first DMA transfer unit that DMA-transfers the subject image information to the combining unit by a predetermined amount of image information, and displays the image by the display unit;
When the display position of the display means becomes the display position stored in the position information storage means by the first DMA transfer means, the different image information stored in the image information storage means is converted into a predetermined amount of image information. Second DMA transfer means for performing DMA transfer to the combining means and performing display by the display means,
An imaging apparatus comprising:   5. The imaging apparatus according to claim 4, wherein the different image information stored in the image information storage means is image information including characters, symbols, icons, or a combination thereof representing functions of the imaging apparatus. .   The imaging apparatus according to claim 4, wherein the display position information includes at least head display position information of the different image information displayed on the display unit.   The first and second DMA transfer units each include at least two buffer memories, and the two buffer memories alternately store and output the predetermined amount of image information. The imaging device according to any one of 4 to 6.

Images