JP2002262175A - Digital camera - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a novel digital camera that can prevent processing failure. SOLUTION: When a through-image is outputted to a monitor 44, thinning processing is applied to high resolution YUV data outputted from a signal processing circuit 22, and low resolution YUV data are generated. The low resolution YUV data of a current frame are written in one bank formed in an SDRAM taking 1/15 second. On the other hand, the low resolution UV data of a preceding frame are read from the other bank taking 1/30 second. That is, data are read twice for 1/15 second. The read low resolution YUV data are outputted from the monitor 44 after the processing of an NTSC encoder 42. Since the data quantity is reduced, no processing failure is caused. Furthermore, since write and read are applied to the different banks, no outrun takes place in the operation and the display image cannot be disturbed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital camera, and more particularly, to a digital camera for displaying, for example, a moving image (through image) of a subject photographed in real time on a monitor.

[0002]

2. Description of the Related Art When displaying a through image of a subject photographed by a digital camera on a built-in monitor, the display image must be updated every 1/30 second according to the NTSC format. For this reason, the image data of each captured frame must be processed in a short time so as to be in time for the update timing. On the other hand, as the number of pixels of the CCD imager increases, the amount of image data in each frame increases, and unless the data processing method is improved, the processing will fail.

For this reason, in a conventional digital camera having one million pixels or more, pixels output from a CCD imager are thinned out when a through image is output. That is, all pixels are read when the shutter button is pressed, but when outputting a through image, the data amount is suppressed by thinning out the pixels.

[0004]

However, in the method of switching the reading method between the output of the through image and the shutter-on, it is difficult to control the CCD imager.
There has been a problem that the circuit configuration is complicated. SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a novel digital camera capable of preventing a failure in processing.

[0005]

SUMMARY OF THE INVENTION The present invention provides a CCD imager having a first resolution.
Output means for outputting a resolution image signal; thinning means for performing a thinning process on the first resolution image signal to generate a second resolution image signal having a lower resolution than the first resolution image signal; a main memory having at least two memory areas Specifying means for selectively specifying each of the two memory areas, main writing means for writing a second resolution image signal into one of the two memory areas based on the output of the specifying means, and The digital camera includes a main reading unit that reads a second resolution image signal from the other of the two memory areas.

[0006]

The output means outputs a first resolution image signal from the CCD imager. The output first resolution image signal is subjected to a thinning process by the thinning means, and as a result, a second resolution image signal having a lower resolution than the first resolution image signal is generated. On the other hand, the designating means selectively designates each of the two memory areas of the main memory. The main writing means writes the second resolution image signal into one of the one memory areas based on the output of the specifying means. Further, the main reading unit reads the second resolution image signal from the other memory area based on the output of the specifying unit.

In one aspect of the present invention, the output means is a first
Outputting a first resolution image signal for one screen every predetermined period;
The main reading means reads the second resolution image signal for one screen every second predetermined period shorter than the first predetermined period. The designating means alternately switches the designated memory area every first predetermined period. In another aspect of the present invention, the first disabling means disables the thinning means in response to the operation of the shutter button. For this reason, the second
A second resolution image signal is output instead of the resolution image signal. When the first resolution image signal for one screen is output from the buffer memory, the second disabling means disables the buffer reading means at this time. Also, in response to the operation of the shutter button, the third disabling means disables the main reading means.

[0008] In another aspect of the present invention, an image corresponding to the second resolution image signal is displayed on a monitor.

[0009]

According to the present invention, since the first resolution image signal is thinned out to generate the low resolution second resolution image signal, the signal processing fails even if the resolution of the CCD imager increases. Does not occur. In addition, when a write operation is performed on one memory area, a read operation is performed on the other memory area. Therefore, even when the operation speeds are different, one operation does not overtake the other operation. No disturbance occurs in the output image.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0011]

Referring to FIG. 1, a digital camera 10 of this embodiment includes a CCD imager 12. A color filter (not shown) is mounted on the front surface of the CCD imager 12. The light image of the subject is passed through this color filter to the CCD
The light is irradiated to the imager 12.

When the operator sets the mode setting switch 56 to the camera side, the system controller 52 sets the camera mode. Then, the CPU 68 activates the signal generator (SG) 16, and the signal generator (SG) 15 outputs a horizontal synchronization signal and a vertical synchronization signal. The TG 14 generates a timing signal based on the output horizontal synchronization signal and vertical synchronization signal,
The CCD imager 12 is driven by a progressive scan method. The CCD imager 12 has a vertical line number of “1”.
024 "and an imager having a horizontal pixel number of" 768 ", and as a result, an XGA resolution camera signal (high resolution camera signal) is output. Take it.

The camera signal output from the CCD imager 12 is a signal in which each pixel has any one color component. Such a camera signal is transmitted to the CDS / AGC circuit 1
The signal is subjected to well-known noise elimination and level adjustment at 4, and then converted to camera data as a digital signal by the A / D converter 16. The signal processing circuit 18 includes the A / D converter 1
6 at the ratio of 4: 2: 2 to the camera data output from Y
UV conversion is performed to generate YUV data (high-resolution YUV data).

When a real-time moving image (through image) of a subject is displayed on the monitor 44, the switch SW1 is
It is connected to the thinning circuit 24 side. That is, the thinning circuit 2
4 is activated when a through image is output. The high-resolution YUV data output from the A / D converter 16 is subjected to thinning processing by the thinning circuit 24, and the number of vertical lines is “76”.
8 "and converted to YUV data (low-resolution YUV data) having the number of horizontal pixels of" 480 ".
Pixel data constituting data is output intermittently.

The low resolution Y output from the thinning circuit 24
The UV data is stored in the buffer 26a via the switch SW1.
Given to. The buffer 28 is a YUV for 128 pixels.
Dual-port SRAM with a capacity equivalent to data
Composed of The low-resolution YUV data is continuously written to the buffer 26a by the buffer writing circuit 22a provided in the signal processing circuit 22. That is, the pixel data is packed so that the missing portion of the pixel due to the thinning is eliminated. Thereby, the pixel pitch becomes equal to that before the thinning processing.

The YUV data written to the buffer 26a is written before being overwritten by subsequent YUV data.
It is read by the memory control circuit 30. The memory control circuit 30 takes in the read YUV data via the bus 28 and then writes it into the SDRAM 38 via the bus 6. The read clock rate is set to four times the write clock rate, and buses 28 and 36 are occupied by the transfer of YUV data from buffer 26a to SDRAM 38 for only 1/4 of the entire period.

The write operation to the SDRAM 38 is shown in FIG.
This will be specifically described with reference to FIG. The read request generation circuit 22b included in the signal processing circuit 22 generates a read request at a predetermined timing. The write request generation circuit 42b included in the NTSC encoder 42 also generates a read request at a predetermined timing. When outputting a through image, the CPU 68 sets the AND circuit 2
A high level gate signal is applied to 2c and 42c.
As a result, the gate is opened, and the read request and the write request are input to the arbitration circuit 30a.
The arbitration circuit 30a arbitrates each request and outputs a predetermined start signal to the processing circuit 30b in order to respond to any of the requests.

When processing a read request, the buffer control circuit 32a supplies an address signal to the buffer 26a in response to the start signal, and reads YUV data from the buffer 26a. The read YUV data is taken into the processing circuit 32b via the bus 28.
The SDRAM writing circuit 34 a
The data is written to the SDRAM 38 via the bus 36.
If the buses 28 and 36 are always occupied, no other processing can be performed. For this reason, the processing circuit 30 b
Each time data writing is completed, an end signal is output to the arbitration circuit 30a, and the buses 28 and 36 are released. The arbitration circuit 32a proceeds to the processing of the next request. In this way, the read request from the signal processing circuit 18 is processed a plurality of times, and one frame of low-resolution YUV data is
/ 15 seconds to be written to the SDRAM 38.

When processing a write request from the NTSC encoder 42, the arbitration circuit 30a outputs a predetermined start signal to the processing circuit 30b in response to the input of the write request. In response, SDRAM read circuit 34b reads YUV data from SDRAM 38. Also, the buffer control circuit 32b
Is written into the buffer 26b. As described above, the processing circuit 30b generates an end signal when the reading of the YUV data for 64 pixels is completed. This opens the buses 28 and 36. Such a process is repeated, and the low-resolution YUV data for one frame is stored in the SDRAM 38 in 1/30 second.
Is read from. Note that the buffer 26b is also formed of a dual-port SRAM, and has a capacity to store YUV data for 128 pixels.

The SDRAM 38 includes a bank A and a bank B as shown in FIG. Bank switching circuit 40
Outputs a bank switching pulse whose level changes every 1/15 second based on the vertical synchronization signal and the horizontal synchronization signal output from the SG 16. The SDRAM write circuit 34a sets the write destination to bank A when the bank switching pulse is at a high level, and sets the write destination to bank B when the bank switch pulse is at a low level. On the other hand, the SDRAM read circuit 34b sets the read destination to bank B when the bank switching pulse is at a high level, and sets the read destination to bank A when the bank switch pulse is at a low level. That is, the write operation and the read operation for the SDRAM 38 are performed complementarily,
When data is written to one bank, data is read from the other bank.

As described above, the writing of one frame of YUV data requires 1/15 second, while the reading of one frame of YUV data is completed in 1/30 second. The level of the bank switching pulse changes every 1/15 second. Therefore, the YU of the current frame is stored in one bank.
While the V data is written, the YUV data of the next frame is repeatedly read twice from the other bank. As described above, since there is a difference between the time required for writing and the time required for reading, if there is only one bank, the read scan will overtake the write scan. Then
A line extending in the horizontal direction appears on the monitor 44.
In this embodiment, in order to solve such a problem,
Two banks are formed in the SDRAM 38, and a write operation and a read operation for each bank are performed complementarily.

A buffer read circuit 42a provided in the NTSC encoder 42 reads the YUV data stored in the buffer 42 at a clock rate 1/4 that of writing. Further, the read YUV data is transferred to NT
Encode in SC format. The encoded data is converted to an analog signal by a D / A converter 54,
Output to the monitor 56. As a result, a through image is displayed on the monitor 56.

Thus, when a through image is output, 1/1
The high-resolution YUV data generated every 5 seconds is thinned out, and the low-resolution Y whose resolution is reduced to about VGA
UV data is output from the thinning circuit 24 every 1/15 second. That is, as the number of pixels decreases, the pixel pitch in the thinned portion increases, and the data amount per unit time decreases. Therefore, the period during which the buses 28 and 36 are occupied for transferring such low-resolution YUV data to the SDRAM 38 is reduced to half of the conventional period. In the conventional manner, since the resolution is reduced at the time of output from the CCD imager 12, the low-resolution YUV data of each frame must be written to the SDRAM 38 in 1/30 second. On the other hand, in this embodiment, since the writing of the low-resolution YUV data of each frame may be completed in 1/15 second, the occupancy of the buses 28 and 36 is reduced to 1/2.
Can be suppressed. That is, similarly to the related art, not only the failure of the processing can be prevented, but also the occupancy of the bus can be suppressed to be higher than that of the related art.

However, the low resolution Y from the SDRAM 38
Since the reading of the UV data must be completed in 1/30 second, the occupancy of the buses 28 and 36 at the time of reading is twice that at the time of writing. In other words, SDRAM
Reading from the memory 38 is performed at twice the speed of writing to the SDRAM 38. Therefore, in this embodiment, two banks are further formed in the SDRAM 38, and the bank for writing and the bank for reading are complementarily switched. Therefore, it is possible to prevent the image quality of the through image displayed on the monitor 44 from deteriorating.

When the operator operates the shutter button 54, the CPU 46 switches the switch SW1 to the signal processing circuit 2.
Connect to 2. Further, the gate signal to the AND circuit 42c shown in FIG. 2 is lowered to a low level to gate the write request. As a result, the thinning circuit 24, the SDRAM read circuit 34b, and the buffer control circuit 32c are disabled. The high-resolution YUV data output from the signal processing circuit 22 is written to the buffer 26a without performing the thinning process. The number of pixels of the high-resolution YUV data is larger than that of the low-resolution YUV data, and the time required for writing to the SDRAM 38 is proportionally longer. However, the occupancy of the buses 28 and 36 is reduced by the amount by which the reading of data from the SDRAM 38 is stopped, and this reduction is allocated to writing data to the SDRAM 38. Therefore, no failure occurs in the process of writing the high-resolution YUV data to the SDRAM 38.

When the writing of the high-resolution YUV data to the SDRAM 38 is completed, that is, when 1/15 second has elapsed since the shutter button 54 was pressed, the CPU 46
The gate signal to the AND circuit 22c shown in FIG. 2 is also lowered to a low level. As a result, the read request is also gated, and the write operation to the SDRAM 38 is also stopped.

The switch SW2 is connected to the black image generation circuit 41 in response to the operation of the shutter button 54. For this reason, black image data is given to the NTSC encoder 42, and the black image is simultaneously
4 is displayed. One frame of high-resolution YUV data stored in the SDRAM 38 is supplied to the JPEG codec 45 via the buffer 26c and subjected to JPEG compression. The compressed data obtained by this is SDRA
After being written to M38 once, it is recorded on the memory card 50. When the recording process is completed, the switch SW2 is returned to the original state, and the level of the gate signal applied to the AND circuit 42c is returned to the high level. For this reason, SDRAM
38, the high-resolution YUV data stored in
The display on the monitor 44 switches from the black image to the frozen image. When the freeze image is displayed, the writing process to the SDRAM 38 has been stopped, and the buses 28 and 36 have free space correspondingly. Therefore, even if the number of pixels of the high-resolution YUV data is larger than that of the low-resolution YUV data, no failure occurs in the processing of the buffer 26b.

The resolution of the monitor 44 is high resolution Y
It is lower than both UV data and low resolution YUV data. For this reason, the NTSC encoder 42 performs a thinning process according to the number of pixels on each of the high-resolution YUV data and the low-resolution YUV data. The CPU 46
Specifically, the flowcharts shown in FIGS. 4 and 5 are processed.
First, in step S1, the DMA of the camera signal processing block
Start. That is, the SG 15 is activated, the switch SW 1 is connected to the thinning circuit 24, and a high-level gate signal is given to the signal processing circuit 22. The signal processing circuit 22 writes the low-resolution YUV data into the buffer 28 and sends a read request to the memory control circuit 3.
Give to 0. As a result, the low-resolution YUV data
It is written to AM34. Next, the CPU 46 starts DMA of the encode block in step S3.
That is, a high-level gate signal is given to the NTSC encoder 42. Therefore, a write request is given to the memory control circuit 30, and the low-resolution YUV data read from the SDRAM 32 is written to the buffer 26b. NTSC encoder 50 further includes buffer 26
The low-resolution UV data written in b is processed, and as a result, a through image is displayed on the monitor 44.

When the shutter button 88 is operated by the operator, the CPU 46 determines "YES" in a step S5.
Is determined. Therefore, in step S7, the switch SW1
And SW2 are connected to the signal processing circuit 22 and the black image generation circuit 41, respectively, and the gate signal applied to the NTSC encoder 42 is lowered to low level in step S9. Therefore, the high-resolution YUV data is written to the SDRAM 38, and a black image is displayed on the monitor 44. In step S11, after the shutter button 54 is pressed, 1 /
It is determined whether 15 seconds have elapsed. Here "YES"
If so, the gate signal applied to the signal processing circuit 22 is lowered from high level to low level in step S13. Therefore, the write operation to the SDRAM 38 is stopped.

Subsequently, in step S15, the high-resolution YUV
Data recording processing is performed, and when the recording processing is completed, “YES” is determined in the step S17. Then, in each of steps S19 and S21, the switch SW2 is returned to the original state, and the gate signal supplied to the NTSC encoder 42 is returned to the high level. Therefore, the monitor 44
, A frozen image is displayed instead of the black image. In step S23, it is determined whether a predetermined time has elapsed since the shutter button 54 was operated. If "YES", the switch SW1 is returned to its original state in step S25, the level of the gate signal applied to the signal processing circuit 22 is returned to its original state in step S27, and the process returns to step S5. As a result, the through image is displayed on the monitor 44 again.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a part of the embodiment in FIG. 1;

FIG. 3 is an illustrative view showing an SDRAM;

FIG. 4 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 5 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Digital camera 22 ... Signal processing circuit 24 ... Thinning-out circuit 28,36 ... Bus 30 ... Memory control circuit 38 ... SDRAM 42 ... NTSC encoder

Claims (6)

[Claims] A CCD imager having a first resolution; output means for outputting a first resolution image signal from the CCD imager;
Thinning means for generating a second resolution image signal having a lower resolution than the resolution image signal; a main memory having at least two memory areas; designating means for selectively designating each of the two memory areas; output of the designating means Main writing means for writing the second resolution image signal into one of the two memory areas based on
A digital camera, comprising: main reading means for reading the second resolution image signal from the other of the two memory areas. 2. The output unit outputs the first resolution image signal for one screen every first predetermined period, and the main reading unit outputs one screen every second predetermined period shorter than the first predetermined period. 2. The digital camera according to claim 1, wherein said second resolution image signal is read out. 3. The digital camera according to claim 2, wherein said designating means alternately switches a designated memory area every said first predetermined period. 4. A shutter button, first disabling means for disabling the thinning means in response to operation of the shutter button, and second disabling means for disabling the main reading means in response to operation of the shutter button. 4. The image processing apparatus according to claim 1, further comprising: a disabling unit; and a third disabling unit for disabling the main writing unit when the first resolution image signal for one screen is written in the main memory. Digital camera as described. 5. A first circuit for outputting a first request signal requesting writing of the second resolution image signal to the main memory.
Request signal output means, and second request signal output means for outputting a second request signal for requesting the second resolution image signal to be read from the main memory, wherein the second disabling means includes the second request signal. 5. The digital camera according to claim 4, further comprising second request gate means for gating a signal, and wherein said third disabling means includes first request gate means for gating said first request signal. 6. The digital camera according to claim 1, further comprising a monitor for displaying an image corresponding to the second resolution image signal.