JP2006074115A - Digital camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital camera capable of reducing the power consumption and properly generating image data representing an object field. <P>SOLUTION: Electric charges representing the object field are generated on an imaging surface of a CCD imager 16 through photoelectric conversion. A TG 22 outputs the electric charges generated on the imaging surface from the CCD imager 16 at a rate of one frame per 1/30 second. A signal processing circuit 26 generates image data corresponding to the output electric charges and an LCD monitor 38 displays the through-image on the basis of the generated image data. A CPU 30 turns ON/OFF a prescribed driver provided to the TG 22 when the LCD monitor 38 displays the through-image. Then each of the ON state and the OFF state is continued over a period being an integer multiple of 1/30 second. Setting of the OFF state interrupts the horizontal transfer operation of the CCD imager 16. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital camera, and more particularly to a digital camera that displays a moving image representing an object scene on a monitor in real time.

  An example of a conventional digital camera of this type is disclosed in Patent Document 1. According to this prior art, image data representing an object scene photographed by a CCD imager is written to the SDRAM through a bus. Thereafter, the image data is read from the SDRAM through the bus, and is supplied to the LCD monitor after being encoded by a video encoder. A real-time moving image representing the object scene is displayed on the LCD monitor.

Here, the CCD imager outputs charges at a rate of 1 frame per 1/15 second, while the video encoder performs an encoding process at a rate of 1 frame per 1/30 second. For this reason, banks A and B each having a capacity of one frame are prepared in the SDRAM, and the bank designation is switched every 1/15 seconds. The input image data is written to the designated bank frame by frame, and the output image data is read frame by frame from a bank different from the designated bank. This avoids the phenomenon of overtaking noise appearing in the display image.
Japanese Patent No. 3416536 [H04N 5/225, 5/907, 7/24]

  When a CCD imager that outputs charges at a rate of 1 frame per 1/30 second is applied to the prior art, not only does the bus occupancy rate increase, but the power consumption also increases. Furthermore, if the drive speed that is not assumed by the CCD imager is changed to obtain a frame rate of 15 fps, accurate data processing becomes impossible.

    Therefore, a main object of the present invention is to provide a digital camera that can reduce power consumption and can accurately create image data representing an object scene.

  According to a first aspect of the present invention, there is provided a digital camera having an imaging unit that generates an electric charge representing an object scene image by photoelectric conversion, and outputs the electric charge generated on the imaging plane from the imaging unit at a rate of one screen in a predetermined period. Output means, creation means for creating image data corresponding to the output of the imaging means, display means for displaying an image based on the image data created by the creation means, and output means when display processing is performed by the display means First switching means for switching between a state and an off state is provided.

  The charge representing the object scene image is generated by photoelectric conversion on the imaging surface. The output means outputs the charge generated on the imaging surface from the imaging means at a rate of one screen for a predetermined period. Image data corresponding to the output of the imaging means is created by the creating means, and an image based on the created image data is displayed by the display means. When the display process is performed by the display means, the output means is switched between the on state and the off state by the first switching means.

  The output means executes the charge output operation when in the on state, and stops the charge output operation when in the off state. By stopping the charge output operation, power consumption is reduced. Further, by switching the output means between the on state and the off state, low screen rate image data representing the object scene image is accurately created. The display means displays the object scene image based on the image data thus created.

  A digital camera according to a second aspect of the present invention is dependent on the first aspect, the writing means for writing the image data created by the creating means into the memory, and the writing means in the on state in synchronization with the switching operation of the first switching means. Second switching means for switching between the OFF states is further provided.

  The image data created by the creating means when the output means is in the off state is meaningless data that does not represent the object scene image. A situation in which such meaningless data overwrites significant data representing the object scene image is avoided by the switching operation of the second switching means.

  The digital camera according to the invention of claim 3 is dependent on claim 2, and the creation means issues a write request to the write means every time a predetermined amount of image data is created, and the write means responds to the write request. Then, a predetermined amount of image data is written into the memory, and the second switching means gates the write request in relation to the OFF state. This prohibits writing meaningless data to the memory.

  A digital camera according to a fourth aspect of the invention is dependent on the second or third aspect, and further comprises a reading means for reading out image data to be subjected to display processing from the memory at a rate of one screen per predetermined period. The display means can execute the display process at a rate of one screen for a predetermined period regardless of the switching mode of the first switching means.

  A digital camera according to a fifth aspect of the invention is dependent on any one of the second to fourth aspects, further comprising designation means for changing the area designation every time an ON state appears, and each of the memories stores image data of one screen. A plurality of memory areas having a capacity that can be written, a writing unit writes image data to one of the plurality of memory areas based on a designation result of the designation unit, and a reading unit is a plurality of memories based on the designation result of the designation unit Read image data from the other one of the area.

  Therefore, the image data writing destination and the image data reading destination do not match, and the writing address and the reading address do not collide. As a result, it is possible to avoid a situation in which noise resulting from address collision appears in the display image.

  A digital camera according to a sixth aspect of the invention is dependent on any one of the first to fifth aspects, and the first switching means stops the switching operation with the output means set to the on state when a switching stop command is issued. . Image data representing an object scene image is created at a rate of one screen in a predetermined period.

  A digital camera according to a seventh aspect of the invention is dependent on the sixth aspect, and is responsive to the exposure adjusting operation and the adjusting means for adjusting the exposure condition based on the image data created by the creating means when the exposure adjusting operation is accepted. Issuing means for issuing a switching stop command. When the exposure adjustment operation is accepted, the image data corresponding to the object scene image is created at a rate of one screen for a predetermined period. Thereby, the time required for adjusting the exposure conditions can be shortened.

  The digital camera according to the invention of claim 8 is dependent on claim 6 or 7, further comprising start command issuing means for issuing a switch start command when a period during which no operation is performed reaches a threshold, and the first switch The means starts a switching operation when a switching start command is issued. The switching operation once stopped is resumed when the operation toward the digital camera is not performed over a period corresponding to the threshold value. This eliminates the complexity of the operation.

  A digital camera according to a ninth aspect of the invention is dependent on any one of the first to eighth aspects, and the imaging means includes a vertical transfer register for transferring charges in the vertical direction and a horizontal transfer register for transferring charges in the horizontal direction. The output means includes first drive means for driving the vertical transfer register and second drive means for driving the horizontal transfer register, and the first switching means controls the state of the second drive means. Thus, the vertical transfer operation is executed at a rate of one screen for a predetermined period.

  According to the present invention, power consumption is reduced by stopping the charge output operation. Further, by switching the output means between the on state and the off state, low screen rate image data representing the object scene image is accurately created.

  The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

  Referring to FIG. 1, a digital camera 10 of this embodiment includes an optical lens 12 and a mechanical shutter 14. The optical image of the object scene is irradiated on the imaging surface of the CCD imager 16 through these members in the upside down direction.

  Referring to FIG. 2, the CCD imager 16 is an interline transfer type image sensor. The plurality of light receiving elements (pixels) 16a, 16a,... Formed on the imaging surface respectively correspond to the plurality of color elements forming the primary color filter. Therefore, a charge having color information of any one of R, G, and B is generated by photoelectric conversion in each light receiving element 16a.

  When executing the through image processing for displaying the real-time moving image (through image) of the object scene on the LCD 38, the CPU 30 instructs the TG (Timing Generator) 22 to repeat the pre-exposure and thinning readout. The TG 22 pre-exposes the CCD imager 16 in response to a vertical synchronization signal Vsync output from the SG (Signal Generator) 24 every 1/30 seconds. The TG 22 also reads a part of the charge generated by the pre-exposure to the vertical transfer register 16b, transfers the read charge in the vertical direction, and transfers the charge that has reached the horizontal transfer register 16c in the horizontal direction. As a result, a charge representing the object scene image, that is, a low-resolution raw image signal is output from the CCD imager 16.

  The charge transfer mode of the CCD imager 16 differs depending on the setting state of the mode SW 34. When the normal mode is selected by the mode SW 34, both the vertical transfer operation and the horizontal transfer operation are always permitted. As a result, the raw image signal is output from the CCD imager 16 at a rate of 1 frame per 1/30 second as shown in FIG.

  On the other hand, when the power saving mode is selected by the mode SW 34, the vertical transfer operation is always permitted, but the horizontal transfer operation is switched between the permitted state and the prohibited state every time the vertical synchronization signal Vsync is generated. . When attention is paid to two consecutive frame periods, the horizontal transfer operation is executed in the first one frame period and interrupted in the next one frame period.

  As shown in FIG. 4B, the raw image signal output from the CCD imager 16 changes in the manner of object scene image → black image → object scene image → black image →. As a result, a raw image signal corresponding to the object scene image is obtained intermittently at a rate of 1 frame per 1/15 second.

  The raw image signal output in this way is subjected to a series of processing of noise removal, level adjustment and A / D conversion by the CDS / AGC / AD circuit 18. The CDS / AGC / AD circuit 18 outputs raw image data that is a digital signal. The raw image data is subjected to signal processing such as color separation, white balance adjustment, and YUV conversion by the signal processing circuit 26, thereby being converted into image data in the YUV format. The signal processing circuit 26 issues a write request to the memory control circuit 40 every time a predetermined amount of image data is created.

  The memory control circuit 40 is configured as shown in FIG. The write request from the signal processing circuit 26 is given to one input terminal of the AND gate 40a. A gate pulse from the CPU 30 is given to the other input terminal of the AND gate 40a. The write request is given to the arbitration circuit 40b only when the gate pulse indicates the H level.

  As shown in FIGS. 4A and 4B, the gate pulse is always set to the H level in the normal mode, and between the H level and the L level every time the vertical synchronization signal Vsync is generated in the power saving mode. Switch with. Therefore, in the normal mode, all issued write requests are given to the arbitration circuit 40b. On the other hand, in the power saving mode, only the write request issued in the frame in which the image data representing the subject image is created is given to the arbitration circuit 40b.

  When the write request is approved by the arbitration circuit 40 b, the signal processing circuit 26 provides a predetermined amount of image data to the memory access circuit 40 through the bus 54. A predetermined amount of image data is written into the SDRAM 42 by the memory access circuit 40c. Thus, the image data representing the subject image is stored in the SDRAM 42.

  In the power saving mode, as shown in FIG. 4B, image data representing a black image is created intermittently. However, the image data of the black image is not written in the SDRAM 42, and it is possible to avoid a situation in which significant image data representing the object scene image is overwritten by meaningless image data such as a black image.

  The video encoder 36 repeatedly issues a read request to the memory control circuit 36 in order to read the image data stored in the SDRAM 42 at a rate of 1 frame per 1/30 second. The memory access circuit 40c reads a predetermined amount of image data from the SDRAM 42 each time a read request is approved by the arbitration circuit 40b. The read image data is given to the video encoder 36 through the bus 54. The image data stored in the SDRAM 42 is thus given to the video encoder 36 by a predetermined amount.

  Note that the transfer speed of the image data on the bus 54 is much faster than the processing speed of each of the signal processing circuit 26 and the video encoder 36. For this reason, the image data does not collide on the bus 54, and the data transfer process does not fail.

  The video encoder 36 converts the image data given from the memory control circuit 40 into a composite video signal. The converted composite video signal is applied to the LCD monitor 38 at a rate of 1 frame per 1/30 second. As a result, a through image of the object scene is displayed on the monitor screen.

  More specifically, the SDRAM 42 has two banks A and B each having a capacity capable of storing one frame of image data. The bank switching circuit 44 selects a write bank as a write destination of the image data output from the signal processing circuit 26 and a read bank as a read destination of the image data directed to the video encoder 36 from the vertical synchronization signal from the TG 24. Designate complementarily in synchronization with Vsync.

  Accordingly, when the image data from the signal processing circuit 26 is written into the bank A, the image data directed to the video encoder 36 is read out from the bank B. When the image data from the signal processing circuit 26 is written into the bank B, the image data directed to the video encoder 36 is read out from the bank A.

  However, the period in which the image data representing the object scene image is output from the signal processing circuit 26 differs between the normal mode and the power saving mode. That is, the image data representing the object scene image is created at a rate of 1 frame per 1/30 seconds in the normal mode, and is created at a rate of 1 frame per 1/15 seconds in the power saving mode.

  Therefore, the bank switching circuit 44 switches the bank designation every 1/30 seconds when the normal mode is selected, and switches the bank designation every 1/15 seconds when the power saving mode is selected. The memory access operation is performed as shown in FIG. 5A in the normal mode, and is performed as shown in FIG. 5B in the power saving mode. According to FIG. 5A, for writing one frame image into one bank, one frame image is read out from the other bank. On the other hand, according to FIG. 5B, for writing one frame image to one bank, two frame images are read from the other bank.

  As a result, in both the normal mode and the power saving mode, the write address and the read address do not collide with each other, and noise due to the address conflict does not appear in the through image displayed on the LCD monitor 38.

  Returning to FIG. 1, the Y data of the image data generated by the signal processing circuit 26 is also given to the luminance evaluation circuit 28. The luminance evaluation circuit 28 integrates the given Y data in response to the vertical synchronization signal Vsync, and calculates a luminance evaluation value for each frame. In the normal mode, the luminance evaluation value of the object scene image is always calculated. In the power saving mode, the luminance evaluation value of the object scene image and the luminance evaluation value of the black image are calculated alternately.

  The calculated luminance evaluation value is used for the through image AE process of the CPU 30. When the normal mode is selected, the CPU 30 fetches the luminance evaluation value from the luminance evaluation circuit 28 every time the vertical synchronization signal Vsync is generated, and when the power saving mode is selected, the CPU 30 receives the vertical synchronization signal Vsync twice. The luminance evaluation value is fetched from the luminance evaluation circuit 28 every time it occurs. The acquired luminance evaluation value is always an evaluation value indicating the brightness of the object scene image.

  The CPU 30 calculates the optimum exposure period Tpre based on the luminance evaluation value thus taken, and sets the calculated optimum exposure period Tpre to TG22. The TG 22 performs pre-exposure according to the set optimum exposure period Tpre. As a result, the brightness of the through image displayed on the LCD monitor 38 is appropriately adjusted.

  When the shutter button 32 is half-pressed, the horizontal transfer operation of the CCD imager 16 is always permitted regardless of the setting state of the mode SW 34. Image data representing the scene image is output from the signal processing circuit 26 at a rate of 1 frame per 1/30 second, and the luminance evaluation value indicating the brightness of the scene image is also 1/30 from the luminance evaluation circuit 28. Output every second. The CPU 30 fetches the luminance evaluation value in response to the vertical synchronization signal Vsync, and executes the recording AE process based on the fetched luminance evaluation value. As a result, the optimum exposure period Tmain can be obtained in a short time. That is, by always permitting the horizontal transfer operation, the time required for calculating the optimum exposure period Tmain is shortened.

  When the shutter button 32 is fully pressed, the CPU 30 executes photographing / recording processing. First, the CPU 30 instructs the TG 22 to execute main exposure and all-pixel reading, and instructs the driver 20 to drive the mechanical shutter 14 when the optimum exposure period Tmain has elapsed from the start of main exposure.

  The TG 22 performs a main exposure on the CCD imager 16, and the mechanical shutter 14 blocks light from entering the image sensor 16 at a desired timing. The TG 22 reads all the charges generated by the main exposure after the mechanical shutter 14 is driven. The read charge, that is, the high-resolution raw image signal is subjected to the same processing as described above, and as a result, the high-resolution image data is written in the SDRAM 42.

  Next, the CPU 30 instructs the JPEG codec 46 to perform JPEG compression. The JPEG codec 46 reads high-resolution image data stored in the SDRAM 42 through the memory control circuit 40, compresses the read image data by the JPEG method, and compresses the compressed image data, that is, JPEG data through the memory control circuit 40. Write to.

  Thereafter, the CPU 30 reads the JPEG data from the SDRAM 42 through the memory control circuit 40 and records a JPEG file including the read JPEG data on the recording medium 50 through the I / F 48.

  Note that when accessing the SDRAM 42, both the JPEG codec 34 and the CPU 30 issue requests to the memory control circuit 40. When this request is approved by the arbitration circuit 40b shown in FIG. 3, an access operation via the memory access circuit 40c is executed.

  With reference to FIG. 6A, the configuration of the CCD imager 16 will be described in more detail. The vertical transfer register 16b is formed of a plurality of metals M, M,..., And three metals M are assigned to each light receiving element 16a. One drive pulse V1, V2A, V2B and V3 output from the TG 22 is applied to each metal M.

  When attention is paid to four consecutive pixels in the vertical direction, the three lines assigned to the G / B pixel on the first line (first line) from the bottom or the R / G pixel on the second line (second line) from the bottom. Drive pulses V2B, V1, and V3 are applied to the metal M, respectively. The three metals M assigned to the G / B pixel on the third line (third line) from the bottom or the R / G pixel on the fourth line (fourth line) from the bottom include drive pulses V2A, V1 and V3 is applied to each. When a plurality of pixels continuous in the vertical direction is considered as a set of such four pixels, the driving pulses V1, V2A, V2B, and V3 are given to each of the four pixels in the manner described above.

  The TG 22 is specifically configured as shown in FIG. The count value (horizontal count value) of the H counter 22a is incremented in response to the pixel clock, and reset in response to the horizontal synchronization signal Hsync. The count value (vertical count value) of the V counter 22b is incremented in response to the horizontal synchronization signal Hsync and reset in response to the vertical synchronization signal Vsync. Both the horizontal count value and the vertical count value are used for pulse generation of the decoders 22c to 22l.

  The decoder 22c generates a timing pulse XV1, and the driver 22m generates the above-described driving pulse V1 based on the timing pulse XV1. The decoder 22d generates a timing pulse XV3, and the driver 22n generates the above-described driving pulse V3 based on the timing pulse XV3.

  Decoders 22e, 22f, 22g and 22h generate timing pulses XV2A, XSGA, XV2B and XSGB, respectively. The driver 22o generates the above-described drive pulse V2A based on the timing pulses XV2A and XSGA. The driver 22p generates the above-described drive pulse V2B based on the timing pulses XV2B and XSGB.

  The decoder 22i generates a timing pulse XSUB. The driver 22q generates a charge sweeping pulse SUB based on the timing pulse XSUB from the decoder 22i and the exposure period data from the CPU 30.

  Decoders 22j and 22k generate timing pulses XH1 and XH2, respectively. The driver 22r generates a drive pulse H1 for driving the horizontal transfer register 16c based on the timing pulse XH1. Similarly, the driver 22s generates a drive pulse H2 for driving the horizontal transfer register 16c based on the timing pulse XH2. The decoder 22l generates a timing pulse XRG, and the driver 22t outputs a reset gate clock RG based on the timing pulse XRG.

  The charge generated by each light receiving element 16a is read to the vertical transfer register 16b by the timing pulse XV2A or XV2B. The charges on the vertical transfer register 16b are transferred in the vertical direction by drive pulses V1 and V3 and timing pulses XV2A and XV2B. The charges that have reached the horizontal transfer register 16c are transferred in the horizontal direction by the drive pulses H1 and H2. The signal level defined by the amount of charge is reset by the reset gate clock RG.

  When the through image processing according to the power saving mode is executed, the charge sweep-out pulse SUB and the drive pulses V1, V2A, V2B, and V3 are synchronized with the vertical synchronization signal Vsync shown in FIG. 8A or FIG. 9A. 8B, FIG. 8C, FIG. 8D, FIG. 8E and FIG. 8F, or FIG. 8B, FIG. 8C, FIG. 8D, This occurs in the manner shown in FIGS. 8E and 8F. Further, the drive pulses H1, H2 and the reset gate clock RG are generated in the manner shown in FIG. 8G or FIG. 9G.

  The charge sweep-out pulse SUB is repeatedly generated until the pre-exposure is started. The charges generated by each light receiving element 16a are swept away to the drain (not shown) by the charge sweeping pulse SUB. When pre-exposure is started, the output of the charge sweep-out pulse SUB is interrupted. As a result, charges are accumulated in each light receiving element 16a.

  The pre-exposure is completed by reading out the charges in response to the SG component shown in FIG. 8D or FIG. 9D. The SG component is a component corresponding to the timing pulse XSGA output from the decoder 22f, and is generated almost simultaneously with the generation of the vertical synchronization signal Vsync.

  As shown in FIG. 6A, the drive pulse V2A is assigned to the pixels on the third line and the fourth line, and the drive pulse V2B is assigned to the pixels on the first line and the second line. Therefore, when a through image is output, the charge is read to the vertical transfer register 16b as shown in FIG.

  The charges read out to the vertical transfer register 16b are transferred in the vertical direction by the drive pulses V1, V2A, V2B and V3. The charges that have reached the horizontal transfer register 16c are transferred in the horizontal direction by the drive pulses H1 and H2 and output from the CCD imager 16. The output level is reset by a reset gate clock RG generated at a predetermined timing.

  However, in the power saving mode, the drivers 22r to 22t are turned on / off every time the vertical synchronization signal Vsync is generated. That is, the outputs of the drive pulses H1, H2 and the reset gate clock RG are switched between the permitted state and the prohibited state every frame period. Accordingly, only the charges that have reached the horizontal transfer register 16c during one frame period when the drivers 22r to 22t are turned on are output from the CCD imager 16 by horizontal transfer.

  When the shutter button 32 shifts to the full-pressed state through the half-pressed state, the charge sweep-out pulse SUB and the drive pulses V1, V2A, V2B, and V3 are synchronized with the vertical synchronization signal Vsync shown in FIG. This occurs in the manner shown in FIGS. 10B, 10C, 10D, 10E, and 10F. Further, the drive pulses H1 and H2 and the reset gate clock RG are generated as shown in FIG.

  When the shutter button 32 is fully pressed, the main exposure is executed. As shown in FIG. 10B, the main exposure is started by the interruption of the charge sweep-out pulse SUB, and is ended by the closing operation of the mechanical shutter 14. During the main exposure, the decoders 22f and 22h output timing pulses XSGA and XSGB, respectively, whereby SG components appear in both the drive pulses V2A and V2B. As a result, the charges generated by all the light receiving elements 16a, 16a,... Are read to the vertical transfer register 16b as shown in FIG. The read charges are then output from the CCD imager 16 through vertical transfer and horizontal transfer.

  The CPU 30 executes in parallel the imaging task shown in FIG. 11, the mode control task shown in FIGS. 12 to 13, and the power saving task shown in FIG. 14 under the control of the multitask OS. Note that control programs corresponding to these tasks are stored in the flash memory 52.

  Referring to FIG. 11, first, initialization processing is performed in step S1, and through image processing is performed in step S3. The power saving flag is reset by the initialization process, and the through image of the object scene is displayed on the LCD monitor 38 by the through image process. The power saving flag is a flag for identifying permission / prohibition of the horizontal transfer operation of the CCD imager 16 and the data writing operation to the SDRAM 42. The power saving flag is in a reset state when the operation is permitted, and in a set state when the operation is prohibited.

  In step S5, it is determined whether or not the shutter button 32 has been half-pressed. If NO, the state of the power saving flag is determined in step S7. If the power saving flag is in the set state, the process directly returns to step S5, and if the power saving flag is in the reset state, the process returns to step S5 through the through image AE process in step S9. The optimum exposure period Tpre for pre-exposure is updated by the process of step S9. As a result, the brightness of the through image is appropriately adjusted.

  If YES is determined in the step S5, a recording AE process is executed in a step S7. As a result, the optimum exposure period Tmain is accurately obtained. In step S13, it is determined whether or not the shutter button 32 has been fully pressed. In step S15, it is determined whether or not the operation of the shutter button 32 has been released. When the operation of the shutter button 32 is released, the process returns to step S5, and when the shutter button 32 is fully pressed, the photographing / recording process is performed in step S17. The main exposure according to the optimum exposure period Tmain is performed by the photographing / recording process, and the image data of the object scene photographed thereby is recorded on the recording medium 46 in a compressed state. When the process of step S17 is completed, the process returns to step S3.

  Referring to FIG. 10, in step S21, the switching cycle of bank switching circuit 44 is set to 1/30 second. The bank switching circuit 44 complementarily switches the write bank and the read bank between the banks A and B each time the vertical synchronization signal Vsync is generated once from the SG 24. In each of steps S23 and S25, it is determined whether or not a mode selection operation has been performed.

  When the power saving mode selection operation is performed, YES is determined in step S23, and the switching period of the bank switching circuit 44 is set to 1/15 seconds in step S27. The bank switching circuit 44 complementarily switches the write bank and the read bank between the banks A and B every time the vertical synchronization signal Vsync is generated twice. In step S29, a power saving task is activated, and then the process proceeds to step S35.

  When the normal mode selection operation is performed, YES is determined in step S25, and the switching period of the bank switching circuit 44 is set to 1/30 seconds in step S31. The bank switching circuit 44 complementarily switches the write bank and the read bank between the banks A and B every time the vertical synchronization signal Vsync is generated once. In step S33, the power saving stops the task, and then proceeds to step S35.

  In step S35, it is determined whether or not the shutter button 32 has been half-pressed. If NO, the process returns to step S23, but if YES, the process proceeds to step S37. In step S37, the switching cycle of the bank switching circuit 44 is set to 1/30 second, and in the subsequent step S39, the power saving task is stopped. That is, when the shutter button 32 is half-pressed, the normal mode is forcibly set.

  In step S41, it is determined whether or not the shutter button 32 has been fully pressed. In step S43, it is determined whether or not the operation of the shutter button 32 has been released. When the shutter button 32 is fully depressed, the process proceeds to step S47 through the standby process of step S45, and when the operation of the shutter button 32 is released, the process returns to step S47 as it is. The standby time in step S45 corresponds to the time required for the photographing / recording process in step S17 in FIG.

  In step S47, it is determined whether or not the currently selected mode is the power saving mode. If YES here, the switching cycle of the bank switching circuit 44 is set to 1/15 seconds in a step S49, and the power saving task is stopped in a step S51. That is, the mode transition executed in response to half-pressing of the shutter button 32 is returned in response to full-pressing or releasing of the shutter button 32. When the process of step S51 is completed, the process returns to step S23. On the other hand, when it is determined NO in step S47, the process returns to step S23 as it is.

  Referring to FIG. 14, it is determined in step S61 whether an activation request has been issued. When the process of step S29 or S51 is executed, it is determined as YES and the process proceeds to step S63. In step S63, it is determined whether or not the vertical synchronization signal Vsync is generated from SG24. If YES, the state of the power saving flag is determined in step S65.

  If the power saving flag is in the reset state, the power saving flag is set in step S67, the horizontal transfer operation of the CCD imager 16 is prohibited in step S69, and the data writing operation to the SDRAM 42 is prohibited in step S71. In step S69, the drivers 22r to 22t shown in FIG. 7 are disabled, and in step S71, the gate pulse directed to the AND gate 40a shown in FIG. 3 is set to L level.

  If the power saving flag is set, the power saving flag is reset in step S73, the horizontal transfer operation of the CCD imager 16 is permitted in step S75, and the data writing operation to the SDRAM 42 is permitted in step S77. In step S75, the drivers 22r to 22t shown in FIG. 7 are activated, and in step S77, the gate pulse directed to the AND gate 40a shown in FIG. 3 is set to H level.

  When the process of step S71 or S77 is completed, it is determined in step S79 whether or not a stop request has been issued. The stop request is issued by the process of step S33 or S39. If NO is determined here, the processes of steps S63 to S77 are repeated. The horizontal transfer operation and the data write operation are permitted / prohibited every time the vertical synchronization signal Vsync is generated. If YES is determined in the step S79, the same processes as in the steps S73 to S85 are executed in the steps S81 to S85, and then the process returns to the step S61.

  15, the digital camera 10 of another embodiment is provided with a timer 54 instead of the mode SW 34, and the CPU 30 replaces the mode control task shown in FIGS. 12 to 13 with the mode control task shown in FIG. 1 is the same as the embodiment in FIG. For this reason, it demonstrates centering around the operation | movement different from FIG. 1 Example.

  Referring to FIG. 16, in step S91, the switching cycle of bank switching circuit 44 is set to 1/30 second. The bank switching circuit 44 complementarily switches the write bank and the read bank between the banks A and B each time the vertical synchronization signal Vsync is generated once from the SG 24. In step S93, the timer 54 is reset and started. The timer 54 starts measuring time.

  In step S95, it is determined whether or not the measurement time of the timer 54 has reached 10 seconds. In step S97, it is determined whether or not a key such as the shutter button 32 has been operated, that is, whether or not any dynamic operation directed to the digital camera 10 has been performed. If “YES” in the step S95, the process proceeds to a step S99, and if “YES” in the step S97, the process returns to the step S93. Note that “10 seconds”, which is the determination criterion in step S95, is much longer than the time required for shooting / recording processing.

  In step S99, the switching period of the bank switching circuit 44 is set to 1/15 seconds, and in the subsequent step S101, a power saving task is activated. The bank switching circuit 44 complementarily switches the write bank and the read bank between the banks A and B every time the vertical synchronization signal Vsync is generated twice. The permission / prohibition of the horizontal transfer operation of the CCD imager 16 and the permission / prohibition of the data writing operation to the SDRAM 42 are switched every time the vertical synchronization signal Vsync is generated.

  In step S103, a determination operation similar to that in step S97 is performed. If “YES” here, the switching period of the bank switching circuit 44 is set to 1/30 seconds in a step S105, and the power saving task is stopped in a step S107. The bank switching circuit 44 complementarily switches the write bank and the read bank between the banks A and B every time the vertical synchronization signal Vsync is generated once. Further, the horizontal transfer operation of the CCD imager 16 and the data write operation to the SDRAM 42 are always permitted. When the process of step S107 is completed, the process returns to step S93.

  As can be understood from the above description, the charge representing the object scene image is generated by photoelectric conversion on the imaging surface of the CCD imager 16. The TG 22 outputs the charge generated on the imaging surface from the CCD imager 16 at a rate of 1 frame per 1/30 second. Image data corresponding to the output charge is created by the signal processing circuit 26, and a through image based on the created image data is displayed on the LCD monitor 38.

  When the through image is displayed on the LCD monitor 38, the drivers 22r to 22t provided in the TG 22 are turned on / off by the CPU 30 (S69, S75). Each of the on and off states continues for a period of an integer multiple of 1/30 seconds.

  The drivers 22r to 22t set in the on state perform the horizontal transfer operation over a period of an integral multiple of 1/30 seconds, and the drivers 22r to 22t set in the off state have a period of an integral multiple of 1/30 seconds. The horizontal transfer operation is stopped for a while.

  By stopping the horizontal transfer operation, power consumption is reduced. In addition, the drivers 22r to 22t are switched between the on state and the off state, and the period in which each of the on state and the off state is continued is set to an integral multiple of 1/30 seconds, thereby reducing the low field representing the object scene image. Frame rate image data is created. The LCD monitor 38 displays an object scene image based on the image data thus created.

  In this embodiment, the horizontal transfer operation and the data write operation are permitted / prohibited every 1/30 seconds. However, as long as the permission period and the prohibition period are integer multiples of 1/30 seconds, Not limited.

It is a block diagram which shows the structure of one Example of this invention. It is an illustration figure which shows an example of a structure of the CCD imager applied to the FIG. 1 Example. FIG. 2 is a block diagram showing an example of a configuration of a memory control circuit applied to the embodiment in FIG. 1. (A) is a timing chart showing a part of the operation of FIG. 1 embodiment in the normal mode, and (B) is a timing chart showing a part of the operation of the FIG. 1 embodiment in the power saving mode. (A) is an illustrative view showing a part of the operation of the FIG. 1 embodiment in the normal mode, and (B) is an illustrative view showing a part of the operation of the FIG. 1 embodiment in the power saving mode. (A) is an illustrative view showing a part of the configuration of the CCD imager shown in FIG. 2, (B) is an illustrative view showing an example of a distribution state of charges read to the vertical transfer register, (C) FIG. 10 is an illustrative view showing another example of a distribution state of charges read out to the vertical transfer register. It is a block diagram which shows an example of a structure of TG applied to the FIG. 1 Example. (A) is a timing chart showing an example of the generation timing of the vertical synchronization signal Vsync, (B) is a timing chart showing an example of the generation timing of the charge sweeping pulse SUB, and (C) is a timing chart of the vertical transfer pulse V1. FIG. 4 is a timing diagram illustrating an example of generation timing, (D) is a timing diagram illustrating an example of generation timing of a vertical transfer pulse V2A, and (E) is a timing diagram illustrating an example of generation timing of a vertical transfer pulse V2B. (F) is a timing chart showing an example of the generation timing of the vertical transfer pulse V3, and (G) is a timing chart showing an example of the generation timing of the horizontal transfer pulses H1, H2 and the reset gate clock. (A) is a timing chart showing another example of the generation timing of the vertical synchronization signal Vsync, (B) is a timing chart showing another example of the generation timing of the charge sweeping pulse SUB, and (C) is a vertical chart. FIG. 4D is a timing chart showing another example of the generation timing of the transfer pulse V1, FIG. 4D is a timing chart showing another example of the generation timing of the vertical transfer pulse V2A, and FIG. 3E is the generation timing of the vertical transfer pulse V2B. FIG. 6F is a timing chart showing another example of the timing chart, FIG. 5F is a timing chart showing another example of the generation timing of the vertical transfer pulse V3, and FIG. 4G is a chart showing generation of the horizontal transfer pulses H1 and H2 and the reset gate clock. It is a timing diagram which shows another example of timing. (A) is a timing diagram showing another example of the generation timing of the vertical synchronization signal Vsync, (B) is a timing diagram showing another example of the generation timing of the charge sweeping pulse SUB, and (C) is a vertical diagram. FIG. 4D is a timing diagram showing another example of the generation timing of the transfer pulse V1, FIG. 4D is a timing diagram showing another example of the generation timing of the vertical transfer pulse V2A, and FIG. 3E is the generation timing of the vertical transfer pulse V2B. FIG. 6F is a timing diagram showing another example of the generation timing of the vertical transfer pulse V3, and FIG. 4G is a timing diagram showing generation of the horizontal transfer pulses H1 and H2 and the reset gate clock. It is a timing diagram which shows another example of timing. It is a flowchart which shows a part of operation | movement of CPU applied to the FIG. 1 Example. It is a flowchart which shows a part of other operation | movement of CPU applied to the FIG. 1 Example. It is a flowchart which shows a part of other operation | movement of CPU applied to the FIG. 1 Example. FIG. 12 is a flowchart showing yet another portion of behavior of the CPU applied to the embodiment in FIG. 1. It is a block diagram which shows the structure of the other Example of this invention. FIG. 16 is a flowchart showing one portion of behavior of a CPU applied to the embodiment in FIG. 15;

Explanation of symbols

10 ... Digital camera 16 ... CCD imager 22 ... TG
28 ... CPU
34… Mode SW
36… LCD
40 ... SDRAM
42: Bank switching circuit 54: Timer

Claims (9)

An imaging means having an imaging surface for generating electric charge representing an object scene image by photoelectric conversion;
An output means for outputting the charge generated on the imaging surface from the imaging means at a rate of one screen in a predetermined period;
Creating means for creating image data corresponding to the output of the imaging means;
A digital display comprising: display means for displaying an image based on the image data created by the creation means; and first switching means for switching the output means between an on state and an off state when display processing is performed by the display means. camera. Writing means for writing image data created by the creating means into a memory; and second switching means for switching the writing means between the on state and the off state in synchronization with the switching operation of the first switching means. The digital camera according to claim 1, further comprising: The creation means issues a write request to the writing means every time a predetermined amount of image data is created,
The writing means writes the predetermined amount of image data to the memory in response to the write request,
3. The digital camera according to claim 2, wherein the second switching means gates the write request in relation to the off state.   4. The digital camera according to claim 2, further comprising a reading unit that reads out image data subjected to the display process from the memory at a rate of one screen during the predetermined period. Further comprising designation means for changing the area designation each time the ON state appears;
The memory has a plurality of memory areas each having a capacity capable of storing image data of one screen,
The writing means writes the image data to one of the plurality of memory areas based on a designation result of the designation means,
The digital camera according to claim 2, wherein the reading unit reads the image data from another one of the plurality of memory areas based on a designation result of the designation unit.   6. The digital camera according to claim 1, wherein the first switching unit stops the switching operation in a state where the output unit is set to the on state when a switching stop command is issued. An adjustment unit that adjusts an exposure condition based on image data created by the creation unit when an exposure adjustment operation is received, and a stop command issue unit that issues the switching stop command in response to the exposure adjustment operation The digital camera according to claim 6. A start command issuing means for issuing a switching start command when a period during which no operation is performed reaches a threshold;
The digital camera according to claim 6 or 7, wherein the first switching means starts the switching operation when the switching start command is issued. The imaging means includes a vertical transfer register that transfers the charge in the vertical direction, and a horizontal transfer register that transfers the charge in the horizontal direction,
The output means includes first driving means for driving the vertical transfer register, and second driving means for driving the horizontal transfer register,
9. The digital camera according to claim 1, wherein the first switching unit controls the state of the second driving unit.

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