JP3338357B2 - Digital camera - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital camera, and more particularly to a digital camera for recording a plurality of continuous still images collectively on a recording medium.

[0002]

2. Description of the Related Art A conventional digital camera is provided with a 350,000 pixel CCD imager, and a timing generator converts an image signal for one frame (one image) into 1/30.
Reading from CCD imager in seconds. That is, the timing generator operates at a clock rate of 12 MHz and reads out an image signal of 350,000 pixels in 1/30 second. In the camera mode, a moving image based on the image signal thus read is displayed on a monitor, and when the shutter button is pressed, the image signal read at that timing is subjected to predetermined signal processing. Was recorded on a recording medium.

[0003]

However, if the number of pixels of the CCD imager is increased without changing the clock rate, it takes a period longer than 1/30 second to read out an image pickup signal. There has been a problem that the shooting interval becomes longer when performing continuous shooting. Therefore, a main object of the present invention is to provide a digital camera capable of shortening a photographing interval during continuous photographing.

[0004]

SUMMARY OF THE INVENTION The present invention relates to an image pickup device having a first number of pixels, readout means for reading out an image pickup signal of a second pixel number smaller than the first number of pixels from the image pickup device, and displaying the image pickup signal on a monitor. A first generating unit for generating a display image signal to be read, and a plurality of image signals read out by the reading unit in response to an instruction from an operator, and then recorded on a recording medium using the read plurality of image signals. A second generating unit configured to generate a recording image signal, wherein the second generating unit includes:
First disabling means for intermittently disabling at least one of the image sensor and the reading means in response to an instruction each time one image signal is read, and an image sensor when a plurality of image signals are output from the image sensor And a second disabling means for continuously disabling at least one of the reading means.

[0005]

In the camera mode for displaying a real-time moving image on a monitor, the timing generator reads out electric charges of about 300,000 pixels from a CCD imager of about 1.2 million pixels. The timing generator operates at a clock rate of 12 MHz, which results in 300,000 pixels of charge being 1/30
Read within seconds. One still image is generated based on the image signal thus read out and output to the monitor. An image pickup signal is read out from the CCD imager every 1/30 second, whereby a moving image is displayed on a monitor.

When the operator sets the pseudo continuous shooting mode and presses the shutter button, the CCD imager intermittently outputs 16 imaging signals. Also at this time, the timing generator reads out the electric charge from the CCD imager by about 300,000 pixels. That is, one image signal is 3
It has 100,000 pixels, whereby the reading of one imaging signal is completed within 1/30 second. The read image signal for one image is subjected to a predetermined thinning process and then written to the internal memory. When the writing is completed, the reading of the next 300,000 pixel charge is started. In this manner, the imaging signals for 16 frames, that is, 1.2 million pixels are stored in the internal memory. The imaging signals for the 16 frames are then subjected to a YUV conversion process as a single imaging signal, whereby 1
A recording image signal of 200,000 pixels is generated. The recording image signals are collectively recorded on the recording medium.

[0007]

According to the present invention, since the image pickup signal of the second pixel number smaller than the first pixel number is read from the image pickup element, even if the number of pixels of the image pickup element is increased, the photographing at the time of continuous photographing is performed. The interval will not be long. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0008]

Referring to FIG. 1, a digital camera 10 of this embodiment includes a CCD imager 12. The CCD imager 12 has approximately 1.2 million pixels, with 1280 pixels and 960 lines in the horizontal and vertical directions, respectively. Therefore, a period of 1 / 7.5 seconds is required to read all pixel signals from the CCD imager 12.

As shown in FIG. 2, a plurality of light receiving portions 12a are formed on the CCD imager 12, and the light receiving portions 12a
Is mounted on the front surface of the complementary color filter 14 in which Ye, Cy, Mg and G are arranged in a mosaic pattern as shown in FIG. Each light receiving unit 12a constitutes each pixel of the CCD imager 12, and one of Ye, Cy, Mg and G is arranged corresponding to each light receiving unit 12a. The illuminated light image passes through the complementary color filter 14 and the CCD imager 12
And is subjected to photoelectric conversion.

As shown in FIG. 2, the CCD imager 12
Are a plurality of light receiving sections 12a corresponding to each pixel and light receiving sections 1
2a, a plurality of vertical transfer registers 12b for vertically transferring the charges which have been photoelectrically converted and accumulated in the vertical transfer register 12b, and a horizontal transfer register arranged at the end of the vertical transfer registers 12b for transferring the charges transferred by the vertical transfer registers 12b in the horizontal direction. A timing generator 16 including a transfer register 12c;
It is driven by a timing signal output from.

Here, as the timing signal, a vertical transfer pulse for reading out charges from the light receiving section 12a to the vertical transfer register 12b and transferring the charges in the vertical direction line by line and the charges in the horizontal transfer register 12c in the horizontal direction one pixel at a time. There are a horizontal transfer pulse for transferring, a sweep pulse for sweeping charge generated in the light receiving section 12a to an overflow drain (not shown) in a non-exposure period, that is, a non-charge accumulation period.

In a camera mode in which a real-time moving image is displayed on the LCD 40, a camera signal in which the number of lines in the vertical direction is thinned to １ ／ is output from the CCD imager 12. That is, when attention is paid to eight lines that are continuous in the vertical direction, the first Cy, Ye,.
Only the signal of the Mg, G ... line is output,
Signals on other lines are swept away. Therefore, CC
1280 pixels × 240 output from the D imager 12
The line camera signals alternately include Cy, Ye,... Lines and Mg, G,.

The operation of the timing generator 16 at this time will be described with reference to FIGS. Since the CCD imager 12 is irradiated with the light image of the subject in the upside-down direction, the line numbers V1 to V each having eight lines as one unit are used.
8 are assigned in order from the bottom as shown in FIG. One photodiode is associated with each pixel, and two registers are associated with each photodiode.
Registers 1A and 1B are supplied with vertical transfer pulses XV1A and XV1B shown in FIGS. 5A and 5B, and registers 2 and 3A are shown in FIGS. 5C and 5D.
Are applied, and registers 3B and 4 are applied with vertical transfer pulses XV3B and XV4 shown in FIGS. 5 (E) and 5 (F).

The timing generator 16 sets the vertical transfer pulse XV1A to a positive level during the period, and reads out charges from the photodiode on the line V1. In addition, during the period, the vertical transfer pulse XV3A is set to the + level, and charges are read from the photodiode on the line V4. When charges are read from the lines V1 and V4 in this manner, the vertical transfer pulses XV1A to XV4 alternate between zero level and negative level, whereby each charge is transferred one line at a time in the vertical direction. . Since the number of lines in the vertical direction is reduced to １ ／, the reading of the camera signal of 1280 pixels × 240 lines is completed within 1/30 second.

The operator operates the mode switch 4
When 8 is set on the camera side, the system controller 4
6 gives the CPU 44 a camera mode setting command. A
Timing generator 16 provided in SIC 42
Is controlled by the CPU 44, and in the camera mode,
The timing signal is output so that the CCD imager 12 outputs only the above-mentioned predetermined line.

The camera signal output from the CCD imager 12 is subjected to well-known noise removal and level adjustment by a CDS / AGC circuit 18. The camera signal subjected to such processing is converted by the A / D converter 20 into 10-bit digital data (camera data) at a clock rate of 12 MHz. In the camera mode, the switch SW1 is connected to the A / D converter 20 side, the switch SW2 is connected to the thinning circuit 26 side, and the thinning rate of the thinning circuit 26 is "1/2" in each of the horizontal direction and the vertical direction. "And" 0 "
Is set to For this reason, the camera data output from the A / D converter 20 is subjected to color separation and YUV conversion by the signal processing circuit 24, and the number of horizontal pixels of the YUV data is thinned to “640” by the thinning circuit 26. .
Then, the YUV data of 640 pixels × 240 lines is
The buffer control circuit 2 via the switch SW2
8 is input. The switching of the switches SW1 and SW2 and the setting of the thinning rate of the thinning circuit 26 are also performed by CP
U44 does.

The buffer control circuit 28 and the buffer 32 are specifically configured as shown in FIG.
Six controllers 28a to 28f are provided in the buffer control circuit 28, and buffers 32a to 32f formed by SRAM are assigned to the respective controllers 28a to 28f. The controllers 28a to 28f have counters 29a to 29f, respectively. These counters 29a
Address data from the CPU 44 is loaded into .about.29f.

The YUV data via the switch SW2 is input to the controller 28a. At the same time, a window signal that defines an effective area of the CCD imager 12 is input from the timing generator 16. Only when the window signal is at a high level,
The YUV data is written into the buffer 32a at a clock rate of 12 MHz, and the same YUV data is written into the buffer 32a.
At a clock rate of 48 MHz. The read YUV data is stored in the SDRAM control circuit 30.
Are input continuously. The controller 28a also receives, from the CPU 44, the start address data of the area in which the YUV data is to be written, and determines the write address of the YUV data based on the start address data. That is, the head address is loaded into the counter 32a, and the counter 32a is incremented at a clock rate of 48 MHz. Then, in parallel with the input of the YUV data, the count value, that is, the write address data is input to the SDRAM control circuit 30 once every four addresses.

More specifically, referring to FIG. 7, the controller 28a firstly outputs a request signal RE shown in FIG.
QUEST is output to the SDRAM control circuit 30. Then, the acknowledgment signal ACKNOLEGE from the SDRAM control circuit 30 shown in FIG.
The identification number (SRAMN) of the buffer 32a shown in FIG.
o. ), The YUV data shown in FIG. 7D and the address data shown in FIG. 7E are output to the SDRAM control circuit 30. The SDRAM control circuit 30 provides an acknowledgment signal ACKNOLEGE and an identification number to all of the controllers 28a to 28f, and only the corresponding controller outputs data according to the identification number. Thus, the SDRAM control circuit 30 also operates as an arbitration circuit.

Any signal or data is exchanged with the SDRAM control circuit 30 via the bus 66. Such exchange of signals or data is performed by the controller 2a in addition to the controller 28a.
8b to 28f are also performed, and the bus 62 or 64 is used for communication with the JPEG codec 56. SD
The RAM control circuit 30 writes the input YUV data to a desired address of the SDRAM 58 via the bus 60. That is, the SDRAM control circuit 3
0 writes the YUV data for four addresses to the four addresses following the address indicated by the input address data. Further, in response to the input of the next address data, the next four addresses of the YUV data are written to the four addresses following the address indicated by the data. Counter 2
9a is loaded with the start address of the display data area shown in FIG. 9, and the YUV data is written into this display data area. The SDRAM control circuit 30 also executes writing at a clock rate of 48 MHz. As described above, access to the SDRAM 30 does not always require address data, but only needs to be provided intermittently.

As shown in FIG. 8, the SDRAM 30 has 512 addresses in the column direction (horizontal direction) and 2048 addresses in the row direction (vertical direction), and each address is 16 bits. The CPU 44 operates in the camera mode in FIG.
Load the start address of each area shown in
30 is mapped as shown in FIG. That is, 30
Display data area of 0 Kbytes, camera data area of about 1.5 Mbytes, JPEG data area of 40 Kbytes, thumbnail data area of 40 Kbytes, 88
A K-byte software work area and a 36-Kbyte character area are formed in the SDRAM 30.

The signal processing circuit 24 has a so-called 4: 2: 2
By the conversion, YUV data is generated as shown in FIG. Y data, U data and V data are 8
Since it is a bit, the data amount of the YUV data for four pixels is 64 bits, that is, four addresses. On average,
The YUV data is 16 bits (2 bytes) per pixel, and 640 pixels × 24 output from the thinning circuit 26
The YUV data of line 0 is 307,200 bytes (30
0K bytes). As described above, since the display data area has a capacity of 300 Kbytes, 640 pixels × 2
The 40 lines of YUV data are properly stored in the display data area.

The YUV data stored in the display data area is read by the SDRAM control circuit 30 when the bus 60 is open. That is, S
Since the DRAM 58 is accessed at a high clock rate of 48 MHz, the YUV data is read while the bus 60 is idle. The SDRAM control circuit 30 uses the same YU to create an image of one frame.
The V data is read twice. At this time, the controller 28b shown in FIG. 6 inputs the address data to the SDRAM control circuit 30 once every four addresses, and
The M control circuit 30 transmits the desired data to 48 MHz
Read at the clock rate of The read YUV data is supplied to the controller 28b, and the clock rate is returned to 12 MHz in the buffer 32b.

YUV output from controller 28b
The data is input to the pseudo framing circuit 34, and each line data is given a predetermined weight. Specifically, 1
The weighting amount for the YUV data input in the first half of the frame period is “0.25”, and the weighting amount for the YUV data input in the second half of one frame period is “0.
As a result, odd-line data and even-line data are pseudo-generated from the respective input line data as shown in FIG. After passing through 36, it is converted into an analog signal by a D / A converter 38. This analog signal, that is, the interlaced scanned YUV signal is output from the output terminal S1 and input to the LCD 40, and is output to the LCD 40 in real time. A moving image is displayed.

When the operator sets the pseudo continuous shooting mode on / off switch 50 to the ON side and presses the shutter button 52 while a moving image is displayed, the system controller 46 issues a pseudo continuous shooting command to the CPU 44. give. The CPU 44 connects the switch SW1 to the buffer control circuit 28 side and connects the switch SW2 to the thinning circuit 22 side. Further, the timing generator 16 is controlled so that a camera signal of 1280 pixels × 240 lines, which is the same as in the above-described camera mode, is output from the CCD imager 12. However, the CPU 44 intermittently disables the timing generator 16. That is, when one camera signal is output for 1/30 second, the timing generator 16 is disabled, and the YUV data corresponding to the output camera signal is output to the SDRAM 5.
8, the timing generator 16 is activated. The activation period is 1/30 second.

Thus, the camera signal including the lines of Cy, Ye,... And the lines of Mg, G,. The timing generator 16 is completely disabled by the CPU 44 when camera signals for 16 frames are obtained after the shutter button 52 is pressed. Note that the CPU 44 may replace the timing generator 16 or add
The D imager 12 may be disabled.

Each camera signal output from the CCD imager 12 is supplied to an A / D converter 20 via a CDS / AGC circuit 18 and is converted into a digital signal. The camera data output from the A / D converter 20 is input to the thinning circuit 22. At this time, the thinning rate of the thinning circuit 22 is set to “0” and “１ ／” in the vertical and horizontal directions, and the number of horizontal pixels of each camera data is reduced from “1280” to “320”. . The thinning circuit 22 outputs the camera data of 320 pixels × 240 lines 16 times, and the switch SW2
To the controller 28a. The head address of the camera data area formed in the SDRAM 58 is also loaded into the controller 28a in response to the operation of the shutter button 52. The controller 28a
In the same manner as described above, the input camera data is temporarily stored in the buffer 32a, and thereafter, together with the address data,
This is given to the RAM control circuit 30. This address data is also generated based on the loaded top address data. Therefore, SDRAM control circuit 30 writes the input camera data in the camera data area shown in FIG.

Each camera data is 320 pixels × 2
It has a data amount of 40 lines. On the other hand, the camera data area has a capacity of about 1.5 Mbytes and 1280 pixels x
960 lines of camera data can be stored. In this camera data area, an odd field area and an even field area are individually formed as shown in FIG.
Each area can store 1280 pixels × 480 lines of camera data. In the pseudo continuous shooting mode, the controller 28a outputs the address data of the odd field area simultaneously with the odd line data, and outputs the address data of the even field area simultaneously with the even line data. That is, the camera data of 320 pixels × 240 lines is distributed to odd field areas and even field areas line by line. The address data is 320 pixels × 1 obtained by dividing each field area into 16 parts.
One of the divided areas for 20 lines is designated, and the odd line data and the even line data are written to the designated divided area. Thus, the camera data area stores 16 camera data as shown in FIG. In FIG. 13, “o” and “e” attached to the respective numbers mean odd and even.

Each camera data obtained in the pseudo continuous shooting mode is 320 pixels × 240 lines,
Each pixel data is 10 bits. In other words, the camera data of 320 pixels × 240 lines is
96,000 bytes (= 320 pixels x 240 lines x 10
Bits / 8 bits), and the data amount for 16 sheets is 15
36000 bytes, that is, 1.5 Mbytes. Therefore, the 16 camera data are stored in the camera data area. Note that, as shown in FIG.
Since each address of M58 is 16 bits, 5 addresses are used for writing camera data for 8 pixels.

When the writing of the camera data for 16 frames is completed, the SDRAM control circuit 30 executes the reading of the camera data according to the address data from the controller 28d. At this time, the controller 28d handles the camera data for 16 frames in the same manner as the camera data for one frame. That is, the controller 28d alternately reads data from the odd-numbered field area and the even-numbered field area line by line without distinguishing each camera data. Therefore, the camera data o1 to o4 and e1 to e4 shown in FIG.
Next, camera data o5 to o8 and e5 to e8 are read. Thereafter, o9 to o12 and e9 to e12,
The camera data is read out in the order of o13 to o16 and e13 to e16. As a result, progressive scan data is obtained in which the camera data for 16 frames is used as the camera data for one frame.

The SDRAM control circuit 30 transmits the read progressive scan data to the controller 2.
8d, and the controller 28d supplies the input progressive scan data to the signal processing circuit 24 via the switch SW1. Thus, Cy, Ye,
Mg and G camera data are subjected to color separation and YUV conversion to generate YUV data of 1280 pixels × 960 lines. The thinning rate of the thinning circuit 26 is determined by the CPU.
By 44, "1/2" and "1/4" are set in the horizontal and vertical directions, respectively. Therefore, the YUV data of 1280 pixels × 960 lines becomes 6
It becomes YUV data of 40 pixels × 240 lines.

At the time when the camera data for 16 frames has been written into the camera data area, the CPU 44 sets the switch SW
2 is switched to the thinning circuit 26 side. For this reason,
The YUV data output from the thinning circuit 26 is input again to the controller 28a via the switch SW2. The controller 28a writes the 16 YUV data into the display data area in the same manner as when displaying a moving image. Therefore, in the display data area,
As shown in FIG. 11, 16 sheets of YUV data are written. Further, at the time when this writing is completed, the controller 28b reads out all the YUV data in the same manner as when displaying a moving image, and
4 is output. As a result, 16 consecutively-frozen freeze images are displayed on the LCD 40.

The YUV data generation process may be performed every time one sheet of camera data is stored in the camera data area. In this case, the number of freeze images displayed on the LCD 40 increases by one every predetermined period. After all the freeze images are displayed on the LCD 40, the controller 28d reads the camera data again from the camera data area. At this time, the odd-numbered field area and the even-numbered field area are alternately scanned line by line in the same manner as described above, and the camera data is read out in groups of four. However, reading is performed every eight lines because of the thumbnail image creation processing and JPEG compression processing performed later. The controller 28d supplies the read progressive scan data for eight lines to the signal processing circuit 24 again. At this time, the CPU 44 sets the thinning rate of the thinning circuit 26 to “0” in both the horizontal direction and the vertical direction. Therefore, 1280 pixels × 8 lines of YU output from the signal processing circuit 24
The V data is returned to the controller 28a as it is.

The YUV data of 1280 pixels × 8 lines is supplied to the SDR control circuit 30 through the SDR control circuit 30.
It is input to the AM 58 and stored in the JPEG work area shown in FIG. Also at this time, the CPU 44
The top address of the work area is loaded into the controller 28a, and the controller 28a
This is given to the RAM control circuit 30. Since the YUV conversion is performed at a ratio of 4: 2: 2, the YUV data of 1280 pixels × 8 lines is 20480 bytes (= 1280
Pixel × 8 lines × 16 bits / 8 bits), ie, 20
K bytes. Therefore, a 40K byte JPEG
The work area has 1280 pixels x 16 lines of YU
V data can be written. In other words, the YUV data for a certain 8 lines is the first half of the JPEG work area.
The following 8 lines of YU are written to the 0K byte area.
The V data is written in the latter half 20 Kbyte area of the JPEG work area.

According to the address data from buffer control circuit 28, SDRAM control circuit 30, as shown in FIG.
Store data separately. Y data for 8 lines is 10
Since it is K bytes, this Y data is stored in the first half of one 20 K byte area, and the U data and V data for 8 lines are each 5 K bytes.
Stored individually in 0K bytes.

When the writing of the YUV data for eight lines is completed in this way, the CPU 44 creates thumbnail image data based on the YUV data for eight lines. There are 10240 pixels (12
If there is YUV data of 80 pixels × 8 lines and 64 pixels (8 pixels × 8 lines) are one block, then 20K
The YUV data in the byte area can be divided into 160 blocks. The CPU 44 controls the SDRAM control circuit 30
And accesses the SDRAM 58 through the CPU and reads out Y data, U data and V data for each block. Then, one pixel of thumbnail data is created from each block. Thereafter, the CPU 44 writes the created thumbnail data via the SDRAM control circuit 30 one pixel at a time in the thumbnail work area shown in FIG. With this, YUV of 20K bytes area
Thumbnail data for 160 pixels is obtained from the data.

When the process of creating thumbnail data for 160 pixels is completed, the SDRAM control circuit 30
According to the address data from the controller 28e, the Y data, U data and V
Data is read out one block (8 pixels × 8 lines). The Y data, U data and V data are individually written in the JPEG work area.
Since U: V = 4: 2: 2, the Y data is first read twice for each block. That is, the Y data is continuously read twice. Next, U data and V data are 1
It is read out block by block. Such read processing is repeatedly executed by the controller 28e, and each read block data is input to the JPEG codec 56 via the bus 62. That is, J
The block data is repeatedly input to the PEG codec 56 in the order of Y data, Y data, U data, and V data. The JPEG codec 56 performs a compression process on the Y data, U data and V data according to the JPEG format for each block. Each time the compression processing for one block is completed, the compressed data is transferred to the bus 6.
2 to the controller 28f.

The head address of the camera data area shown in FIG. 9 is loaded into the controller 28f. Therefore, the controller 28f stores the input compressed data in the camera data area via the SDRAM control circuit 30. SDRAM 58 has YUV
Since some camera data has not been subjected to conversion or compression processing, the compressed data is overwritten in the camera data area so as to avoid such unprocessed camera data. In other words, the compressed data is written on the camera data that has already been compressed. Since the data amount of the compressed data is smaller than the camera data, if the compressed data is written from the beginning of the camera data area, the compressed data will not be written on the unprocessed camera data.

Simultaneously with the compression processing of the eight lines of YUV data stored in the JPEG work area, the controller 28d reads the next eight lines of camera data from the camera data area, and applies a signal processing circuit to the camera data. 24 performs YUV conversion.
Then, the YUV data is written into the JPEG work area by the controller 28a. One 20K
When the compression process is performed on the YUV data stored in the byte area, the newly generated YUV data is stored in the other 20 Kbyte area.

As described above, the work area for JPEG is 4
A memory capacity of 0 Kbytes, that is, 16 lines is secured, and the compression processing of the current YUV data and the generation processing of the next YUV data are performed in parallel. When the compression processing for the 16 camera data stored in the camera data area is completed, compressed data corresponding to the 16 camera data is obtained in the camera data area. At the same time, 16
Thumbnail data corresponding to the pieces of camera data is obtained in the thumbnail work area. After the compression processing for the camera data is completed, the same compression processing is performed on the thumbnail data, and the compressed data is stored in the thumbnail work area.

The CPU 44 reads out each compressed data from the camera data area and the thumbnail work area through the SDRAM control circuit 30 and records it in the flash memory 54. That is, the CPU 44 records the compressed data corresponding to all the camera data in the flash memory 54 at one time. When the shutter button 52 is operated in the pseudo continuous shooting mode,
6 is processed. That is, first, step S
The counter 45 is initialized by 1 and then CC is set in step S3.
It is determined whether the D imager 12 has output a camera signal for one sheet, that is, about 300,000 pixels. Where "N
If "O", the CPU 44
6 is continued to be activated, but if "YES", the timing generator 16 is disabled in step S5, and the counter 45 is incremented in step S7. Subsequently, in step S9, it is determined whether one camera signal output from the CCD imager 12 has been stored in the camera data area. If "YES", it is determined whether or not the count value of the counter 45 is "16" in a step S11. When the count value is "1"
If it is not 6 ", step S13 is performed to perform the next photographing.
Activates the timing generator 16 at step S
Return to 3. On the other hand, if the count value is “16”, 16
It is determined that the shooting for the number of frames has been completed, and the process ends. Since the timing generator 16 is disabled in step S5, if "YES" in step S11, the timing generator 16 continues to be disabled.

According to this embodiment, in the pseudo continuous shooting mode, the number of pixels of one camera signal read from the CCD imager 12 is reduced to about 300,000 pixels, and the camera signal is read in 1/30 second. Even if the number of pixels of the CCD imager 12 increases, the shooting interval during continuous shooting does not increase. In the camera mode for displaying a moving image on the LCD 40 and the pseudo continuous shooting mode, C
Since the method of reading camera signals from the CD imager 12 is common, it is possible to prevent signal processing from becoming complicated in the pseudo continuous shooting mode.

In this embodiment, an image signal in which 16 images are arranged four by four in the vertical and horizontal directions is generated. However, the image signals of a plurality of images are temporally continuous. If you record in one image file,
A moving image can be reproduced by a simple method.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an illustrative view showing a CCD imager;

FIG. 3 is an illustrative view showing a color filter;

FIG. 4 is an illustrative view showing one portion of an operation of the timing generator;

FIG. 5 is a waveform diagram showing a timing signal.

FIG. 6 is an illustrative view showing a buffer control circuit and a buffer;

FIG. 7 is a timing chart showing a part of the operation of the buffer control circuit.

FIG. 8 is an illustrative view showing an SDRAM;

FIG. 9 is an illustrative view showing a mapping state of an SDRAM in a camera mode;

FIG. 10 is an illustrative view showing a head address of each area mapped to the SDRAM in the camera mode;

FIG. 11 is an illustrative view showing YUV data;

FIG. 12 is an illustrative view showing an operation of the pseudo framing circuit;

FIG. 13 is an illustrative view showing a camera data area formed in the SDRAM;

FIG. 14 is an illustrative view showing a display data area formed in the SDRAM;

FIG. 15 is an illustrative view showing a JPEG work area formed in the SDRAM;

FIG. 16 is a flowchart showing a part of the operation in the pseudo continuous shooting mode.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Digital camera 22, 26 ... Thinning-out circuit 28 ... Buffer control circuit 30 ... SDRAM control circuit 54 ... Flash memory 56 ... JPEG codec 58 ... SDRAM

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/225 H04N 5/335 H04N 5/907-5/91

Claims (3)

(57) [Claims] An image sensor having a first number of pixels; reading means for reading an image signal of a second number of pixels smaller than the first number of pixels from the image sensor; a display image signal to be displayed on a monitor from the image signal; A first generation unit for generating, and one recording image to be recorded on a recording medium by using the plurality of read out imaging signals after reading out the plurality of imaging signals by the reading unit in response to an instruction of an operator A second generating unit that generates a signal, wherein the second generating unit intermittently disables at least one of the image sensor and the read unit in response to the instruction each time one of the image signals is read. A first disabling unit that disables at least one of the image sensor and the reading unit when the plurality of image signals are output from the image sensor. Including the means,
Digital camera. 2. The digital camera according to claim 1, wherein said display image signal is a moving image signal. 3. The digital camera according to claim 1, wherein the recorded image signal has the first number of pixels.