JP3515466B2 - Digital camera - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital camera, and more particularly, to a display image signal for displaying on a display based on a camera signal output from an image sensor in response to a photographing instruction and recording on a recording medium. The present invention relates to a digital camera that generates a recorded image signal for recording.

[0002]

2. Description of the Related Art An example of a conventional digital camera of this type is disclosed in Japanese Patent Application Laid-Open No. 11-239321 [H04N5 / 92, 5/90, filed on August 31, 1999].
7]. In this conventional technique, camera data (RAW data) of a subject image is stored in a camera data area of an SDRAM, and display image data (display image signal) for displaying a freeze image on a display and recorded image data to be recorded on a recording medium. (Recorded image signal)
Both of the above were generated based on the camera data stored in the camera data area. At this time, YUV conversion processing and thinning processing for generating a display image signal,
In addition, YUV conversion processing for generating a recorded image signal has been individually performed.

[0003]

However, in the individual signal processing as in the prior art, there is a problem that it takes time to complete the generation processing of both the display image signal and the recorded image signal.

[0004]

A digitizer according to the invention.
The real camera is a live image of the subject taken in response to the shooting instruction.
First writing means for writing the image signal in the first area of the memory, reading means for reading the raw image signal stored in the first area, and YUV format based on the raw image signal read by the reading means first generating means for generating a recording image signal, second generating means for generating an image signal for display by performing zoom processing in the recording <br/> image signal generated by the first generating means, second generating means Display generated by
A second writing means for writing the image signal for writing into the second area of the memory, and a third writing means for writing the image signal for recording generated by the first generating means into the third area of the memory, and to the memory Then together the more than three times the processing speed of the access speed first generating means and the second generating means
To the recording image signal generated by the first generating means.
Give to the second generation means without going through the memory
Was, it is a digital camera.

[0005]

According to the present invention, a display image signal for displaying on a display and a recording image signal for recording on a recording medium based on a camera signal output from an image sensor in response to a shooting instruction. In the digital camera for generating the, the first writing means for writing the camera signal in the first area of the memory, the reading means for reading the camera signal from the first area, and the recording image signal generated based on the camera signal read by the reading means. First generating means, a second generating means for generating a display image signal based on the recorded image signal, a second writing means for writing the display image signal in a second area of the memory, and a recorded image signal in a third area of the memory. A third writing unit for writing is provided, and the access speed to the memory is controlled by the first generating unit and the second generating unit. Characterized in that it has more than three times the speed, a digital camera.

[0006]

The camera signal output from the image sensor in response to the shooting instruction is written in the first area of the memory by the first writing unit and then read by the reading unit. The first generation unit generates a recording image signal based on the read camera signal, and the second generation unit generates a display image signal based on the recording image signal. The generated display image signal is written in the second area of the memory by the second writing unit, and the recording image signal is written in the third area of the memory by the third writing unit.
Here, the access speed to the memory is three times or more the processing speed of the first generation means and the second generation means, and the reading of the camera signal and the writing of the display image signal and the recorded image signal are performed in parallel. .

In one embodiment of the present invention, the buffer memory is accessed at a first clock rate and a second clock rate that is at least three times the first clock rate. The difference between the access speed to the memory and the processing speed of the first generation means and the second generation means is absorbed by this buffer memory.

In another embodiment of the present invention, the second generation means performs a thinning process on the recorded image signal to generate a display image signal.

In another embodiment of the invention, the memory has a single data input / output port.

In still another embodiment of the present invention, the camera signal is a raw image signal in which each pixel has any one color component, and both the display image signal and the recorded image signal are YUV signals.

In another embodiment of the present invention, the output means is
The display image signal is read from the second area and output to the display. Further, the recording means reads the recording image signal from the third area and records it on the recording medium.

[0012]

According to the present invention, the recording image signal is generated based on the camera signal read from the first area of the memory, and the display image signal is further generated based on the recording image signal. Then, the generated recording image signal and display image signal are written in the second area and the third area of the same memory. Therefore, it is sufficient to read the camera signal from the first area only once. The access speed to the memory is three times or more the processing speed of the first generation means and the second generation means, and the reading of the camera signal and the writing of the display image signal and the recorded image signal are performed in parallel. Therefore, it is possible to shorten the time required to generate the display image signal and the recorded image signal and write each image signal into the memory.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a digital camera 10 of this embodiment includes a CCD imager 12. The CCD imager 12 has approximately 1.2 million pixels, with 1280 pixels and 960 pixels in the horizontal and vertical directions, respectively. Therefore, it takes 1 / 7.5 seconds to read the camera signals of all lines from the CCD imager 12. The optical image of the subject is C as shown in FIG.
The light receiving surface of the CCD imager 12 is irradiated with y, Ye, Mg, and G through the color filters 14 arranged in a mosaic pattern.

When the operator switches the mode selector switch 48 to the camera mode side, the system controller 4
6 gives a CPU mode setting command to the CPU 48. Then, the CPU 48 causes the ASIC 42 to display a moving image (through image) of the subject on the LCD 40 in real time.
The timing generator (TG) 16 provided in the above is instructed to perform thinning-out reading.

The TG 16 is a CCD in the thinning-out reading method.
The imager 12 is driven, and the CCD imager 12 outputs a camera signal (raw image signal) in which the number of lines in the vertical direction is thinned to 1/4. In other words, when paying attention to 8 lines that are continuous in the vertical direction, the first Cy, Ye, ...
.. and the fourth Mg, G ... Line pixel signals are output, and the pixel signals of the other lines are swept away. Therefore, in the camera signal of 1280 pixels × 240 lines output from the CCD imager 12, lines of Cy, Ye, ... And Mg, G ...
Lines are included alternately. The number of lines in the vertical direction is 1 /
Since it is thinned out to 4, the time required to output the camera signal of 1280 pixels × 240 lines is 1/30
Seconds.

The camera signal output from the CCD imager 12 is subjected to well-known noise removal and level adjustment by the CDS / AGC circuit 18. Then, the camera signal subjected to such processing is converted into 10-bit digital data (camera data) by the A / D converter 20 at a clock rate of 12 MHz. When outputting a through image, the switch SW1 is connected to the A / D converter 20 side, and the switch SW3 is a thinning circuit (zoom circuit) 2
6a side, and the thinning rate of the thinning circuit 26a is "1 /" in each of the horizontal direction and the vertical direction.
2 "and" 0 ". Therefore, the camera data output from the A / D converter 20 is the signal processing circuit 2
4, color separation and YUV conversion are performed, and the YUV data generated by this is given to the thinning circuit 26a. In the thinning circuit 26a, the number of horizontal pixels of the given YUV data is thinned to "640", and 640 pixels x
240 lines of YUV data is input to the buffer control circuit 28 via the switch SW3. In addition,
The switching of the switches SW1 and SW3 and the setting of the thinning rate of the thinning circuit 26a are performed by the CPU 48.

The buffer control circuit 28 and the buffer 32 are specifically constructed as shown in FIG.
The buffer control circuit 28 is provided with seven controllers 28a to 28g, and buffers 32a to 32g formed by SRAM are assigned to the seven controllers 28a to 28g, respectively. Further, the controllers 28a to 28g have counters 29a to 29g, respectively.
29g is incremented at a clock rate of 48MHz.

When accessing the SDRAM 50, the controllers 28a to 28g first access the access request signal R.
EQUEST is output to the SDRAM control circuit 30. The SDRAM control circuit 30 receives the approval signal A
CKNOLEGE together with the identification number (SRAM No.) of any of the buffers 32a to 32g in the controller 2
Return to 8a-28g. Each controller 28a-28
The g compares the returned identification number with the identification number of the buffer allocated to itself, and only the controller having the same ID accesses the SDRAM 50. When writing,
The desired data is output to the SDRAM control circuit 30 together with the address data, and the desired data is output to the SDRAM.
It is written in the SDRAM 50 by the controller 30. On the other hand, at the time of reading, the address data
Output to the control circuit 30 and the desired data is SDR
It is read from the SDRAM 50 by the AM control circuit 30.

Any signal or data is exchanged between the controller 28a and the SDRAM control circuit 30 via the bus 66. Such signals and data are exchanged not only by the controller 28a but also by the controllers 28b to 28g, and the JPE
The bus 62 or 64 is used for communication with the G codec 56. Further, the SDRAM 50 has only a single data input / output port.

The YUV data of 640 pixels × 240 lines output from the thinning circuit 26a is stored in the controller 28.
Input to a. At the same time, the timing generator 16
From, a window signal that defines the effective area of the CCD imager 12 is input. The controller 28a writes the YUV data to the buffer 32a at a clock rate of 12 MHz only when the window signal is at the high level, and writes the same YUV data from the buffer 32a to 48 MHz.
Read at the clock rate of. The controller 28a also receives the head address data of the display data area shown in FIG. 5 from the CPU 48, and calculates the write address of the YUV data based on the head address data and the count value of the counter 29a. Then, the access request is generated in the above-described manner, and when the access is recognized, the YUV data is output to the SDRAM control circuit 30 together with the write address data. Since the SDRAM is a burst transfer type memory, write address data is output once every four addresses, for example.

The SDRAM control circuit 30 receives the input YUV data from the SDRAM 5 via the bus 60.
Write to the desired address of 0. That is, the SDRAM control circuit 30 writes YUV data for four addresses at four addresses following the address indicated by the input address data. Further, in response to the input of the next address data, the YUV data for the next four addresses is written to the four addresses following the address indicated by the data. The head address of the display data area shown in FIG. 5 is given to the controller 28a, and the YUV data is written in the display data area. The SDRAM control circuit 30 also executes writing at a clock rate of 48 MHz.

As described above, address data is not always required for accessing the SDRAM 30,
Address data may be given intermittently. High-speed access can be realized by the characteristics of the SDRAM 30 and the clock rate of 48 MHz.

As shown in FIG. 4, the SDRAM 30 has 512 addresses in the column direction (horizontal direction) and 8192 addresses in the row direction (vertical direction), and each address is 16 bits. CPU48 is SDR when selecting the camera mode.
The AM 30 is mapped as shown in FIG. That is,
Display data area of 300 Kbytes, camera data area of about 1.5 Mbytes, recording data area of 2.4 Mbytes, JPEG data area of 400 Kbytes, 40
A Kbyte thumbnail data area, a 88Kbyte software work area, and a 36Kbyte character area are formed in the SDRAM 30.

The signal processing circuit 24 is a so-called 4: 2: 2.
YUV data is generated by the conversion. Since each of Y data, U data and V data is 8 bits, 4
The amount of YUV data for pixels is 64 bits, that is, 4
It becomes an address. On average, YUV data is 16 bits (2 bytes) per pixel, and the thinning circuit 26a
The YUV data of 640 pixels × 240 lines output from 307200 bytes is 307200 bytes (300 Kbytes).
As described above, since the display data area has a capacity of 300 Kbytes, YUV data of 640 pixels × 240 lines is appropriately stored in the display data area.

The YUV data stored in the display data area is read twice by the SDRAM control circuit 30 when the bus 60 is open. That is, 6 from the YUV data of 640 pixels × 240 lines.
The same YUV data is read twice to create a through image of 40 pixels × 480 lines. At this time, reading is performed in response to the address data from the controller 28c shown in FIG. That is, the controller 28c
Calculates a read address based on the start address data of the display data area and the count value of the counter 29c, and inputs the calculated read address data to the SDRAM control circuit 30 once every four addresses. The SDRAM control circuit 30 reads the YUV data from the display data area at a clock rate of 48 MHz in response to such read address data. The read YUV data is given to the controller 28c, and the clock rate is set to 1 using the buffer 32c.
Returned to 2MHz.

The YUV data output from the controller 28c at a clock rate of 12 MHz is input to the pseudo framing circuit 34, and each line data is given a predetermined weighting. Specifically, the weighting amount for the YUV data input in the first half of one frame period is set to "0.2.
5 ", and the weighting amount for the YUV data input in the latter half of one frame period is" 0.75 ". As a result, the odd line data and the even line data are respectively input line data as shown in FIG. The interlaced scan data thus obtained is converted into an analog signal by the D / A converter 38 after passing through the encoder 36. This analog signal, that is, interlaced scan The YUV signal is output from the output terminal S1 and the LCD 40
And a through image is displayed on the LCD 40.

When the shutter button 44 is pressed by the operator while the through image is displayed, the system controller 46 gives a photographing command to the CPU 48. Then, the CPU 48 connects the switch SW1 to the buffer control circuit 28 side, and
3 is connected to the thinning circuit (zoom circuit) 22 side. CP
U48 also controls the timing generator 16 so that the camera signals of all lines are output from the CCD imager 12 in an interlaced scan system. As a result, the interlaced scan camera signal for one screen is
It is output from the CCD imager 12 in 1 / 7.5 seconds. This camera signal is given to the A / D converter 20 via the CDS / AGC circuit 18. Shutter button 52
The CPU 48 disables the CCD imager 12 1 / 7.5 seconds after is pressed. Therefore, after the shutter button 52 is pressed, only one screen of camera signal can be obtained.

The camera data of all lines output from the A / D converter 20 is input to the thinning circuit 22. At this time, the thinning rate of the thinning circuit 22 is set to "0" in both the vertical direction and the horizontal direction, and the camera data of all lines are given to the controller 28a as they are. The controller 28a is also loaded with the start address of the camera data area shown in FIG. 5 in response to the operation of the shutter button 52. Similarly to the above, the controller 28a temporarily stores the input camera data in the buffer 32a, and then supplies it to the SDRAM control circuit 30 together with the address data. This address data is also generated based on the loaded start address data,
The camera data and the address data are output to the SDRAM control circuit 30 at the clock rate of 48 MHz. As a result, the camera data is written in the camera data area by the SDRAM control circuit 30 at the clock rate of 48 MHz.

Since this camera data is interlaced scan data, odd field data is stored in the first half of the camera data area and even field data is stored in the second half. That is, an odd field area and an even field area are formed in the camera data area.

The camera data of all lines obtained according to the operation of the shutter button 44 is 1280 pixels × 960 lines, and each pixel is 10 bits.
That is, the camera data of all the lines is 153600
It has a data amount of 0 bytes (= 1280 pixels x 960 lines x 10 bits / 8 bits), that is, 1.5 Mbytes, and is stored in the camera data area in full.

When the writing of the camera data of all lines is completed, the SDRAM control circuit 30 executes the reading of this camera data in response to the address data from the controller 28e. That is, the controller 28e calculates the address data based on the head address data of the camera data area loaded from the CPU 48 and the count value of the counter 29e, and the SDRAM control circuit 30 responds to such address data, and the SDRAM control circuit 30 responds to the address data. Data is alternately read line by line from the odd field area and the even field area. As a result, the interlaced scan data is converted into progressive scan data.

The read progressive scan data is subjected to frequency conversion processing (48) by the controller 28e.
(MHz → 12 MHz), and then applied to the signal processing circuit 24 through the switch SW1. Signal processing circuit 2
4 performs color separation and YUV conversion on the input progressive scan data, that is, camera data of Cy, Ye, Mg, and G, and thereby 1280 pixels × 96.
0-line YUV data (recording YUV data) is generated.

The CPU 48 switches the switch S when the camera data of all lines are written in the camera data area.
W2 is connected to the signal processing circuit 24 side, and the switch SW3 is connected to the thinning circuit 26a side. The CPU 48 also sets the thinning rate of the thinning circuit 26a to "1/2" and "1/4" in the horizontal and vertical directions, respectively, and sets the thinning rate of the thinning circuit (zoom circuit) 26b in the horizontal and vertical directions. “0” for any direction
Set to.

Therefore, the thinning circuit 26a outputs 640
YUV data (display YUV data) of pixels × 240 lines is output, and the output display YUV data is input to the controller 28a via the switch SW3. The controller 28a is loaded with the start address of the display data area, and the display YUV data is written in the display data area in the same manner as when the through image is output.

On the other hand, the thinning circuit 26b has a switch SW.
The recording YUV data input through 2 is output as it is. The recording YUV data is directly input to the controller 28b. The head address of the recording data area shown in FIG. 5 is given to the controller 28b from the CPU 48, and the controller 28b calculates the write address based on the given head address data and the count value of the counter 29b. Then, the recording YUV data and the write address data are output to the SDRAM control circuit 30 at the clock rate of 48 MHz. The recording YUV data is written in the recording data area at a clock rate of 48 MHz by the SDRAM control circuit 30. Specifically, JPE described later
In consideration of G processing, Y data, U data, and V data are individually stored as shown in FIG. 640 pixels x 2
Since the display YUV data of 40 lines is 300 Kbytes, the recording YUV data of 1280 pixels × 960 lines is 2.4 Mbytes. Therefore, recording YUV
The data is stored in the full recording data area.

The display YUV data and the recording YUV data
The UV data is simultaneously output from the thinning circuits 26a and 26b, and the writing process of each data in the display data area and the recording data area is performed in parallel with each other.

When the writing of the display YUV data and the recording YUV data is completed, the controller 28c reads the display YUV data from the display data area and outputs it to the pseudo framing circuit 34 in the same manner as when the through image is output. As a result, the image at the time when the shutter button 52 is operated, that is, the same freeze image as the recorded image is displayed on the LCD 40.

In addition, YUV data for display and Y for recording
When the writing of UV data is completed, the CPU 48
However, the switch SW2 is connected to the buffer control circuit 28 side, and the thinning rate of the thinning circuit 26b is "1/4" and "1 /" in the vertical direction and the horizontal direction, respectively.
The display YUV data read by the controller 28c is supplied to the thinning circuit 26b only once through the switch SW2 and is subjected to thinning processing, in addition to being output to the pseudo framing circuit 34. As a result, based on the display YUV data, 160 pixels ×
120 lines of thumbnail YUV data are generated.

12 MH output from the thinning circuit 26b
The thumbnail YUV data of z is given to the controller 28b. At this time, the head address of the thumbnail work area is loaded into the controller 28b, and the controller 28b calculates the write address based on the loaded head address data and the count value of the counter 29b. Then, the thumbnail YUV data is output to the SDRAM control circuit 30 together with the calculated write address data. The thumbnail YUV data is supplied to the SDRAM control circuit 30 at a clock rate of 48 MHz, and the SDRAM control circuit 30 writes the supplied thumbnail YUV data in the thumbnail work area according to the write address data. 160 pixels x 120 lines thumbnail YU
V data is 37.5 Kbytes, thumbnail YUV
The data is stored in the 40 Kbyte thumbnail work area without any problem.

The controller 28f uses the start address of the recording data area loaded from the CPU 48 and 48 MH.
Counter 2 incremented at the z clock rate
Read address data is generated based on the count value of 9f. The SDRAM control circuit 30 reads the Y data, the U data, and the V data from the recording data area according to the read address data from the controller 28f.
The data is read for each block (8 pixels × 8 lines). Y data, U data, and V data are individually stored as shown in FIG. 7, and Y: U: V = 4:
Since it is 2: 2, first, the Y data is read twice for each block. That is, the Y data is continuously read twice. Next, U data and V data are read one block at a time.

Such a reading process is performed by the controller 2
8f and the SDRAM control circuit 30 repeatedly execute and read each block data, and the frequency conversion processing (4
8MHz → 12MHz), then JPE through bus 62
It is input to the G codec 56. JPEG codec 5
6, block data is repeatedly input in the order of Y data, Y data, U data, and V data. The JPEG codec 56 compresses the Y data, U data, and V data for each block according to the JPEG format. Then, each time the compression processing for one block is completed, the compressed YUV data is input to the controller 28g via the bus 64.

The controller 28g has a JPE shown in FIG.
The start address of the G work area is loaded, and the controller 28g calculates the write address of the compressed YUV data based on this start address data. Then, the calculated write address data is input from the JPEG codec 56 and subjected to frequency conversion (12 MHz →
48 MHz) and compressed YUV data together with S
Output to the DRAM control circuit 30. For this reason,
The compressed YUV data is stored in the SDRAM control circuit 30.
Is written in the JPEG work area at a clock rate of 48 MHz.

The capacity of the work area for JPEG is 400K.
Since it is a byte, if the compression ratio of the JPEG codec 56 is 1/6 or less, the compressed YUV data can be JP
It is stored in the EG work area.

When the writing process of the compressed YUV data to the JPEG work area is completed, the CPU 48 makes the SD
Thumbnail YU through RAM control circuit 30
The V data is read from the thumbnail work area, and the compressed YUV data is read from the camera data area. Then, the read compressed YUV data and thumbnail YUV data are recorded in the flash memory 54 through the interface 54.

As can be seen from the above description, the controllers 28a to 28g have the following roles. That is, the controller 28a writes the data input via the switch SW2 to the SDRAM 50. The controller 28b writes the data output from the thinning circuit 26b in the SDRAM 50. The controller 28c is
Read data from the display data area. The controller 28d reads character data from the character area shown in FIG. The controller 28e reads data from the camera data area. Controller 28f
Reads the data to be compressed from the SDRAM 50 and inputs it to the JPEG codec 56. The controller 28g receives the data compressed by the JPEG codec 56 and writes the data in the SDRAM 50.

According to this embodiment, the signal processing circuit is
The camera data read out from the camera data area of the DRAM is subjected to processing such as color separation and YUV conversion to generate recording YUV data, and the thinning circuit further causes the recording YU to be performed.
The V data is thinned out to generate display YUV data. Generated YUV data for display and Y for recording
The UV data is written in the display data area and the recording data area of the SDRAM, and then subjected to the display processing on the display and the recording processing on the flash memory. Here, the access speed to the SDRAM is 48 MHz
And the processing speed of the signal processing circuit and the thinning circuit is 1
2 MHz, and such a speed difference is absorbed by the buffer memory. Therefore, the YUV data for reading and displaying the camera data and the YUV data for recording
Data writing is performed in parallel. As a result,
It is possible to reduce the time required to generate the display data and the recording data and to write each generated YUV data in the SDRAM.

In this embodiment, a recording data area in which one frame of recording YUV data can be stored and a JPEG in which one frame of compressed YUV data can be stored.
Work area for SDRAM is formed in the SDRAM, and all compressed YUV data generated by JPEG compression is JPEG
Is stored in the work area for JPEG.
The compression process may be performed in the same manner as the conventional technique (Japanese Patent Laid-Open No. 11-239321).

That is, the recording YU based on the camera data
The V data generation process is performed every 8 lines, and the generated YUV data for recording for 8 lines is recorded in a 40 Kbyte JP
Stored in the work area for EG, this Y for recording of 8 lines
The compressed YUV data generated based on the UV data may be sequentially stored from the beginning of the camera data area. At this time, the display YUV data generation processing based on the recording YUV data is also performed every eight lines, and the freeze image display processing and the recording YUV data compression processing are completed almost at the same time.

Further, although the CCD type image sensor is used in this embodiment, it goes without saying that a CMOS type image sensor may be used instead.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an illustrative view showing a color filter.

FIG. 3 is a block diagram showing a buffer control circuit and a buffer.

FIG. 4 is an illustrative view showing an SDRAM.

FIG. 5 is an illustrative view showing a mapping state of SDRAM in a camera mode.

FIG. 6 is an illustrative view showing an operation of the pseudo framing circuit.

FIG. 7 is an illustrative view showing a recording data area formed in an SDRAM.

[Explanation of symbols]

10 ... Digital camera 22, 26a, 26b ... Thinning circuit 28 ... Buffer control circuit 30 ... SDRAM control circuit 50 ... SDRAM 56 ... JPEG codec 58 ... Flash memory

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H04N 9/07 (56) References JP-A-10-178612 (JP, A) JP-A-11-103436 (JP, A) Special Kaihei 11-284884 (JP, A) JP 2000-354193 (JP, A) JP 11-239321 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 5 / 225 H04N 5/76-5/956 H04N 9/07 H04N 9/79

Claims (4)

(57) [Claims] 1. A live image of a subject photographed in response to a photographing instruction.
First writing means for writing an image signal in a first area of a memory, reading means for reading out a raw image signal stored in the first area, for recording in YUV format based on the raw image signal read by the reading means First generating means for generating an image signal, the recording image signal generated by the first generating means
Second generating means, second writing means for writing the display image signal generated by said second generating means to the second area of said memory for generating a display image signal by performing zooming processing,
And processing of the recorded image signal generated by the first generating means comprises a third writing means for writing the third area of said memory, said first generating means access speed to the memory and the second generating means Then Tomo to more than three times the speed
The recording image signal generated by the first generating means.
To the second generation means without passing through the memory
A digital camera that I tried to give . 2. A buffer memory that is accessed at a first clock rate and a second clock rate that is at least three times the first clock rate, the access speed to the memory, the first generation means, and the second memory. 2. The digital camera according to claim 1, wherein the buffer memory absorbs a difference in processing speed of the generating means. Wherein the memory has a single data input and output ports, according to claim 1 or 2 digital camera according. 4. A record in the output unit, and the recording image signal to the third read from area serial <br/> recording medium to output the display image signal to read out de Isupurei from said second area The digital camera according to any one of claims 1 to 3 , further comprising a recording unit.