JP5678273B2 - Memory controller - Google Patents

Description

  The present invention relates to a memory controller having interleave access means and non-interleave access means.

  In an electronic device such as a digital still camera, the capacity and number of memories to be mounted are increased and the driving frequency is also increased in order to improve functions. For this reason, the ratio of the power consumed by the memory is high in the power consumption of the electronic device.

  Also in consumer electronic devices, the adoption of a unified memory system in which a memory is shared for a plurality of uses and the adoption of an interleave access in which a plurality of memories are regarded as one memory are being advanced.

  Patent Document 1 discloses a technology for reducing power consumption of an imaging apparatus equipped with a plurality of memories. The technology described in Patent Document 1 uses a memory controller with interleave access means and non-interleave access means, and when high-speed image processing is required for continuous shooting, etc., high-speed memory access is realized using interleave access means In other periods, it is intended to reduce the current consumption of the DRAM as a whole by performing non-interleaved access to only one memory and putting the memory that is not accessed into a power saving mode.

JP 2008-152687 A

  However, in the technique described in Patent Document 1, access may be concentrated on one memory, and there is a possibility that intended high-speed memory access may not be realized. For example, in FIG. 3 of Patent Document 1, YC data, image data, compressed data, and CPU work assigned to the DRAM on the 8b side may be accessed simultaneously, resulting in processing delay due to access contention.

  Also, since the interleave access means and the non-interleave access means are selected above or below the area boundary address, and the compressed data non-interleave access and YC data are determined to be interleave access, the area when the area allocated to the YC data is insufficient Even if there is an empty area below the boundary address, YC data cannot be allocated if at least one DRAM is used up to the area boundary address.

  An object of the present invention is to solve the above-mentioned problems and to provide a memory controller that realizes high-speed memory access and power saving control.

  In order to solve the above problems, a memory controller according to the present invention is a memory controller that manages a plurality of memory banks composed of at least one memory element, and that accesses a single memory bank in response to a sequential access request. Interleave access means, interleave access means for alternately accessing a plurality of memory banks in response to sequential access requests, and storage management means for allocating storage areas in units of pages, the storage management means being non-interleave access means for each page And interleave access means are selected.

  The memory controller includes an access amount monitoring unit that counts an access amount. When the access amount is larger than a threshold, when the page is allocated, an interleave access unit is selected, and when the access amount is smaller than the threshold. Further, it may be characterized by having access selection means for selecting non-interleaved access means when allocating pages.

  Further, the page capacity when the interleave access means is selected and the page is allocated may be an integral multiple of the page capacity when the non-interleave access means is selected and the page is allocated.

  The memory controller has a process identification means for identifying the accessing process, and means for selecting one of the interleave access means and the non-interleave access means according to the process, or means for changing the threshold according to the process It is good also as having.

  The memory controller includes an access amount monitoring unit that counts an access amount for each bank, and the storage management unit allocates an access amount assigned to a memory bank with a smaller access amount when assigning a page designating non-interleaved access. It may be characterized by having an averaging means.

  Further, the storage management means has a page number management means for counting the number of pages assigned to each memory bank, and the storage management means is more allocated pages when assigning pages specifying non-interleaved access. It may be characterized by having means for averaging the number of pages allocated to a memory bank with a small amount of memory.

  Further, the storage management means has a page number management means for counting the total number of pages allocated to the memory, and when the total number of pages is larger than a threshold value, the interleave access means is selected when allocating pages. In addition, when the total number of pages is smaller than a threshold value, an access selection unit that selects a non-interleaved access unit when allocating a page may be provided.

  The storage management means may have a centralizing means for assigning to a specific memory bank when assigning a page designating non-interleaved access.

  Further, the storage management means has a page number management means for counting the number of pages assigned to each memory bank, and the storage management means saves power for a memory bank in which the number of assigned pages is zero. Control may be performed.

  As described above, according to the present invention, the memory usage is averaged between the memory banks and the access is averaged. Therefore, access and memory usage are concentrated in a specific memory bank, and access delay and memory usage are reduced. It is possible to prevent waste. When the access amount is small, the memory use can be concentrated on a specific memory bank, and the remaining memory can be put into a power saving state.

The block diagram which shows the structure of the digital still camera using the memory controller by this invention Memory map explaining the address conversion function of the interface circuit Flow chart explaining memory allocation condition determination Timing chart explaining transition of memory usage and power saving control

(Embodiment 1)
(1. Configuration)
Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a digital still camera using a memory controller according to the present invention.

  In FIG. 1, 1 is an imaging circuit, 2 is a YC processing circuit, 3 is a compression processing circuit, 4 is a recording circuit, 5 is a CPU, 6 is an interface circuit, 7a is interleave access means, 7b is non-interleave access means, and 8 is A first DRAM, 9 a second DRAM, 10 a memory controller, 11 a power supply circuit, 12 a memory card for storing compressed data of captured images, 13 a storage management means, 21 a monitor for displaying images, Reference numeral 20 denotes a display circuit for displaying an image on the monitor 21.

  As shown in FIG. 1, the memory controller 10 of this embodiment comprises an interface circuit 6, an interleave access means 7a, and a non-interleave access means 7b. Each of the circuits 1 to 5 in FIG. 1 has a function of accessing the DRAM 8 and the DRAM 9, and all accesses to the two DRAMs are performed via the memory controller 10.

(2. Operation)
(2.1 Digital still camera operation)
Hereinafter, the operation as a digital still camera will be briefly described with reference to FIG. The imaging circuit 1 includes a photoelectric conversion element such as a CCD, and converts an image of incident light into image data. Image data output from the imaging circuit 1 is stored in the DRAM 8 or DRAM 9 via the memory controller 10.

  The YC processing circuit 2 reads the image data from the DRAM 8 or DRAM 9 via the memory controller 10 and converts it into YC data suitable for compression, and writes it back to the DRAM 8 or DRAM 9 again via the memory controller 10.

  The compression processing circuit 3 reads YC data from the DRAM 8 or DRAM 9 via the memory controller 10 and performs compression conversion, and writes the generated compressed data back to the DRAM 8 or DRAM 9 via the memory controller 10 again.

  The recording circuit 4 reads the compressed data from the DRAM 8 or the DRAM 9 via the memory controller 10 and stores it in the memory card 12 attached to the recording circuit 4.

  The CPU 5 controls the circuits 1 to 4 in FIG. 1 (control lines are not shown) and accesses the DRAM 8 or DRAM 9 via the memory controller 10 to operate the header portion of the compressed data.

  The circuits 1 to 4 in FIG. 1 can operate independently of the CPU 5, and in particular, the imaging circuit 1, YC processing circuit 2, and compression processing circuit 3 can execute processing of one image data without the intervention of the CPU 5. .

  The interface circuit 6 of the memory controller 10 converts the logical address input to the interface circuit 6 into a physical address given to the DRAM 8 and DRAM 9 in response to the memory access request of the circuits 1 to 5 in FIG.

  The memory controller 10 is a memory controller that can accept a plurality of memory access requests while arbitrating, and the circuits 1 to 5 in FIG. 1 can access the DRAM 8 and the DRAM 9 independently and in parallel.

  The power supply circuit 11 is a circuit that supplies a current to each circuit of the digital still camera. In particular, the current supplied to the DRAM 8 and the DRAM 9 can be turned on / off independently of other circuits.

(2.2 Function of interface circuit)
The function of the memory controller 10 will be described with reference to FIG. The memory controller 10 of this embodiment includes interleave access means 7a and non-interleave access means 7b, and can control the DRAM 8 and DRAM 9 and convert the data width. The DRAM 8 and DRAM 9 of this embodiment have a data width of 2 bytes, and 2 bytes of data are assigned to one logical address. The circuits 1 to 5 in FIG. 1 output one address in one access and request the memory controller 10 to access two bytes of data for one address. In response to this, the memory controller 10 executes 2-byte data access for one address in one of the DRAM 8 and the DRAM 9 in response to one access request.

  The conversion from the logical address to the physical address is performed by the interface circuit 6. The storage management unit 13 converts the logical address output by the circuits 1 to 5 in FIG. 1 into a physical address, and at the same time, uses either the interleave access unit 7a or the non-interleave access unit 7b. Instruct whether to access.

  For example, when the interleave access means 7a is selected for the address accessed by the imaging circuit 1, the DRAM 8 and the DRAM 9 are alternately accessed for sequential access by the imaging circuit 1. On the contrary, when the non-interleaved access means 7b is selected, the DRAM 8 and the DRAM 9 which are designated by the storage management means 13 are continuously accessed.

  The address conversion performed by the storage management means 13 is a conversion from a logical address to a physical address in units of an area having a certain capacity called a page and a series of addresses. The logical addresses output by the circuits 1 to 5 are Even if they are scattered, the memory area can be used without waste by assigning a series of continuous physical address areas by address conversion. The storage management means 13 is provided with a conversion table 14 for address conversion. The correspondence between the logical address and the physical address, the selection of the DRAM, and the selection of the interleave access means 7a and the non-interleave access means 7b are all conversion tables 14. Is remembered.

  Although not shown, the storage management unit 13 includes a counter that independently counts the number of pages allocated to each of the DRAM 8 and the DRAM 9, and the number of pages allocated to the DRAM 8 and the pages allocated to the DRAM 9. From the sum of the numbers, the total number of allocated pages can be obtained.

  Further, the memory controller 10 of this embodiment includes a counter 15, and the counter 15 counts the number of accesses to the DRAM 8 and DRAM 9. More specifically, although not shown, the counter 15 comprises an access counter for the DRAM 8 and an access counter for the DRAM 9, and the interleave access means 7 a and the non-interleave access means 7 b correspond each time the DRAM 8 and DRAM 9 are accessed. A count-up pulse is sent to the access counter, and in the counter 15, each access counter counts the number of accesses according to the count-up pulse.

  Next, the function of the interface circuit 6 will be described with reference to FIG. FIG. 2 is a memory map for explaining the address conversion function of the interface circuit 6. 2A is a memory map of the logical address space, and FIG. 2B is a memory map of the physical address space, and includes a memory map 8b of the physical address space of the DRAM 8 and a memory map 9b of the physical address space of the DRAM 9. The logical address is an address output by the circuits 1 to 5 in FIG. 1, and the physical address is an address given to the DRAM 8 and DRAM 9 by the interface circuit 6. The horizontal width of each memory map indicates the data width. FIG. 2C is a conversion table for converting logical addresses into physical addresses.

  One unit of the memory area when assigning a physical address to a logical address is called one page. The capacity per page usually varies from several kilobytes to several megabytes. However, in the description of this embodiment, for convenience of illustration, 4 bytes are used for one page during non-interleaved access, and 8 bytes are used for non-interleaved access. It is a page.

  The numbers added on the left side of FIG. 2A are logical addresses, and 2-byte data corresponds to one logical address. The rectangular area in the figure represents 1-byte data, and the numbers in the rectangular area correspond to addresses expressed in bytes.

  2B includes a memory map 8b of the physical address space of the DRAM 8 and a memory map 9b of the physical address space of the DRAM 9, and the rectangular area to which the same numbers are entered in FIG. 2B and FIG. It means 1 byte on the address and 1 byte on the physical address associated therewith. For example, the first page on the logical address is 4 bytes at addresses 0 and 1, and is allocated to the physical addresses 0 and 1 of the DRAM 8 on the physical address. Non-interleaved access is specified for access to this page. When data 0, 1, 2, and 3 at logical address 0 and address 1 are accessed sequentially, the same DRAM 8 is continuously accessed, and two accesses are made. Access to 4 bytes.

  In FIG. 2A, interleaved access is specified for data 48, 49, 50, 51, 52, 53, 54, and 55 from logical addresses 24 to 27. When sequential access is performed on logical addresses, As shown in FIG. 2B, interleave access is performed in which the DRAM 8 and the DRAM 9 are accessed alternately. At this time, if the DRAM 8 and the DRAM 9 are accessed at the same time, 4 bytes can be accessed in the time required for the two accesses, and the speed twice as high as that in the non-interleaved access can be obtained.

  Non-interleaved access and interleaved access can be used properly according to the situation. For example, in FIG. 2A, data from logical addresses 20 to 23, 40, 41, 42, 43, 44, 45, 46, and 47 are data from logical addresses 24 to 27, 48 , 49, 50, 51, 52, 53, 54, 55, but specifies non-interleaved access. That is, the logical addresses 20 to 21 of (a) are assigned as one page and assigned to the physical addresses 4 to 5 of the 8b, and the physical addresses 8b are assigned to the logical addresses 22 to 23 of the (a) as one page. Address conversion assigned to addresses 4 to 5 is performed. In this way, even for continuous data on a logical address, it is possible to change the designation from non-interleaved access to interleaved access at the page boundary, or to reverse from interleaved access to non-interleaved access.

  In the address conversion of this embodiment, in order to simplify the conversion circuit, the capacity of one page at the time of non-interleaved access is doubled at the time of non-interleaved access. In other words, the 4 bytes from the logical addresses 20 to 21 of (a) where non-interleaved access is specified in the previous example is one page, whereas the logical of (a) where interleaved access is specified. Addresses 24 to 27 are one page with 8 bytes. In this way, the width of the address occupied by one page on the physical address is always address 2, and each page can be managed as starting from an even address.

  FIG. 2C shows a conversion table 14 for address conversion, which has a function of converting a logical address to a physical address. The top address of the corresponding logical address is added to the left side of FIG. As shown in the figure, the start address of the logical address conversion unit is always an even number.

  The conversion table 14 has a memory of one word for each unit of address conversion, and each word is divided into three bit fields 8c, 9c, and 14c. If bit 8c is 1, it means that it is assigned to DRAM 8, and if bit 9c is 1, it means that it is assigned to DRAM 9. If only the bit 8c is 1 and the bit 9c is 0 as in address 0 in FIG. 2C, non-interleaved access for accessing only the DRAM 8 is designated. If only bit 9c is 1 and bit 8c is 0, as in address 10 in FIG. 2 (c), non-interleaved access for accessing only DRAM 9 is designated.

  If both the bit 8c and the bit 9c are 1 as in the 24th address and the 26th address in FIG. 2C, interleave access for alternately accessing the DRAM 8 and the DRAM 9 is designated. Although illustration is omitted, if both bits 8c and 9c are 0, it indicates that the page is a free page to which no physical address is assigned to the logical address.

  In FIG. 2C, the bit field 14c stores the start address of the physical address assigned to the logical address. In a word in which non-interleaved access is designated, such as addresses 0 to 2 in FIG. 2C, the capacity of one page, that is, 4 bytes corresponds to the capacity of two addresses on the physical address. In the conversion table, the 8-byte memory from the address to the address 3 stores the allocation information in the two words of the addresses 0 and 2.

  As described above, in order to simplify the conversion circuit in the address conversion of the present embodiment, the capacity of one page at the time of interleave access is doubled at the time of non-interleave access. This is the conversion of FIG. On the table, it means that information is stored continuously in two words like the 24th address and the 26th address. The 24th address instructs allocation to the 6th address of the two DRAMs, and the 26th address allocates to the 7th address of the two DRAMs. In addition, the capacity corresponding to the 2nd address on the physical address is allocated.

  The storage management means 13 of the present invention has a function of automatically assigning a physical address to a logical address in synchronization with a write request to the DRAM. Specifically, for example, when there is an initial write request to a page starting from address 12 on the logical address, the storage management means 13 writes the physical address information in the word at the address 12 in the conversion table. When a page is assigned to a page with a physical address and there is a subsequent write request to address 13 in the same page, address conversion is performed using the information of the word at address 12 in the conversion table.

  This page allocation operation takes a certain time depending on the configuration of the storage management means 13 and the conversion table 14. Therefore, the access time becomes longer than usual in the first writing to the page. During interleaved access, the capacity of one page is twice that of non-interleaved access, so the frequency of page allocation is halved. Therefore, the time spent waiting for page allocation while writing a certain amount of data is shorter for interleaved access than for non-interleaved access.

  Although not shown, the storage management means 13 has two counters for counting the number of pages allocated to the DRAM 8 and the number of pages allocated to the DRAM 9 respectively. The two counters are initialized to 0 when the system is activated, and the storage management unit 13 counts up the counter on the corresponding DRAM side every time the physical address information is written in the management table 14.

  In addition, the storage management unit 13 has a function of monitoring memory access and deleting registration of pages that are no longer necessary as the processing progresses. Count down the counter on the side. Since the capacity of the SDRAM is known, the number of free pages that can be allocated in the future can be obtained for each DRAM by subtracting the number of allocated pages. Further, the storage management means 13 can obtain the total number of allocated pages by summing the values of the two counters.

  At the time of assignment, the storage management means 13 assigns the youngest address among the areas where the physical address is empty. In this way, since the memory is used in a bottom-up manner as shown in FIG. 2B, the memory capacity is not wasted.

  As described above, the memory controller 10 of the present invention can simultaneously execute interleave access and non-interleave access by using the storage management means 13 or the conversion table 14.

  Next, the criteria for selecting interleaved access and non-interleaved access at the time of page allocation will be described with reference to FIG. FIG. 3 is a flowchart for determining which one of interleave access and non-interleave access is selected, and which DRAM is accessed in the case of non-interleave access. In FIG. 3, interleaving indicates selection of interleaved access, only A indicates selection of non-interleaved access only to DRAM 8, and only B indicates selection of non-interleaved access only to DRAM 9.

  When page allocation is performed, first, in step S101, the total amount of memory used is checked. The total amount of memory used is the sum of the counter values of the number of pages assigned to the DRAM 8 and DRAM 9 of the storage management means 13 described above. If the total usage is smaller than the threshold T1, non-interleaved access to only the DRAM 8 is selected. This is because when the memory usage is small, only the DRAM 8 is used and the power supply of the DRAM 9 can be shut off.

  If the total usage is larger than the threshold value T1, the process proceeds to step S102. In step S102, it is determined whether the written data requires high speed processing. Since the interface circuit 6 individually accepts access requests from the circuits 1 to 6 that access the memory, it is known which circuit has output the data. By utilizing this, the threshold value T1 can be changed according to the type of data.

  For example, the data output from the compression processing circuit 3 is compressed data, and the compressed data is read by the recording circuit 4 and written to the relatively low-speed memory card 12, so that high-speed memory access is not required. Therefore, if the circuit that output the write data is the compression processing circuit 3, if zero is used as the threshold value T1, the branch is made to No in step S102, and the interleave access is not performed. On the contrary, if the data is output from the imaging circuit 1 or the YC processing circuit 2, the circuit that reads the next written data is the YC processing circuit 2 or the compression processing circuit 3, and these have a high data processing speed. It is better to be able to select interleave access. Therefore, if the circuit that outputs the write data is the image pickup circuit 1 or the YC processing circuit 2, if the upper limit value is used as the threshold value T1, the process always branches to Yes in step S102 and interleaved access becomes possible.

  Of course, such control for each data is arbitrary, and a constant threshold value T1 may be used regardless of the circuit that outputs the write data.

  In step S103 and step S104, the availability of memory for each DRAM is checked. In order to select interleaved access, both DRAMs need to be free. In the conditional statement in step S 103, B free indicates the number of pages that can be allocated to the DRAM 9. When the empty space of the DRAM 9 is smaller than the threshold value T2 in step S103, it is determined that a page cannot be allocated to the DRAM 9, and non-interleaved access to only the DRAM 8 is selected. When the determination is No, the process proceeds to step S104, and the number of pages that can be allocated to the DRAM 8 is checked. Similarly to step S103, when the free space of the DRAM 8 is smaller than the threshold value T2, it is determined that a page cannot be allocated to the DRAM 8, and non-interleaved access to only the DRAM 9 is selected.

  If both DRAMs are free, the process proceeds from step S104 to step S105, and the access frequency is checked. In the conditional statement in step S105, the B frequency is a value obtained by dividing the number of accesses to the DRAM 9 measured by the counter 15 by the unit time. If a page is allocated to a busy SDRA, the amount of access further increases and the access time may increase due to contention. Therefore, a page is allocated to the non-crowded SDRAM. In step S105, if the access frequency to the DRAM 9 exceeds the threshold T3, non-interleaved access to only the DRAM 8 is selected. Otherwise, the process proceeds to step S106.

  In the conditional statement in step S105, the A frequency is a value obtained by dividing the number of accesses to the DRAM 8 measured by the counter 15 by the unit time. Similarly to step S105, when the access frequency to the DRAM 8 exceeds the threshold value T3, non-interleaved access only to the DRAM 9 is selected.

  In the case of No in step S106, there is no problem in the availability of DRAM and the degree of access, so interleave access to both DRAMs is selected.

  When branching to the No side in step S102, there is no interleave access as the final option, and either non-interleave access to DRAM 8 or non-interleave access to DRAM is selected. In step S107 to step S108, as in steps S103 to S104, the availability of memory for each DRAM is checked.

  When the empty space of the DRAM 9 is smaller than the threshold value T2 in step S107, it is determined that a page cannot be allocated to the DRAM 9, and non-interleaved access to only the DRAM 8 is selected. When the determination is No, the process proceeds to step S108, and the number of pages that can be allocated to the DRAM 8 is checked. When the free space of the DRAM 8 is smaller than the threshold value T2, it is determined that a page cannot be allocated to the DRAM 8, and non-interleaved access to only the DRAM 9 is selected. If none of them match, the process proceeds to step S109. In step S109, the access frequencies of the DRAM 8 and the DRAM 9 are compared, and the non-interleaved access is selected for the one with less access.

By selecting page allocation as described above, when the total memory usage is less than the threshold T1, pages are allocated only to the DRAM 8, and when the total memory usage is equal to or higher than the threshold T1 and high-speed data access is required. As long as there is no problem with memory availability and access congestion, pages are allocated for interleaved access to both DRAMs. If there is a problem with memory availability or access congestion, there is free space and it is not crowded. A page is allocated to the DRAM on the side, and when high-speed data access is not required, the page is allocated to the DRAM on the side where the access is not crowded.

  With this operation, when the total memory usage is equal to or greater than the threshold value T1, the usage of the two memories is averaged, so that interleaved access to access both DRAMs can operate satisfactorily. Further, when the total memory usage falls below the threshold value T1, pages are allocated only to the DRAM 8. Therefore, as the registration and deletion of unnecessary pages proceed as the processing proceeds, the number of pages allocated to the DRAM 9 increases. Becomes zero. From that point on, the DRAM 9 does not store valid data and there is no need to retain the contents of the memory, so the power supply circuit 11 can cut off the current supply to the DRAM 9.

  Although explanation of the operation when each threshold value is changed is omitted here, there is no problem even if the threshold value is changed during the operation, and no inconvenience occurs. Since the result of the condition determination is stored in the conversion table 14, even if the threshold value changes after registration, the registered information is not affected. The page registered in the conversion table 14 is valid until the registration is deleted, and can be accessed regardless of the threshold value at that time.

(2.3 Power consumption)
Next, the power consumption of a digital still camera using the memory controller of the present invention will be described with reference to FIG. FIG. 4 is a timing chart for explaining the transition of memory usage and power saving control during shooting.

  In FIG. 4A, the horizontal axis represents time, the vertical axis represents the memory usage, and 31 represents the memory usage transition. In FIG. 4B, the horizontal axis represents time, the vertical axis represents the power consumption of the DRAM, and 36 schematically represents the transition of the power consumption of the DRAM.

  Time 20 is the power-on time of the digital still camera, and the CPU 5 operates to secure the CPU work area. The memory usage at this time is the CPU work area size 29. 4 is a capacity corresponding to the threshold value T1 in the flowchart of FIG. 3, and the CPU work area size 29 is less than the threshold value T1, so that a page is allocated only to the DRAM 8.

  Since the DRAM 9 is unnecessary at this time, the power supply circuit 11 cuts off the current supply to the DRAM 9 and the DRAM consumes only one power as a whole (period 33).

  Time 21a is the time when the shutter button is pressed and exposure is started. The time 21b is the time when the exposure is completed and the output of the image data from the imaging circuit 1 is started. Thereafter, the imaging circuit 1 operates and writes the image data, so that the memory usage 31 increases. . Since the memory usage 31 exceeds the threshold value T1 in FIG. 3 and 28 lines in FIG. 4 at time 22, a page is also allocated to the DRAM 9. The interface circuit 6 instructs the power supply circuit 11 to supply current to the DRAM 9 at the time 21a when the shutter button is pressed, and the DRAM 9 is also accessible at the time 22. In principle, the power supply may be performed when the DRAM 9 becomes necessary. However, since a certain waiting time is actually required until the DRAM 9 becomes accessible from the power-off state, the power supply is performed at the time 22. In this case, part of the image data output from the imaging circuit 1 is missed due to the waiting time. In order to avoid this, the DRAM 9 is energized in advance from when the shutter button is pressed.

  Time 23 is the time when the imaging circuit 1 finishes outputting the image data. From here, the YC processing circuit 2 converts the image data into YC data, and the compression processing circuit 3 compresses and converts the generated YC data into JPEG data. To start. The amount of image data is compressed to about 1/10 by compression conversion, and the recording circuit 4 once reads the compressed data written in the SDRAM and writes it in the memory card 12.

  At this time, the page assigned to the processed image data and YC data is deregistered from the conversion table 14 by the storage management means 13, so that the image data is replaced with the compressed data on the memory. Since the compressed data is one-tenth the capacity of the image data, the memory usage will decrease from time 23 as the processing proceeds.

  Time 24 is a time when the memory usage 31 falls below the threshold value T1, and all the write data after that is allocated to the DRAM 8.

  Time 25 is the time when the compression processing circuit 3 finishes the compression processing, and the image data and YC data are all converted into compressed data, and only the CPU work and the compressed data occupy the memory. At this time, since the compressed data generated between time 23 and time 24 is also allocated to the DRAM 9, the power of the DRAM 9 cannot be shut off at this time. From time 25, the recording circuit 4 starts to transfer the compressed data to the memory card 12.

  Since the compressed data is transferred to the memory card 12 in the order in which it was generated, the compressed data generated between time 23 and time 24 is read from the DRAM prior to the subsequent data. As a result, the compressed data pages allocated to the DRAM 9 are deregistered one after another, and the usage amount of the DRAM 9 decreases.

  Time 26 is when the page allocated to the DRAM 9 becomes zero while the recording circuit 4 is transferring the compressed data to the memory card 12. After that, since it is not necessary to hold the memory of the DRAM 9, the interface circuit 6 issues an instruction to the power supply circuit 11 at time 26 to cut off the current to the DRAM 9. The period 34 thus far indicates a period in which both the DRAM 8 and the DRAM 9 are energized, and the period 35 indicates a period in which only the DRAM 8 is energized and the DRAM 9 is turned off.

  Time 27 is the time when the recording circuit 4 has finished transferring all of the compressed data to the memory card 12, and here, one image capturing sequence is completed.

  In this example, the threshold value 28 is assumed to be constant for simplicity, but the threshold value can be set and changed at any time. For example, if it is desired to speed up the capture of image data using interleaved access, the threshold value 28 may be set to a data amount 29 or less at the time 21b. Can be raised to the upper limit of the total capacity. Further, as described above, since the interface circuit 6 can grasp which circuit has output the data, it is possible to change the threshold value used for condition determination according to the circuit. Therefore, the threshold for image data may be set to zero and the threshold for compressed data may be filled up from the time 20 so that all compressed data is accessed non-interleaved and image data is accessed interleaved.

  As described above, by using the technology of the present invention, the shutter button press standby period and the part of the compressed data transfer period (period 33, period 35) sufficient for low-speed access are energized only to the DRAM 8, The power consumed by the DRAM can be reduced.

(3. Other configurations)
In the above embodiment, the DRAM has been described as an example, but the memory may be an SRAM. The type of memory device does not matter.

  In the above embodiment, the case where two memory devices are used has been described as an example, but the number of memory devices is not limited. For example, in the case where four memory devices are used, one bank may be configured by pairing two memory devices.

  In the above embodiment, the power saving control is performed by turning off the power to the memory device. However, it is possible to stop only the clock supply while the power is on, or the power saving mode of the memory device. You can move to

  In the above-described embodiment, the case where the power saving control is performed for each memory device has been described as an example. However, the power saving control may be performed for each bank in the memory device. For example, when using a memory device having four memory banks of memory banks 0 to 3, two banks may be regarded as one bank, and access using four banks may be redefined as interleave access.

  As another configuration, a digital still camera (an example of an imaging device) includes an imaging circuit 1 (corresponding to an imaging unit) and image data generated based on an image captured by the imaging circuit 1 in a memory card 12 (stored). A recording circuit 4 (corresponding to a recording means) for recording on a medium) and a display circuit 20 (display) for displaying an image generated based on an image captured by the imaging circuit 1 on a monitor 21 (corresponding to a display medium). Means 8), DRAM 8 (corresponding to the first memory), DRAM 9 (corresponding to the second memory), and the memory card 12, when the image data is recorded, the DRAM 8 and the DRAM 9 are accessed in parallel. When controlling to perform interleaved access and displaying an image on the monitor 21, non-interleaved access to either the DRAM 8 or the DRAM 9 is performed. A memory controller 10 (corresponding to the control means) that controls the access to the memory, and an interface circuit 6 (corresponding to the address conversion means) that converts the physical address of the DRAM 8 and the physical address of the DRAM 9 into one virtual address. An interface circuit 6 that performs different address conversions when the controller 10 performs interleaved access and non-interleaved access may be provided.

  INDUSTRIAL APPLICABILITY The present invention can be applied to all electronic information processing apparatuses using a memory and is useful because it can reduce power consumption of the apparatus. Devices that are battery powered are particularly useful because they can increase battery duration.

  For example, in the case of a digital still camera, high-speed access is mainly required for a period during which a captured image is processed, and high-speed access is not required in many other periods.

  According to the present invention, it is possible to perform both high-speed signal processing of captured images by interleaved access and reduction of memory power consumption during other periods, without impairing performance such as high-speed continuous shooting, and the like. This is useful because the duration and the number of images that can be taken can be increased.

DESCRIPTION OF SYMBOLS 1 Imaging circuit 2 YC processing circuit 3 Compression processing circuit 4 Recording circuit 5 CPU
6 Interface circuit 7a Interleave access means 7b Non-interleave access means 8, 9 DRAM
DESCRIPTION OF SYMBOLS 10 Memory controller 11 Power supply circuit 12 Memory card 13 Storage management means 14 Conversion table 15 Counter

Claims (1)

A memory controller for managing a plurality of memory banks each including at least one memory element,
Non-interleaved access means for accessing a single memory bank in response to a sequential access request;
Interleave access means for alternately accessing a plurality of memory banks in response to a sequential access request;
Allocating storage in page units, and a memory management unit you select non-interleaved access means and interleaved access means for each page,
It said storage management means,
A conversion table that manages the registration and de-registration of pages allocated to memory access requests;
Page number management means for counting the total number of pages allocated to the memory;
When the total amount of pages is larger than a threshold, when interleave access means is selected when allocating pages, and when the total amount of pages is smaller than the threshold by deregistering the pages allocated from the conversion table An access selection means for selecting a non-interleaved access means when assigning pages;
When allocating pages that specify non-interleaved access, a centralized means for allocating to specific memory banks and deregistering the pages allocated to the remaining memory banks to bring the registration to zero,
Page number management means for counting the number of pages allocated to each memory bank,
The memory management unit performs power saving control on a memory bank in which the number of allocated pages is zero .

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