JP2721387B2 - Video signal processing circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a video signal processing circuit, and more particularly to a video signal processing circuit having a function of enlarging an image.

[Prior Art] Conventionally, as a process of expanding a video signal, a method of realizing the process by controlling a read address using a random access memory (RAM) according to a predetermined program has been generally used. The present applicant has previously filed an application for a technique for realizing the above-mentioned enlargement processing using a so-called first-in first-out memory (hereinafter referred to as FIFO) (Japanese Patent Application No. 63-17413).

[Problems to be Solved by the Invention] By the way, it is conceivable that the screen subjected to such enlargement processing can be viewed alone, but a very interesting screen can be obtained in combination with other screens.

Further, by combining processes such as wipe and fade of the enlarged screen, more various image effects can be obtained.

However, such a process is generally not installed in household consumer devices even though it is generally installed in business devices. The reason is that, in order to perform the above processing, a processing circuit for enlarging an image, a processing circuit for an image for synthesizing this image, and a processing circuit for wiping or fading each of them are necessary. Would be enormous.

Under such a background, the present invention has a simple circuit configuration,
Another object of the present invention is to provide a video signal processing circuit capable of realizing wipe and fade when an enlarged image is combined with another image.

[Means for Solving the Problems] Under such a purpose, the video signal processing device of the present invention has a memory capable of storing a video signal for one screen,
A processing circuit having a delay function of delaying a video signal by one screen period using the memory, and an image enlargement function of obtaining an enlarged image by reading out the video signal stored in the memory according to a clock having a lower frequency than at the time of writing. A subtractor for obtaining a difference between a video signal output from the processing circuit and an input video signal, a first coefficient unit for multiplying a variable coefficient determined regardless of its input level, A multiplying circuit for multiplying the output of the subtractor by a controllable coefficient by selectively using a second coefficient unit for multiplying the coefficient determined by A first mode in which the processing circuit is used as an image enlargement circuit, the multiplication process is performed by the first coefficient unit, and the processing circuit is used as a delay circuit. It has a configuration and a mode switching means for switching the mode between the second mode in which the multiplication processing by a second coefficient multiplier.

[Operation] With this configuration, noise reduction processing, synthesis with an enlarged image, fading, and wipe can all be realized without providing any complicated processing circuit.

Example An example of the present invention will be described below.

FIG. 1 is a block diagram showing a configuration of a video signal processing circuit according to an embodiment of the present invention. In FIG. ing. It is assumed that all components of FIG. 1 handle digital signals of a plurality of bits.

First, the normal operation of the processing circuit of FIG. 1, that is, the operation when acting as a noise reduction circuit will be described.

In this case, the switch 4 is connected to the output terminal 26 side of the processing circuit by a control signal generated from the system control 30 in accordance with the operation of the operation unit 32.
The video signal being output to the FIFO 6 via the switch 4 is written into the FIFO 6 having a capacity of one field (WD).
Is entered as At this time, the FIFO 6 always writes and reads data, and the reset timing of the write address is set immediately after the reset timing of the read address. Thus, the FIFO 6 simply acts as a one-field delay circuit.

The switch 14 always inputs the output of the FIFO 6 to the subtracter 16 without passing through the one horizontal period delay line (1HDL) 12 by the control pulse CP from the timing controller 8 controlled by the system controller 30. Subtractor 16
Takes the difference between the input video signal and the video signal one field before, and supplies a signal of the sum of the noise component and the motion component obtained by the difference to the subsequent circuit.

Further, the switch 22 is connected to the non-linear circuit 18 side by the system controller 30, and supplies the output of the non-linear circuit 18 to the adder 24. The nonlinear circuit 18 has a predetermined coefficient K (1> K) when the input level is equal to or lower than a predetermined value.
> 0), and outputs a value corresponding to the predetermined value when the value is equal to or larger than the predetermined value. The coefficient K of the non-linear circuit 18 is set to a value close to 1, so that a noise component equal to or less than a predetermined value is output, but a component corresponding to a further image motion is not output. Therefore, the video signal output from the adder 24 is a signal obtained by subtracting only the noise component from the video signal from the input terminal 2.

Next, the operation when the processing circuit shown in FIG. 1 is used for reproducing a VTR still image will be described. At this time, the writing to the FIFO 6 is stopped at the timing when the still image reproduction is commanded, and the same screen is repeatedly read from the FIFO 6. Then, the switch 14 supplies the output of the FIFO 6 without passing through the 1HDL 12 to the subtractor 16. The switch 22 is connected to the multiplier 20 side. The coefficient of the multiplier 20 is controlled by a system controller 30.
Controlled by coefficient data (DK) from 28. During reproduction of a still image, the coefficient data DK is always set to 1, and the output of the multiplier 20 becomes the same as the output of the subtractor 16. Therefore, in the adder 24, the input signal is canceled, and the still image signal output from the FIFO 6 is output from the output terminal 26.

In this state, if the coefficient data DK to the multiplier 20 is switched between 0 and 1 in synchronization with the horizontal synchronizing signal (HD) and the vertical synchronizing signal (VD) from the timing controller 8, a part of the screen is displayed. From the stored still image, a composite video signal in which another portion becomes a moving image according to the input video signal can be obtained. Further, for example, if the coefficient data DK is set to 1/2, a composite video signal which becomes a multiplexed screen of a stored still image and a moving image according to the input video signal can be obtained. Further, if the switching timing of the coefficient data DK between 0 and 1 is switched over time, the screen can be switched by wiping, and the value of the coefficient data DK changes from 0 to 1 over time.
, Or by changing from 1 to 0, the screen can be switched by fading.

Next, the enlargement processing of the image according to the present invention and the synthesis, wipe, fade, etc. of the enlarged screen obtained by this enlargement processing with another screen will be described.

FIG. 2 is a schematic diagram used for explaining this processing, and FIGS. 3 and 4 are timing charts for explaining the processing timing of the FIFO 6 when an image is enlarged.
FIG. 3 shows the vertical scanning timing. FIG. 4 shows the processing timing for the horizontal scanning timing.

The synchronization separation circuit 10 separates the vertical synchronization signal (VD) and the horizontal synchronization signal (HD) from the input signal from the terminal 2. These synchronization signals VD and HD determine the timing of each control signal output from the timing controller 8. decide.

In FIG. 3, VD is a vertical synchronization signal, and WE is FIFO6.
RE is a read enable signal, RE is a read enable signal,
WR is a write reset signal, RR is a read reset signal, WD
Is write data and RD is read data.

Now, it is assumed that the portion of the on-screen area a shown in FIG. 2 is enlarged. As shown in FIG. 3, the write enable signal WE is a high level (H) that enables writing during a period in which video signals corresponding to the areas a and b in FIG. 2 are input, and other periods. Becomes a low level (L) at which writing is disabled, and only the video signal corresponding to the area a and the area b is written into the FIFO 6. More specifically, the write enable signal WE changes to H at the timing of scanning the point indicated by X in FIG.
Turn to L after field. The timing at which this write enable signal WE changes to H is determined by X in FIG. 3 and FIG.
This is the timing indicated by. On the other hand, the write reset signal WR
Is a signal having a pulse (in synchronization with the vertical synchronizing signal in the example of FIG. 3) during a period in which the write enable signal is L once in two fields, and the write clock WC to the FIFO 6 acts as a noise reduction circuit. The clock is exactly the same as the one used. Therefore, assuming that the FIFO 6 has a capacity corresponding to the video signal for one field, the video signal data corresponding to the area a and the area b is written for two fields in two field periods. Will be. Numerical values in the schematic diagram of the write data WD in FIG. 3 are field numbers, and hatched portions indicate periods in which there is no write data. Further, a, b, and c in the schematic diagram of the write data WD in FIG. 4 indicate that they are video signal data corresponding to the areas a, b, and c in FIG. 2, respectively.

On the other hand, the read clock RC at this time is the write clock WC
, And the two fields are read out of the FIFO 6 in the two-field period, with the time axis expanded by a factor of two. Since the frequency of the read clock RC is 1/2 of the frequency of the write clock WC, the read enable signal RE becomes the write enable signal WE.
Must be H for a period twice as long as H, and it is H for all periods except the vertical synchronization period. Read reset signal RR is 2
A signal having a pulse at the timing of operating the upper left end in FIG. 2 once in synchronization with the vertical synchronizing signal in the field, whereby the read data RD as schematically shown in FIG. 3 RD and FIG. can get. In other words, the read data from the FIFO 6 is such that only the scanning lines for scanning the areas a and b in FIG. 2 are extended in time axis by a factor of two, and the video signal and the area corresponding to the area a every horizontal scanning period. and the video signal corresponding to b.

CP in FIG. 4 indicates a control pulse supplied from the timing controller 8 to the switch 14. As shown in FIG. 4, the control pulse is H in the horizontal scanning period in which the video signal data corresponding to the area a is output from the FIFO 6, and is in the area b. It becomes L during the horizontal scanning period during which the corresponding video signal data is output. The switch 14 is connected to the 1HDL12 side when the control pulse CP is L, and is connected to the other side when the control pulse CP is H. Therefore, one horizontal scan of the video signal data corresponding to the area a is repeatedly output from the switch 14 every two times. Therefore, the video signal output from the switch 14 is a video signal indicating an image obtained by enlarging the image of the area a in FIG. 2 by two times.

Next, various modes for outputting the enlarged image obtained as described above will be described. First, if you want to use the enlarged image alone, connect switch 4 to the input side and switch
22 is connected to the multiplier 20 side, and the coefficient data DK is always set to 1. As a result, in the adder 24, the input signal component is canceled, and the enlarged image signal output from the switch 14 is output to the output terminal 26.
Will be output.

If the user wants to output the enlarged image as a still image, the writing of the FIFO 6 is stopped. The read reset signal RR of the FIFO 6 is a signal including a pulse for each field. As a result, the switch 14 repeatedly outputs an enlarged signal of the same screen. Other operations are the same as those in the case where the user wants to enlarge the enlarged image alone.

Next, a case where a wipe or a fade is performed between the enlarged image and the input image will be described. From switch 14,
In a state where the enlarged image of the input image or the enlarged image of the still image is output, the coefficient data DK to the multiplier 20 is synchronized with the horizontal synchronization signal (HD) and the vertical synchronization signal (VD) from the timing controller 8. By switching between 0 and 1, it is possible to obtain a composite video signal in which a part of the screen is an enlarged image and the other part is a moving image according to the input video signal.
Further, for example, if the coefficient data DK is set to 1/2, a composite video signal that is a multiplexed screen of an enlarged image and a moving image according to the input video signal can be obtained. Furthermore, 0 of the coefficient data DK
If the timing of switching between 1 and 1 is changed over time, the screen can be switched by a wipe. If the value of the coefficient data DK is changed from 0 to 1 or from 1 to 0 over time, the screen can be switched by fade. It becomes possible.

In these image synthesis, even if the enlarged image is a still image,
The same operation can be performed for a moving image. In particular, when the enlarged image is a moving image, the normal screen and the moving image can be combined on the same screen, and extremely effective image combining can be performed. For example, it is possible to obtain an image signal corresponding to a composite screen as shown in FIG. 5B from an input image signal corresponding to an image as shown in FIG. 5A.

Also, with the switch 14 outputting an enlarged image,
If the switch 4 is connected to the output terminal 26 for the period of one field and the writing to the FIFO 6 is stopped simultaneously with the end of this period, it is possible to obtain a still image in which the enlarged image is further enlarged.

According to the video signal processing apparatus of the embodiment as described above, with a simple circuit configuration, noise reduction processing, still image output processing, image synthesis processing, wipe, fade, image enlargement processing, enlarged image still image output processing, enlargement Image synthesis processing using images,
Wipe using enlarged image, fade using enlarged image,
Various processes such as image re-enlargement can be realized with the same circuit configuration.

Note that the still image output processing, the image synthesis processing, the wipe, the fade, the image enlargement processing, the image synthesis processing using the enlarged image, the wipe using the enlarged image, and the fade using the enlarged image are performed from the FIFO 6 to the adder 24. The present invention can be realized by any of the above configurations, and the present invention includes all the configurations having such a configuration.

[Effects of the Invention] As described above, according to the present invention, noise reduction processing with a simple configuration, wiping between an enlarged image and another image,
Fade processing can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a video signal processing circuit as one embodiment of the present invention, FIG. 2 is a schematic diagram for explaining an enlargement process by the processing circuit of FIG. 1, FIG. 3, FIG. 5 is a timing chart for explaining the operation of each part of the circuit shown in FIG. 1 during the enlargement process. FIG. 5 is a diagram showing an example of a special screen obtained by the circuit shown in FIG. In the figure, 2 is an input terminal, 4 is a switch, 6 is a FIFO having a capacity of one field, 8 is a timing controller, 10 is a sync separation circuit, 12 is 1HDL, 14 is a switch, 16 is a subtractor, 18 is a non-linear circuit, 20 is a multiplier, 24 is an adder, 26 is an output terminal, 28 is a coefficient control circuit, 30 is a system controller, and 32 is an operation unit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-114471 (JP, A) JP-A-57-154981 (JP, A) JP-A-63-109671 (JP, A) JP-A 64-64 15879 (JP, A) JP-A-63-232577 (JP, A) JP-A-54-160550 (JP, U)

Claims (2)

(57) [Claims] A memory for storing a video signal for one screen, a delay function for delaying the video signal for one screen period using the memory, and a delay function for writing the video signal stored in the memory. A processing circuit having an image enlargement function of obtaining an enlarged image by reading in accordance with a low frequency clock; a subtractor for obtaining a difference between a video signal output from the processing circuit and an input video signal; irrespective of its input level A coefficient controllable to the output of the subtractor by selectively using a first coefficient unit multiplied by the determined variable coefficient and a second coefficient unit multiplied by a coefficient determined according to the input level. A multiplication circuit, an adder for adding the output of the multiplication circuit and the video signal, and the first coefficient unit using the processing circuit as an image enlargement circuit. Signal processing comprising: a first mode for performing processing, and mode switching means for switching a mode between a second mode in which the processing circuit is used as a delay circuit and the second coefficient unit performing the multiplication processing. apparatus. 2. In the first mode, the first mode is synchronized with a read operation of the video signal from the memory.
2. The video signal processing apparatus according to claim 1, further comprising a control circuit for changing a coefficient of said multiplier.