JP2896013B2 - Data processing circuit of television system conversion system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing circuit of a television system conversion system using a common data processing clock after reading.

[0002]

2. Description of the Related Art When a MUSE signal is converted into a standard television signal and displayed on a standard television screen, two types of display modes are employed because the aspect ratio between the high-vision screen and the standard television screen is different. The first display mode is a wide display mode for displaying a high-definition screen corresponding to the width of the standard television screen. Normally, video data is selected at a ratio of one line to three lines of the MUSE signal, and the standard television screen is displayed. A blanking area is formed above and below. The second display mode is a zoom display mode for displaying a high-definition screen corresponding to the vertical width of the standard television screen.
Video data is selected at a rate of one line for every two lines of the E signal, and only a central portion of each line is selected to cut and display a video projected on a high-definition screen.

A data processing circuit for switching between these two types of display modes is disclosed in Japanese Unexamined Patent Publication No. Hei.
04N 7/01). In this prior art, the stored data read in the second display mode is frequency-converted by a factor of two, the return noise is band-limited in the frequency-converted state, and then analogized at the data frequency.

[0004]

However, in the above-described configuration, the clock after the data frequency conversion must be doubled in accordance with the display mode. Since two types of processing clocks after the frequency conversion are required, the circuit is also complicated when performing video processing such as superimposition.

Therefore, it is necessary to use a common data processing clock after data reading.

[0006]

According to the present invention, there is provided sampling means for sampling a MUSE signal in synchronization with a first reference clock for the MUSE signal, and MUSE data in a display range corresponding to a selected display mode. A storage control circuit for sequentially storing data in a memory in synchronization with a reference clock; and a second control signal for a standard television signal in the first display mode.
A read control circuit for sequentially reading storage data from a memory in synchronization with a reference clock, and sequentially reading storage data in a second display mode while synchronizing with the second reference clock and prohibiting reading at a constant interval; A data frequency conversion circuit for converting the storage data read out in step 2 into the second reference clock frequency, a data selection circuit for selecting storage data in the first display mode, and selecting frequency conversion data in the second display mode; A video processing circuit for performing data processing on the selected data with the second reference clock and a DA conversion circuit for converting the video processing output into an analog with the second reference clock are provided.

[0007]

According to the present invention, MUSE data before storage is processed by the first reference clock regardless of the display mode, and storage data after read is processed by the second reference clock regardless of the display mode.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the illustrated embodiments. FIG. 1 is a circuit block diagram showing one embodiment of the present invention. First, the MUSE signal is input low-pass filter 1
Is input to the AD conversion circuit 2 via the. AD conversion circuit 2
Are digitized in synchronization with the first reference clock.
The AD converted MUSE data is supplied to the first video processing circuit 3 and the first synchronization timing circuit 4. The first synchronization timing circuit 4 separates a synchronization component in the MUSE data and performs a first synchronization of 16.2 MHz to perform phase synchronization with the synchronization component.
In addition to forming a reference clock, various timing signals are generated according to the display mode selection signal. Further, the first video processing circuit 3 uses the input timing signal and the first reference clock to limit the frequency band in the vertical direction accompanying the conversion of the number of scanning lines and to perform field interpolation to reduce the data frequency to 2 bits. Processing such as multiplication is executed.

A FIFO memory 5 for inputting the first video processing output stores video data in a range necessary for display at an appropriate line interval in accordance with a clock twice the first reference clock and a timing signal corresponding to a display mode. I do. Therefore, in the first display mode, the video data of the effective video range is stored every three lines, and in the second display mode, the video data of the central portion of each line is stored every two lines.

Further, the FIFO memory 5 sequentially reads out stored data with a timing signal corresponding to a display mode in synchronization with a second reference clock corresponding to a synchronization frequency of a standard television signal. The frequency of the second reference clock is 1
4.742 MHz and the frequency ratio of both clocks is
100: 91. In the present embodiment, the reading of the timing signal of the second display mode is paused at a rate of one cycle to three cycles of the second reference clock, and the read data is sent to the data frequency conversion circuit 6 for data interpolation. You are typing.

As shown in detail in FIG. 3, the data frequency conversion circuit 6 is sequentially input to a first delay circuit 61 and a second delay circuit 62 for delaying input data by one cycle with a second reference clock. The input data contains indefinite data once every three periods due to the prohibition of data reading. The first selection circuit 63 that inputs the non-delayed data D2 and the first delayed data D1 operates to select the non-delayed data at an indefinite timing of the first delayed data D1 by the first selection signal S1. The first selection data M1 shown in FIG. Further, the second selection circuit 64 that inputs the second delay data D0 and the first delay data D1 operates so as to select the second delay data at an indefinite timing of the first delay data D1 by the second selection signal S1. The second shown in FIG.
The selection data M2 is formed.

The first selection data M1 and the second delay data D0
Is input to the first adder circuit 65, the first adder circuit 65 shown in FIG.
The addition data A1 is derived. This first addition data A1
Generates undefined data at undefined timing of the second delay data D2. Further, the second addition circuit 66 that inputs the first addition data A1 and the second selection data M2 derives the second addition data A2 illustrated in FIG. The second addition data A2 generates undefined data at an undefined timing of the first addition data D2.

The second addition data A2 including the periodic indefinite data is supplied to the third selection circuit 6 together with the first delay data D1.
7 and the second selection signal D2, which is delayed from the first selection signal S1 by one period of the second reference clock, replaces the indefinite data of the second addition data A2 with the first delay data D1. As a result, the output data M3 is subjected to desired interpolation by proportional distribution as shown in FIG.

The frequency conversion data is input to the data selection circuit 7 together with the read data, and the data of the corresponding display mode is selected and derived according to the display mode selection signal. The selected data is input to the second video processing circuit 8, and subjected to blanking processing, TCI decoding processing, enhancer processing, and the like in synchronization with the second reference clock and various timing signals.

The processed data is transmitted to a DA converter 10 at a second
It is converted into an analog signal in synchronization with the reference clock and is derived via a common output low-pass filter 11 regardless of the display mode. Note that the second reference clock and the timing signal are
The synchronous timing circuit 9 is formed. The second synchronization timing circuit 9 includes a frame synchronization signal serving as a phase reference for various timing signals and a P reference for forming a second reference clock.
A frequency of the LL circuit and a first reference clock serving as a phase reference are input from the first synchronization timing circuit 4;
The timing signal is switched according to the display mode selection signal.

Therefore, according to the present embodiment, regardless of the display mode, processing synchronized with the first reference clock is performed in the preceding stage of the FIFO memory 5, and processing synchronized with the second reference clock is performed in the subsequent stage of the FIFO memory 5. Done.

[0017]

Thus, according to the present invention, since data processing is performed by a common reference clock at the subsequent stage of the memory, compactness and suppression of the amount of heat generation can be achieved, and the effect is large.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention.

FIG. 2 is an explanatory diagram of a signal arrangement of each unit of the data frequency conversion circuit according to the embodiment.

FIG. 3 is a detailed circuit block diagram of the data frequency conversion circuit of the present embodiment.

[Explanation of symbols]

 2 AD conversion circuit 5 FIFO memory 6 Data frequency conversion circuit 7 Data selection circuit 10 DA conversion circuit

Claims (1)

(57) [Claims] 1. A first display mode for converting a MUSE signal into a standard television signal and displaying the converted image in a horizontal direction of the standard television screen, and a converted image in a vertical direction of the standard television screen. In a television system conversion system for selectively switching between a second display mode for display and a display, a sampling means for sampling a MUSE signal in synchronization with a first reference clock for the MUSE signal to form MUSE data A storage control circuit for sequentially storing MUSE data in a display range corresponding to the selected display mode in a memory in synchronization with the first reference clock; and a second reference clock for a standard television signal in the first display mode. In the second display mode, the stored data is sequentially read out from the memory in synchronization with the second reference clock and for a fixed time. A read control circuit for sequentially reading storage data while prohibiting reading at intervals, a data frequency conversion circuit for converting the storage data read in the second display mode to the second reference clock frequency, and a storage in the first display mode. A data selection circuit for selecting data and selecting frequency-converted data in the second display mode; a video processing circuit for performing data processing on the selected data with the second reference clock; A data processing circuit of a television system conversion system in which a D / A conversion circuit for converting to analog is arranged.