JP4016366B2 - Interface device and video signal processing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an interface device and a video signal processing method, and is suitable for application to, for example, an interface device provided in a television apparatus.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there is a device called a time base corrector (Time Base Corrector) that reduces signal time-axis fluctuations called jitter and skew in an analog video signal. The time base collector writes a digital video signal obtained by digitally converting an analog video signal into a memory of the time base collector in synchronization with the clock of the analog video signal. The digital video signal stored in the memory is read out in synchronization with a stable read clock supplied from a predetermined clock generator so as to remove the time-axis fluctuation of the signal included in the analog video signal. Has been made.
[0003]
On the other hand, in a television receiver, an input video signal having an image format of 525 interlace (525 scanning lines, interlaced scanning) is converted into 1050 interlaced (1050 scanning lines, interlaced scanning) or 525 non-interlaced (525 scanning lines, sequentially). Scanning) format conversion and output, or 625 interlaced (625 scanning lines, interlaced scanning) input video signal 1250 interlaced (1250 scanning lines, interlaced scanning) or 625 non-interlaced (625 scanning lines, sequential scanning) ) Have a double speed conversion device for converting the format and outputting. In such a double speed conversion device, a more stable output signal can be obtained by providing a time base collector in the previous stage and inputting a video signal with reduced temporal fluctuations by the time base collector. .
[0004]
That is, FIG. 3 shows the video signal processing apparatus 1, and an analog video signal S1 inputted from the outside is digitally converted by the analog / digital conversion unit 10 and outputted to the time base collector 11 as a digital video signal S10.
[0005]
The time base collector 11 writes the digital video signal S10 into a memory (not shown) included in the time base collector 11 in synchronization with an analog video clock S2 that is a synchronization signal of the analog video signal S1. The time base collector 11 sequentially reads the digital video signal S10 written in the memory in synchronization with the read clock S16 supplied from the double speed conversion unit 15. Here, the double speed conversion unit 15 generates a clock having a stable frequency, and generates a read clock S16 based on the generated clock.
[0006]
Thus, the time base collector 11 reduces the time axis fluctuation of the digital video signal S10 and outputs it.
[0007]
The double speed conversion unit 15 receives the digital video signal S10 output from the time base corrector 11, converts the image format of the digital video signal S10 from 525 interlace to 1050 interlace or 525 noninterlace, and converts the digital video signal S15. Output as.
[0008]
Thus, the video signal processing apparatus 1 reduces the temporal variation included in the analog video signal S1 and converts and outputs the image format.
[0009]
[Problems to be solved by the invention]
In a video signal processing device combining such a time base collector and a double speed conversion device, digital video output from a digital television receiver or MPEG (Moving Picture Experts Group) decoding device such as a DVD (Digital Video Disc) It is conceivable that a signal is input as an external input signal, converted at double speed, and output.
[0010]
For example, it is conceivable that a video signal selection unit is provided in front of the analog / digital conversion unit, and either an analog video signal or an external input signal is selected and input to the analog / digital conversion unit.
[0011]
That is, in FIG. 4 in which parts corresponding to those in FIG. 3 are assigned the same reference numerals, 2 denotes a video signal processing apparatus as a whole, and has a video signal selection unit 5 before the analog / digital conversion unit 10.
[0012]
In the analog signal input mode, the video signal selector 5 selects the analog video signal S 1 and supplies it to the analog / digital converter 10. The analog / digital converter 10 digitally converts the analog video signal S1 and outputs the digital video signal S10 to the time base collector 11.
[0013]
In the analog signal input mode, the synchronization signal selection unit 6 selects an analog video clock S2 that is a synchronization signal of the analog video signal S1, and supplies this to the time base collector 11 as a write clock S6. The time base collector 11 writes the digital video signal S10 in a memory (not shown) included in the time base collector 11 in synchronization with the write clock S6.
[0014]
The time base collector 11 sequentially reads the digital video signal S10 written in the memory in synchronization with the read clock S16 supplied from the double speed converter 15. The double speed conversion unit 15 receives the digital video signal S10 output from the time base corrector 11, converts the image format of the digital video signal S10 from 525 interlace to 1050 interlace or 525 noninterlace, and converts the digital video signal S15. Output as. Thus, in the analog signal input mode, the video signal processing device 2 inputs the analog video signal S1, converts the image format thereof, and outputs it.
[0015]
On the other hand, in the external input mode, the video signal processing apparatus 2 inputs the digital video signal S20 supplied from the MPEG decoding unit 20 to the digital / analog conversion unit 17. The digital / analog conversion unit 17 converts the digital video signal S20 into an analog signal and supplies it to the video signal selection unit 5 as the analog video signal S17. In the external input mode, the video signal selector 5 selects the analog video signal S17 supplied from the digital / analog converter 16 and supplies it to the analog / digital converter 10. The analog / digital converter 10 digitally converts the analog video signal S17 and outputs it to the time base collector 11 as a digital video signal S10.
[0016]
The synchronization signal selection unit 6 selects the digital video clock S21 supplied from the MPEG decoding unit 20 in the external input mode, and supplies this to the time base collector 11 as the write clock S6. Then, the time base collector 11 writes the digital video signal S10 into the memory of the time base collector 11 in synchronization with the write clock S6.
[0017]
Similar to the analog signal input mode, the time base collector 11 sequentially reads the digital video signal S10 written in the memory in synchronization with the read clock S16 supplied from the double speed converter 15. The double speed converter 15 receives the digital video signal S10 output from the time base collector 11, converts the image format of the digital video signal S10, and outputs it as a digital video signal S15. Thus, the video signal processing apparatus 2 inputs the digital video signal S20 in the external input mode, converts the image format, and outputs it.
[0018]
However, in such a video signal processing apparatus 2, the digital video signal S20 is once converted into an analog signal and then converted again into a digital signal. This causes problems that the signal is deteriorated and the configuration becomes complicated. is doing.
[0019]
It is also conceivable that a video signal selection unit is provided before the double speed conversion unit, and either an analog video signal or an external input signal is selected and input to the double speed conversion unit.
[0020]
That is, in FIG. 5, in which the same reference numerals are assigned to the common parts with FIG. 3, 3 denotes a video signal processing apparatus as a whole, and has the video signal selection unit 5 in the previous stage of the double speed conversion unit 15.
[0021]
In the analog signal input mode, the video signal processing device 3 inputs the analog video signal S1 to the analog / digital conversion unit 10. The analog / digital converter 10 digitally converts the analog video signal S1 and outputs it to the time base collector 11 as a digital video signal S10. The time base collector 11 writes the digital video signal S10 into a memory (not shown) included in the time base collector 11 in synchronization with an analog video clock S2 that is a synchronization signal of the analog video signal S1. The time base collector 11 sequentially reads and outputs the digital video signal S10 written in the memory in synchronization with the read clock S25 supplied from the clock generator 25.
[0022]
In the analog signal input mode, the video signal selector 5 selects the digital video signal S 11 output from the time base collector 11 and supplies it to the double speed converter 15. The double speed converter 15 receives the digital video signal S11, converts the image format of the digital video signal S11, and outputs it as a digital video signal S15. Thus, in the analog signal input mode, the video signal processing device 3 inputs the analog video signal S1, converts the image format thereof, and outputs it.
[0023]
On the other hand, in the external input mode, the video signal selection unit 5 selects the digital video signal S20 supplied from the MPEG decoding unit 20 and supplies it to the double speed conversion unit 15. The double speed converter 15 receives the digital video signal S20, converts the image format of the digital video signal S20, and outputs it as a digital video signal S15. Thus, the video signal processing apparatus 3 inputs the digital video signal S20 in the external input mode, converts the image format, and outputs it.
[0024]
However, in the video signal processing apparatus 3 having such a configuration, in order to transfer digital video signals in synchronization between the MPEG decoding unit 20 and the double speed conversion unit 15 and between the time base collector 11 and the double speed conversion unit 15, It is necessary to configure the system so that each operates with the same clock. That is, the video signal processing device 3 is provided with a clock generation unit 25 so that the MPEG decoding unit 20, the double speed conversion unit 15, and the time base collector 11 operate in synchronization with the clock 25 supplied from the clock generation unit 25. For this reason, it is difficult to provide the MPEG decoding unit 20 independently from the video signal processing apparatus 3, and there is a problem that the circuit scale becomes large and complicated.
[0025]
The present invention has been made in consideration of the above points, and with a simple configuration, an analog video signal is input and output with reduced time-axis fluctuations, or a digital video signal is input and the clock is converted. Thus, an interface device and a video signal processing method are proposed.
[0026]
[Means for Solving the Problems]
In order to solve such a problem, in the present invention, an analog / digital conversion means for converting an analog video signal input from the outside into a digital signal to generate a first digital video signal, and an analog video signal supplied from the outside A synchronization signal generating means for generating a first synchronization signal that follows a time axis variation of the analog signal based on the analog synchronization signal, and a first digital video signal or a second digital video signal supplied from outside Video signal selection means for selecting one of them and outputting it as a selected video signal, and when the first digital video signal is selected, the first synchronization signal is selected as the write synchronization signal, and the second digital video signal selected as the second writing a synchronization signal synchronizing signal supplied together with the second digital video signal if but selected That a synchronizing signal selection means, writing in synchronization with the selected write synchronizing signal selected video signal, by reading in synchronism with the synchronizing signal out read, if the first digital video signal is selected first The time axis fluctuation in the digital video signal is reduced, and when the second digital video signal is selected, a clock transfer means for converting the clock of the second digital video signal is provided.
[0027]
When inputting an analog video signal, the clock changing means is used as a time base collector for reducing the time base fluctuation of the first digital video signal obtained by digitally converting the analog video signal, and when inputting the digital video signal, By using the clock transfer means as a clock transfer device for converting the clock of the digital video signal, the configuration of the entire interface device can be simplified.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
[0029]
In FIG. 1, in which parts corresponding to those in FIG. 4 are assigned the same reference numerals, 4 denotes a video signal processing apparatus as a whole. The video signal processing device 4 is provided in a television device (not shown), and is supplied from an analog video signal S1 supplied from a tuner (not shown) included in the television device or from an external MPEG decoding unit 20. Either one of the digital video signals S20 is input, double speed conversion processing is performed on this, and the digital video signal S15 is output to the video display means of the television apparatus.
[0030]
In the analog signal input mode, the video signal processing device 4 inputs the analog video signal S1 to the analog / digital conversion unit 10. The analog / digital conversion unit 10 digitally converts the analog video signal S1 to generate a digital video signal S10. The analog / digital conversion unit 10 generates a write clock S23 and a timing pulse S24 supplied from an AFC (Automatic Frequency Control) unit 23 as a synchronization signal generation unit. Synchronously output to the video signal selector 5.
[0031]
In the analog signal input mode, the video signal selection unit 5 selects the digital video signal S10 output from the analog / digital conversion unit 10 and supplies it to the clock transfer unit 30.
[0032]
At this time, based on the synchronization signal S2 of the analog video signal S1, the AFC unit 23 generates a write clock S23 and a write timing pulse S24 that follow the time axis fluctuation of the synchronization signal S2, and generates these signals in the analog / digital conversion unit 10 And supplied to the synchronization signal selector 6. In the analog video signal input mode, the synchronization signal selection unit 6 selects the write clock S23 and the write timing pulse S24 supplied from the AFC unit 22 and supplies them to the clock transfer unit 30.
[0033]
FIG. 2 shows a clock transfer unit 30 as a whole, and a memory unit 31 that can independently input a write clock and a read clock, a write timing pulse and a read timing pulse, and can write and read data at different timings, A write address control unit 32 that controls a data write address of the memory unit 31 based on a write clock and a write timing pulse, and a read address control that controls a data read address from the memory unit 31 based on a read clock and a read timing pulse. And an overtaking prevention unit 33 for preventing the read address from overtaking the write address.
[0034]
In the analog signal input mode, the write address control unit 32 writes the write address signal S32 indicating the data write address of the memory unit 31 based on the write clock S23 and the write timing pulse S24 supplied from the synchronization signal selection unit 6 (FIG. 1). Is supplied to the memory unit 31. The memory unit 31 writes each data of the digital video signal S10 at an address indicated by the write address signal S32 in synchronization with the write clock S23 and the write timing pulse S24.
[0035]
Thus, in the analog signal input mode, the video signal processing device 4 converts the digital video signal S10 obtained by analog / digital conversion of the analog video signal S1 into the write clock S23 following the time axis variation of the synchronization signal S2 of the analog video signal S1. In synchronization with the write timing pulse S24, data is sequentially written in the memory 31 of the clock transfer unit 30.
[0036]
On the other hand, in the external input mode, the video signal selection unit 5 shown in FIG. 1 selects the digital video signal S20 supplied from the MPEG decoding unit 20 and supplies it to the clock transfer unit 30. At this time, the synchronization signal selection unit 6 selects the write clock S21 and the write timing pulse S22 synchronized with the digital video signal S20 supplied from the MPEG decoding unit 20, and supplies them to the clock transfer unit 30.
[0037]
In the external input mode, the write address control unit 32 shown in FIG. 2 indicates the data write address of the memory unit 31 based on the write clock S21 and the write timing pulse S22 supplied from the synchronization signal selection unit 6 (FIG. 1). A write address signal S32 is generated and supplied to the memory unit 31. The memory unit 31 writes each data of the digital video signal S20 at an address indicated by the write address signal S32 in synchronization with the write clock S21 and the write timing pulse S22.
[0038]
Thus, in the external input mode, the video signal processing device 4 synchronizes the digital video signal S20 supplied from the MPEG decoding unit 20 with the clock transfer unit 30 in synchronization with the write clock S21 and the write timing pulse S21 synchronized with the digital video signal S20. Are sequentially written in the memory 31 of the.
[0039]
The video signal processing device 4 synchronizes the digital video signal S10 or S20 written in the memory 31 in synchronization with the respective synchronization signals in this way with the read clock S17 and the read timing pulse S18 supplied from the double speed conversion unit 15. Are read out and output to the double speed converter 15.
[0040]
That is, in FIG. 2, the read address control unit 34 generates a read address signal S34 indicating a data read address from the memory unit 31 based on the read clock S17 and the read timing pulse S18 supplied from the double speed conversion unit 15, Is supplied to the memory unit 31. The double speed conversion unit 15 generates the read clock S17 and the read timing pulse S18 based on a stable clock generated by a clock generation unit (not shown) included in the double speed conversion unit 15, and the read clock S17 and read It operates in synchronization with the timing pulse S18. The memory unit 31 sequentially reads each data of the digital video signal S10 or S20 from the address indicated by the read address signal S34 in synchronization with the read clock S17 and the read timing pulse S18, and outputs it to the double speed conversion unit 15.
[0041]
The double speed conversion unit 15 receives the digital video signal S10 or S20 output from the clock transfer unit 30, converts the image format of the digital video signal S10 or S20, and outputs the digital video signal S15. Thus, the video signal processing device 4 inputs either the analog video signal S1 supplied from the tuner (not shown) or the digital video signal S20 supplied from the MPEG decoding unit 20, and performs a double speed conversion process on this. And output as a digital video signal S15.
[0042]
In the above configuration, the video signal processing device 4 digitally converts the analog video signal S1 supplied from the outside in the analog signal input mode to generate the digital video signal S10, and the digital video signal S10 is converted to the clock transfer unit 30. Is written in synchronism with the write clock S23 and the write timing pulse S24 following the time axis fluctuation of the analog video signal S1. The video signal processing device 4 outputs the digital video signal S10 written in the memory 31 to the read double speed conversion unit 15 in synchronization with the stable read clock S17 and read timing pulse S18 supplied from the double speed conversion unit 15. .
[0043]
Thus, in the analog signal input mode, the clock transfer unit 30 operates as a time base collector that reduces time-axis fluctuations of the digital video signal S10 obtained by analog / digital conversion of the analog video signal S1.
[0044]
On the other hand, in the external input mode, the video signal processing device 4 inputs the digital video signal S20 supplied from the MPEG decoding unit 20, and the digital video signal S20 is transferred to the memory 31 of the clock transfer unit 30 and the digital video signal S20. Writing is performed in synchronization with the synchronized write clock S21 and write timing pulse S22. Then, the video signal processing device 4 outputs the digital video signal S20 written in the memory 31 to the read double speed converter 15 in synchronization with the read clock S17 and the read timing pulse S18 supplied from the double speed converter 15.
[0045]
Thus, in the external input mode, the clock transfer unit 30 operates as a clock transfer device that converts the clock of the digital video signal S20 into the operation clock of the double speed conversion unit 15 and outputs it.
[0046]
According to the above configuration, the clock transfer unit 30 is used as a time base collector for reducing the time base fluctuation of the digital video signal S10 obtained by digital conversion of the analog video signal S1 in the analog signal input mode, and in the external input mode. The configuration can be simplified by using it as a clock transfer device that converts the clock of the digital video signal S20.
[0047]
In the above-described embodiment, the output from the clock transfer unit is input to the double speed conversion unit. However, the present invention is not limited to this, and for example, a noise reduction device using a field memory, or a field frequency double speed. It may be inputted to various video signal processing circuits such as a flicker-free device that reduces the flickering of the screen.
[0048]
In the above-described embodiment, the digital video signal supplied from the MPEG decoding unit is input. However, the present invention is not limited to this, and various digital video signals such as a DV (Digital Video) device can be used. A digital video signal may be input from a supply source.
[0049]
【The invention's effect】
As described above, according to the present invention, when an analog video signal is input, the clock transfer means is used as a time base collector that reduces time-axis fluctuations of the digital video signal obtained by digitally converting the analog video signal, and is externally used. When inputting a digital video signal, an interface device having a simple configuration can be obtained by using the clock transfer means as a clock transfer device for converting the clock of the digital video signal.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a video signal processing apparatus according to the present invention.
FIG. 2 is a block diagram illustrating a clock transfer unit.
FIG. 3 is a block diagram showing a video signal processing apparatus.
FIG. 4 is a block diagram showing a video signal processing apparatus.
FIG. 5 is a block diagram showing a video signal processing apparatus.
[Explanation of symbols]
1, 2, 3, 4 ... Video signal processing device, 5 ... Input signal selection unit, 6 ... Synchronization signal selection unit, 10 ... Analog / digital conversion unit, 11 ... Time base collector, 15 ... Double speed Conversion unit, 17 ... Digital / analog conversion unit, 20 ... MPEG decoding unit, 23 ... AFC unit, 25 ... Clock generation unit, 30 ... Clock transfer unit, 31 ... Memory unit, 32 ... Write address Control unit 33... Overtaking prevention unit 34... Read address control unit.

Claims (6)

Analog / digital conversion means for converting an analog video signal input from the outside into a digital signal to generate a first digital video signal;
Synchronization signal generating means for generating a first synchronization signal following the time-axis fluctuation of the analog signal based on the analog synchronization signal of the analog video signal supplied from the outside;
Video signal selection means for selecting one of the first digital video signal and the second digital video signal supplied from the outside and outputting as a selected video signal;
When the first digital video signal is selected, the first synchronization signal is selected as a write synchronization signal, and when the second digital video signal is selected, the first digital video signal is supplied together with the second digital video signal. the second synchronizing signal and the synchronizing signal selection means for selecting as said write synchronizing signal that,
Writing the selected video signal in synchronization with the selected write synchronization signal, by reading in synchronism with the synchronizing signal out read, if the first digital video signal is selected in the first digital video An interface device comprising: clock changing means for reducing time-axis fluctuations in a signal and converting the clock of the second digital video signal when the second digital video signal is selected . The interface device is
The interface apparatus according to claim 1, wherein the interface apparatus is provided in a television device and inputs the selected video signal to a video display unit of the television device. The readout synchronization signal is
2. The interface device according to claim 1, wherein the interface device is supplied from an external read synchronization signal generating means . The read synchronization signal generating means includes:
Predetermined video processing using the readout synchronization signal is executed on the first and second digital video signals output from the clock transfer means.
The interface device according to claim 1. The clock transfer means is
Control so that the read address for reading the selected video signal does not overtake the write address for writing the selected video signal
The interface device according to claim 1 . Converting an externally input analog video signal to a digital signal to generate a first digital video signal;
Based on the analog synchronization signal of the analog video signal supplied from the outside, a first synchronization signal that follows the time axis variation of the analog signal is generated,
Selecting one of the first digital video signal and the second digital video signal supplied from the outside as a selection video signal;
When the first digital video signal is selected, the first synchronization signal is selected as a write synchronization signal, and when the second digital video signal is selected, the first digital video signal is supplied together with the second digital video signal. the second synchronization signal is selected as the write synchronization signal that,
Writing the selected video signal in synchronization with the selected write synchronization signal, by Succoth read out in synchronization with the synchronization signal out read, if the first digital video signal is selected in the first reducing time base fluctuations in a digital video signal, a video signal processing method if the second digital movies image signal is selected which is characterized by converting a clock of said second digital video signal.

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