JP2531098B2 - 2H phase correction circuit for video signal - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a 2H phase correction circuit for video signals, and more particularly to a circuit for performing automatic phase correction of television video signals.

[0002]

2. Description of the Related Art Generally, in a conventional television, in an automatic phase correction circuit for a video signal having a phase adjusting function for a 2H period, a horizontal phase is based on a horizontal synchronization (H-SYNC) phase, and a phase shift of an input signal is caused. The determination as to whether it is within 1 line (H) or 1H or more is made based on the vertical synchronization (V-SYNC) phase. Normally, switching of television video signals is
Since it is performed at the switching timing created from V-SYNC, V
-Switched in the phase immediately after SYNC. As prior applications related to this technique, Japanese Patent Laid-Open Nos. 1-215193 and 2-28
There is a 5895 publication.

[0003]

However, in the conventional technique, since the phase correction in the 2H period uses the V-SYNC information, the phase correction is completed one field later. Therefore, there is a possibility that the phase correction with a 1H shift may be performed on one screen immediately after the image switching, and the normal phase correction was completed only after the V-SYNC period came. Therefore, the output image may go up and down by 1H (two rasters on the monitor) on the second screen after the input signal is switched, and the up and down movement of this image appears as an obstacle to the screen shock.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a phase correction circuit for an image signal, which can appropriately correct the phase from the screen immediately after switching and completely eliminate the screen shock.

[0005]

To achieve the above object, a video signal for correcting the phase of the image data by storing the image data of two lines of the video signal of the present invention and reading the stored image data. The 2H phase correction circuit determines the polarity of the phase of the burst signal included in the video signal and the H pulse generation circuit that generates the H pulse based on the synchronization signal included in the video signal, and determines the line flip-flop pulse. A color frame determination circuit for generation, a 2H memory capable of storing image data for at least two lines, and
The color frame determination circuit inputs a H pulse, and a line flip-flop is constructed according to the input H pulse and the polarity of the phase of the burst signal. L of pulse
/ H is inverted, and the memory control unit inputs this line flip-flop pulse, and the memory control unit stores the image data of one line of the video signal in the 2H memory for each L / H of the input line flip-flop pulse. Due to
The feature is that the image data is managed for each line based on the polarity of the phase of the burst signal.

[0006]

The 2H phase correction circuit for a video signal of the present invention generates a line flip-flop pulse which is inverted to L / H depending on the sync signal contained in the video signal and the polarity of the phase of the burst signal. The writing operation to the 2H memory and the reading operation from the 2H memory are controlled. Therefore, the image data of the video signal can be managed line by line immediately after the synchronization signal and the burst signal.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a 2-frame phase correction circuit for video signals according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 1, there is shown an embodiment of an automatic phase correction circuit for a television video signal to which the 2-frame phase correction circuit for a video signal of the present invention is applied. Hereinafter, the configuration of the present invention will be described in detail based on the embodiment shown in FIG.

The video signal 2H phase correction circuit of this embodiment is composed of A / D conversion circuits 1, 2H memory 2, D / A conversion circuit 3, write (W) start pulse generation circuit section 4, and read (R). It comprises a start pulse generating circuit section 5, a memory read control pulse generating circuit 6 and a memory address control generating circuit 7.

The A / D conversion circuit 1 is an input terminal 1 of this circuit.
The video signal composed of the analog signal input to 1
This is a circuit for converting into a PCM video signal composed of a digital signal and outputting it to the output terminal 12. 2H memory 2
It is a temporary memory having a memory capacity capable of storing digital signals forming two images on a television screen.
The D / A conversion circuit 3 is a circuit that converts a digital image signal into an analog image signal and outputs the analog image signal.

The W start pulse generation circuit section 4 is a circuit section which receives a video signal input to the input terminal 11 as an input signal and generates and outputs a write start pulse based on this signal. The start pulse signal output from the W start pulse generating circuit section 4 is output to the memory address control generating circuit 7.

The R start pulse generation circuit section 5 is a circuit section that generates a read start pulse based on this signal using the reference signal input to the read command input terminal 13 as an input signal and outputs the read start pulse. The reference signal is a request signal from a host device equipped with a 2-frame phase correction circuit for this image signal. The start pulse signal output from the R start pulse generating circuit section 5 is output to the memory address control generating circuit 7. The R start pulse generation circuit section 5
And the W start pulse generation circuit section 4 are different only in the names of signals to be processed, and the internal circuit configurations are the same.

The memory read control pulse generating circuit 6 is a circuit for generating and outputting a pulse based on the input of the reference signal. This output is connected to the memory address control generation circuit 7.

The memory address control generation circuit 6 determines a write memory address of a 2H cycle according to a predetermined procedure based on the W start pulse output from the W start pulse generation circuit section 4, and stores the PCM data of the input image signal in the 2H memory. It is a circuit that decides which address of 2 to write. Further, the R start pulse output from the R start pulse generating circuit unit 5 is processed in the same manner as in the case of the W start pulse, the read memory address of the 2H cycle is determined, and the memory data of which address is set for the phase of the reference signal. Whether to read is decided. This address signal is connected to the 2H memory 2. The address output based on the pulse signal from the W start pulse generation circuit unit 4 is for the 2H memory 2 to store the image signal. The address output based on the pulse signals from the R start pulse generation circuit section 5 and the memory call control pulse generation circuit 6 is for reading the image data stored in the 2H memory 2.

The W start pulse generation circuit section 4 and the R start pulse generation circuit section 5 having the above-mentioned functions are provided in the burst extraction circuit 41, the sync separation circuit 42, the color frame determination circuit 43, the H pulse generation circuit 44 and the writing ( (Or read) start pulse generating circuit 45. In this internal configuration, the input signal line is
It is connected in parallel to the burst extraction circuit 41 and the sync separation circuit 42. Although the following description is based on the W start pulse generation circuit unit 4, the same applies to the R start pulse generation circuit unit 5 in principle.

The burst extraction circuit 41 constituting the W start pulse generation circuit section 4 is a circuit for converting a video signal into a continuous subcarrier signal whose frequency and phase match the burst signal as an input signal. The sync separation circuit 42 is a circuit that receives the video signal as an input signal and separates the sync signal (SYNC) from the video signal and outputs the sync signal (SYNC). The color frame determination circuit 43 inputs the subcarrier signal output from the burst extraction circuit 41 and the WH pulse output from the H pulse generation circuit 44, performs phase comparison for each frame, and inverts the polarity for each frame. It is a circuit that outputs a write line flip-flop pulse (WLFF) of the image data. The H pulse generation circuit 44 is a circuit that inputs the synchronization signal output from the synchronization separation circuit 42 and outputs a WH pulse extracted only in the horizontal period (H period).
The write start pulse generation circuit 45 inputs the WH pulse output from the H pulse generation circuit 44 and the WLFF pulse output from the color frame determination circuit 43, and outputs the W pulse.
This circuit outputs a W start pulse synchronized with the rising edge of the LFF pulse.

The 2H phase correction circuit for the video signal having the above configuration will be described based on the operation as follows.

For example, a video signal input to a television is converted into PCM data composed of a digital signal by the A / D conversion circuit 1 and supplied to the 2H memory 2. The video signal is simultaneously input to the W start pulse generation circuit section 4 as well as the A / D conversion circuit 1. In the W start pulse circuit unit 4, the burst extraction circuit 41 generates and outputs a subcarrier signal whose frequency and phase are the same and continuous with the burst signal included in the video signal based on the input video signal. . The sync separation circuit 42 separates and outputs the sync signal (SYNC) included in the video signal. The output synchronization signal is input to the H pulse generation circuit 44, which generates and outputs a WH pulse in which only a horizontal period (H period) signal is extracted. The WH pulse and the above-described continuous subcarrier signal are input to the color frame determination circuit 43, and the color frame determination circuit 43 is input.
Performs phase comparison on a horizontal cycle basis based on these input signals, and generates and outputs a WLFF pulse whose polarity is inverted on a horizontal cycle basis. The WLFF pulse is input to the write start pulse generation circuit 45, and the write start pulse generation circuit 45 generates and outputs the W start pulse synchronized with the rising edge of the WLFF pulse.

The W start pulse is input to the memory address control generation circuit 7, and the memory address control generation circuit 7 determines the write address for every 2H period based on the W start pulse, and this address determines the A / D conversion circuit. 1
By this, it is determined to which address of the 2H memory 2 the video signal as the PCM signal is written.

The R start pulse circuit section 5 has the above-mentioned W
The circuit configuration is the same as that of the start pulse circuit unit 4, and the R start pulse is generated and output in the same procedure as the W start pulse using the reference signal as an input signal. This R start pulse is input to the memory address control generation circuit 7, a read address is determined every 2H cycle, and which address data of the video signal stored in the 2H memory 2 is determined.

The video signal 2H phase correction circuit of this embodiment outputs image data according to a reference signal transmitted from a host device equipped with this circuit. As a means for converting an input video signal having a phase shift within 2H (about 120 μS) of the video signal input to the input terminal 11 and the video signal obtained from the host device into a phase obtained by the reference signal, V- H-without using SYNC phase
This is realized by using SYNC and the burst polarity of the input video signal. Specifically, the write side control color frame determination circuit 43 of the 2H memory 2 creates a WLFF pulse from the H-SYNC phase of the input video signal and the polarity of the burst signal of the input video signal at that time.

In the NTSC standard television color signal, the polarity of the burst signal is inverted for each frame with respect to H-SYNC. Therefore, the H-SYNC phase is compared with the polarity of the input burst signal, and the result is compared. With a 1-bit signal, a WLFF pulse whose polarity is inverted every frame can be obtained. Similarly, the R start pulse circuit section 5 also obtains the RLFF pulse. By comparing these two LFF pulses, the difference between the phase on the write side and the phase on the read side is known, and it can be determined whether the phase difference is within 1H or more than 1H. By using this judgment to determine the write side address and the read side address in the memory address control generation circuit 7, it is possible to perform the phase correction in the 2H cycle.

FIGS. 2 and 3 show the above relationships as timing charts. FIG. 2 shows an input video signal 2
The case where the phase difference between 1a and the reference signal 23a is within 1H is shown. Burst signal 212a of input video signal 23a
And the burst signal 232a of the reference signal 23a are in phase, and the deviation between the reference pulses 212a and 231a of both is within 1H. Since the burst signal 212a is in the positive phase, WLFF becomes “H” by the synchronizing signal, and the W memory address is sequentially incremented from 0 and the data for the first line is 2H.
Increment to the maximum address value 909 for writing to memory. The WLFF becomes "L" when the synchronizing signal of the next line comes, and increments the address value for writing the image data of the second line to 910 to 1819. The RLFF signal also performs the same operation. 2 is different from FIG. 2 in that the burst signal 212b of the input video signal 21b and the burst signal 2 of the reference signal 23b
32b has the same phase as both sync signals 211b and 2b.
The case where the positional interval of 31b is 1 line or more is shown. In this case, the image data of the first line that has already been written is read out while the image data of the second line is being written in the 2H memory 2.

The operation of the above 2H phase correction circuit causes 2H
Phase correction of the periodic image signal is realized. Since the V-SYNC information is not used in this phase correction, the correction phase determination cycle is determined by the line cycle. Normally, in a broadcasting station, since the switching phase is immediately after V-SYNC, the correction phase is determined within the blanking, and the image is not shocked.

The above embodiment is an example of the preferred embodiment of the present invention, but the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention.

[0025]

As is apparent from the above description, the 2H phase correction circuit for a video signal according to the present invention determines the L / H state depending on the polarity of the phase of the burst signal included in the video signal, and the sync signal. Generates a line flip-flop pulse with a change timing, and this pulse controls the write operation to the 2H memory. Therefore, the polarity of the phase of the input video signal is found on the screen immediately after switching, and it is possible to know whether it is the signal of the first line or the signal of the second line, and the image data is stored in the 2H memory under normal management. It can be performed.

Further, the read signal generating circuit generates a line flip-flop pulse similar to that at the time of writing based on the input signal of the read request, and based on this pulse, the memory control unit stores the image data stored in the 2H memory. Is read line by line. Therefore, the polarity of the phase of the image signal required by the read request signal is determined by the image signal immediately after the input signal of the read request is input, and the image data is read from the 2H memory under normal management. be able to.

Further, since the read signal generating circuit has the same circuit configuration as the H pulse generating circuit and the color frame determining circuit which are the constituent circuits of the write signal generating circuit, the efficiency of designing and manufacturing can be improved. .

[Brief description of drawings]

FIG. 1 is a circuit configuration block diagram showing an embodiment of a 2H phase correction circuit for an image signal according to the present invention.

FIG. 2 is a first timing chart of the 2H phase correction circuit for image signals according to the embodiment of FIG.

FIG. 3 is a second timing chart of the 2H phase correction circuit for the image signal according to the embodiment of FIG.

[Explanation of symbols]

 1 A / D conversion circuit 2 2H memory 3 D / A conversion circuit 4 W start pulse generation circuit section 5 R start pulse generation circuit section 6 Memory read control pulse generation circuit 7 Memory address control generation circuit 11 Video signal input terminal 12 Image signal Output terminal 13 Reference signal input terminal

Claims (3)

(57) [Claims] 1. A video signal 2H phase correction circuit for correcting the phase of the image data by storing the image data of two lines of the video signal and reading the stored image data. An H pulse generation circuit for generating an H pulse based on a synchronization signal included in the video signal, and a color frame determination circuit for determining a phase polarity of a burst signal included in the video signal to generate a line flip-flop pulse. , Capable of storing at least the image data for two lines 2
An H memory and a memory control unit that controls writing and reading operations of the 2H memory are configured, and the color frame determination circuit inputs the H pulse,
The L / H of the line flip-flop pulse is inverted according to the input H pulse and the polarity of the phase of the burst signal, the line flip-flop pulse is input to the memory control unit, and the memory control unit inputs the input line. 1 for the video signal for each L / H of the flip-flop pulse
A 2H phase correction circuit for a video signal, wherein the image data of a line is stored in the 2H memory to manage the image data for each line based on the polarity of the phase of the burst signal. 2. The 2H phase correction circuit for the video signal further includes a read signal generation circuit for generating a pulse for reading the image data stored in the 2H memory,
The pulse is generated based on a read request signal input to the 2H phase correction circuit of the video signal, the pulse is input to the memory control unit, and the image data stored in the 2H memory is read line by line. Claim 1 characterized by
2H phase correction circuit for the described video signal. 3. The read request signal is a signal similar to the synchronizing signal and the burst signal, and the read signal generating circuit has the same circuit configuration as the H pulse generating circuit and the color frame determination circuit. The 2H phase correction circuit for video signals according to claim 1 or 2, further comprising a circuit.