JPS61255180A - Memory control method for video printer - Google Patents

Abstract

PURPOSE:To make small a capacity of a storage capacity memory by reading a digital signal every period of a frequency dividing signal obtained by dividing a repetition frequency of a synchronous signal separated from a video signal with a dividing ratio and by writing the digital signal of 1 horizontal scanning line of said video signal during this reading in parallel. CONSTITUTION:In a synchronizing separator circuit 5, a vertical synchronizing signal and a horizontal synchronizing signal are separated. The vertical synchronizing signal is inputted to a writing timing circuit 7 and a frequency dividing circuit 13 through a line 5a. In the frequency dividing circuit 13, a frequency dividing signal 4V obtained by dividing a repetition frequency of the vertical synchronizing signal to 1/4 is outputted. The frequency dividing signal 4V is a signal for changing over a memory space of a line memory M during writing and reading. When the frequency dividing signal 4V goes to H level, the writing is performed in the A space, and the reading is performed from the B space. When the frequency dividing signal 4V goes to L level, the reading is executed from the space A, which is opposite to the above, and the writing is executed in the space B.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention relates to a memory control method for a video printer that prints an image based on a video signal on paper, and particularly to a control method that can reduce the memory capacity. It is.

(Prior Art) In recent years, video printers have been proposed that print one frame of an image displayed on a CRT using a video signal from a TV receiver, VTR, etc. and output it as a hard copy.

FIG. 6 shows an example of such a conventional video printer.
In the figure, 1 is a video signal input terminal, 2 is a video amplifier, and 3 is an analog-to-digital conversion circuit (hereinafter referred to as A).
4 is a field memory for storing the video signal converted into a digital signal, 5 is a synchronization separation circuit for separating the horizontal synchronization signal and vertical synchronization signal from the video signal, and 6 is a control circuit. The circuit 7 is a write timing circuit, and the write timing circuit 7 includes an oscillator for generating an address step pulse for generating the write address signal described above. 8 is a bus buffer, 9 is an address switching circuit, 10 is a print head, and 11 is a recording paper feeding motor.

Traditional video printers are configured like this.
The field memory 4 is controlled as follows, and the image is printed on the recording paper by the print head 10. To explain this using FIG. 7, first, the video signal applied to the input terminal 1 (FIG. 7(a)) is voltage amplified by the video amplifier 2 to the required amplitude value, and then the A/D conversion circuit 3 and The signal is input to the synchronization separation circuit 5. In the A/D conversion circuit 3, one horizontal scanning line of the video signal is divided into 256 sections, and for each section, a digital signal for writing (7th
(C)). On the other hand, the vertical synchronization signal and horizontal synchronization signal separated by the synchronization separation circuit 5 are sent to the control circuit 6 and the write timing circuit 7, respectively.

Then, the digital signal to the field memory 4 (Fig. 7 (
When writing C)), switching signals are sent from the control circuit 6 to the bus buffer 8 and the address switching circuit 9 through the switching signal line 6a, and the control circuit 6 is disconnected from the data line 3a and switched to the A/D conversion circuit. 3 output terminal is data line 3
The address switching circuit 9 is switched to the write address signal line 7a from the write timing circuit 7. Driven by the horizontal synchronization signal, the write timing circuit 7 generates a write address (Fig. 7 (d)), which is sent to the field memory 4, and is converted into a digital signal (Fig. 7 (C)) by this write address. One field (one screen) of the converted video signal is stored in the field memory 4.

In this one field, one horizontal scanning line is divided into 256 sections, and this is stored over a vertical section of 256 horizontal scanning lines, so the total is 256 x 256-65.
This corresponds to the amount of information for 536 picture elements.

After the information for one field of the video signal is stored in the -H field memory 4 in this way, the stored video signal information is then read out toward the print head. The reason why the storage control and readout control are performed alternately in this way is because the printing speed is slow when comparing the input speed of the video signal to the input terminal 1 and the printing speed on the recording paper by the print head 10. This is because input and output cannot be synchronized.

When reading video signal information, the bus buffer 8 is opened by a switching signal output from the control circuit 6, the data line 3a from the field memory 4 is connected to the control circuit 6 side, and the address switching circuit 9 is connected to the control circuit. 6 to the read address signal line 6b side. The digital video signal stored in the field memory 4 is then read out according to the address from the control circuit 6 and sent to the print head 10 via the bus buffer 78 and the control circuit 6. Then, the pulse application time to the heating element in the print head 1G is varied according to the level of the video signal, and the recording paper is intermittently fed by the motor 11, so that one black and white gray image is printed on the recording paper. printed.

(Problems to be Solved by the Invention) In such a conventional video printer memory control method, approximately 65,500 memory cells corresponding to one field are stored by writing.
The signal information for each picture element was stored in the field memory, and then this stored signal information was read out and printed on recording paper, so the field memory required a fairly large storage capacity, resulting in high costs. There was a problem with sticking.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory control method for a video printer which is designed to solve the problems of the conventional memory control method for a video printer described above, and which can use a memory with a small storage capacity. .

(Means for Solving the Problems) In order to achieve the above object, a memory control method for a video printer according to the present invention converts a video signal into a digital signal, writes and stores this digital signal in a memory,
In a memory control method for a video printer that reads out the stored digital signal and sends it to a print head to print on recording paper, a frequency-divided signal is obtained by dividing the repetition frequency of a synchronization signal separated from the video signal by a predetermined frequency division ratio. The reading of the digital signal is executed every period of , and during the reading, writing of the digital signal for one horizontal scanning line of the video signal is executed in parallel, and the digital signal to be read is , 1 of the read execution
This is a digital signal written and stored in the previous cycle.

(Function) A digital signal is read out every cycle of a frequency-divided signal obtained by dividing the repetition frequency of a synchronizing signal separated from a video signal by a predetermined frequency division ratio. The writing of digital signals for scanning lines is executed in parallel, and the digital signal to be read out is the digital signal written and stored in the cycle immediately before the reading execution, so it is stored in the line memory. The digital signal is required for one horizontal scanning line of the video signal, and the required storage capacity of the memory is greatly reduced.

Furthermore, even if the input speed of the video signal is high and the printing speed on the recording paper is low, the readout time can be long, and writing and reading can be executed smoothly in parallel.

(Example) Embodiments of the present invention will be described below based on the drawings.

First, a video printer to which this invention is applied will be explained with reference to FIG. In FIG. 1, the same or equivalent components as those in FIG. 6 are denoted by the same reference numerals and redundant explanations will be omitted.

The video printer to which this invention is applied differs from the conventional one shown in FIG. 6 in that a line memory M is provided in place of the field memory 4. The line memory M stores a digital signal corresponding to one horizontal scanning line of a video signal, and has a smaller capacity than the field memory 4. The memory space in this line memory M consists of two spaces, A space and B space, as shown in FIG. 4, which will be described later.
(256 picture elements x 2), and the rain spaces are made so that they do not interfere with each other. A decoder 12 is installed between the line memory M and the A/D conversion circuit 3.
is connected. Further, a frequency dividing circuit 13 that divides the repetition frequency of this vertical synchronizing signal by 1/4 is connected to the output line 5a of the vertical synchronizing signal derived from the synchronizing separation circuit 5, and the output line of this frequency dividing circuit 13 is One is directly connected to one contact of the switch 14a in the switching circuit 14, and the other is connected to the other contact a of the inverter 15.
connected via.

Next, an embodiment of the memory control method according to the present invention will be described with reference to FIGS. 2 to 5.

The input video signal is amplified by a video amplifier 2 and then input to an A/D conversion circuit 3 and a sync separation circuit 5. The signal is then converted into a 3-bit digital signal by the A/D conversion circuit 3, and further converted into an 8-bit digital signal (data) by the decoder 12. Further, the synchronization separation circuit 5 separates a vertical synchronization signal and a horizontal synchronization signal, of which the vertical synchronization signal is inputted to the write timing circuit 7 and the frequency division circuit 13 through a line 5a. Based on this vertical synchronization signal, the write timing circuit 7 generates a write timing pulse V (FIG. 5(a)) having the same period as this signal.
)) is output, and the frequency dividing circuit 13 outputs a frequency-divided signal 4V (FIG. 5(b)) obtained by dividing the repetition frequency of this vertical synchronizing signal by 174.

As will be described later, the frequency division signal 4v is a signal for switching the memory space of the line memory M at the time of writing and reading.When this frequency division signal 4v is at H level, writing is executed in the A space, and writing is executed from the B space. Reading is executed. On the other hand, when the frequency division signal 4■ is at the "Yes" level, reading is executed from the A space and writing is executed to the B space (the fifth
figure). The switching operations of data line 12a and switching circuit 14 during writing and reading are controlled by an E (enable) clock output from control circuit 6.

When the E clock is at L level, the control circuit 6 is disconnected from the data line 12a, the output terminal of the decoder 12 is connected to the line memory M via the data line 12a, and the switching circuit 14 is connected to the write address signal. Line 7a is connected to line memory M and is switched to (FIG. 2). Thus, according to the write address from the write timing circuit 7, data from the decoder 12 is written and stored in the memory portion corresponding to the write address. 256 write addresses are sent out in a 1v section @ (FIG. 5(a)) (the next 1v section is stopped), and data for one line is written into the line memory as a 256-byte digital signal.

On the other hand, when ER0 is at H level, bus buffer F8
is opened, the data line 12a from the line memory M is connected to the control circuit 6 side, and the switching circuit 14 is switched to the address bus 6b side of the control circuit 6 (FIG. 3). The data stored in the line memory M is then read out according to the read address from the control circuit 6 and sent to the print head 10 via the control circuit 6.

Writing and reading data to and from the line memory M are executed in parallel as shown in FIG. 5 while being switched by the E clock. Since the printing speed by the print head 10 is slow, the readout time is performed during half the cycle of the divided signal 4V, and since the input speed of the video signal is fast, the writing time is 1V, which is 1/2 of the readout execution cycle. held during the period. Then, the writing and reading operations for the A space and the B space are alternately switched by the switching operation of the switching circuit 14 every half cycle of the frequency divided signal 4■, and the data to be read is
The data is written and stored in the cycle immediately before the read execution, and is controlled so that parallel write and read operations are performed smoothly (FIG. 5).

(Effects of the Invention) As detailed above, according to the present invention, a digital signal is read out every cycle of a frequency-divided signal obtained by dividing the repetition frequency of a synchronizing signal separated from a video signal by a predetermined frequency division ratio. and one of the video signals during this read execution period.
The writing of digital signals for horizontal scanning lines is executed in parallel, and the digital signal to be read out is the digital signal written and stored in the cycle immediately before the reading execution, so it is stored in the memory. Since the amount of digital signal is sufficient for one horizontal scanning line of the video signal, the required storage capacity of the memory is greatly reduced, and the cost of the video printer can be reduced. Further, even if the input speed of the video signal is high and the printing speed on the recording paper is low, the reading time can be long, so writing and reading can be smoothly executed in parallel.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an example of a video printer applied to the present invention, and FIGS. 2 to 4 are diagrams for explaining an embodiment of a memory control method for a video printer according to the present invention.
Fig. 2 is a system diagram showing the switching state of data lines, etc. for the line memory during writing, and Fig. 3! II is a system diagram showing switching states of data lines, etc. for the line memory during read execution, FIG. 4 is a diagram showing the memory space in the line memory, FIG. 5 is a timing chart showing frequency division signals, etc., and FIG. 7 is a system diagram showing a conventional video printer, and FIG. 7 is a timing chart showing video signals and the like. 3: A/D conversion circuit, 5: Synchronization separation circuit, 6: Control circuit 7: Write timing circuit, 8: Bus buffer 7. 10 Ni print head, 13: Frequency divider circuit, 14: Switching circuit, M Ni line memory. 211th 4th II I5II

Claims (1)

[Claims] A memory control method for a video printer that converts a video signal into a digital signal, writes and stores this digital signal in a memory, and reads out the stored digital signal and sends it to a print head to print on recording paper. , The digital signal is read out every period of a frequency-divided signal obtained by dividing the repetition frequency of the synchronizing signal separated from the video signal by a predetermined frequency division ratio, and during this readout, one of the video signals is read out. A video printer characterized in that writing of digital signals for horizontal scanning lines is executed in parallel, and the digital signals to be read out are digital signals written and stored in a cycle immediately before the readout execution. Memory control method.