JP3218375B2 - Superimpose circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superimpose circuit, and more particularly to a character display device or a video device for processing a television video signal such as a television, VTR, video camera, etc. The present invention relates to an improvement of a superimposing circuit for superimposing a video signal such as a video signal on a television signal.

[0002]

2. Description of the Related Art There are several international standards for the structure of a television video signal such as the NTSC and PAL systems. For example, it is common that a video signal such as a chroma signal is included. By processing the television video signal as it is or by performing processing such as modulation, for example, a video reproduced from a broadcast wave by a television receiver is displayed, or a captured image is recorded on a video tape. Video signal processing is performed.

[0003] Further, in a current video device, a video image represented by a television video signal is not displayed as it is.
rare. A video signal such as a channel number, time, or a title image in a video camera is superimposed on a television video signal and then displayed or recorded. FIG. 3 shows a block diagram of a superimpose circuit for superimposing a character on a television video signal as an example of a conventional circuit for performing such processing. Here, 1 and 2 are counter circuits, 3 is a memory access circuit, 4 is an SRAM, 5 is a character generator (cage generator), 6 is a shift register circuit (shift circuit), 7 is a CRT, and 8 is an oscillation circuit.

The oscillation circuit 8 has a NAND gate in an oscillation loop, and receives a feedback of an oscillation signal as one input of the NAND gate to generate a dot clock DCLK as an oscillation signal. Further, as another input of the NAND gate, a horizontal synchronization signal HSYNC separated from a television video signal (not shown) is received. As a result, the dot clock DCLK becomes the horizontal synchronizing signal HSYN.
Oscillation stops while C is significant ("L" in the figure), and oscillation starts in synchronization with the end of the horizontal synchronization signal HSYNC.

The counter circuit 1 is a circuit mainly composed of a counter, and also receives a vertical synchronizing signal VSYNC separated from a television video signal, resets its count value, receives a horizontal synchronizing signal HSYNC, and resets its count value. Is incremented. The count value is used as a vertical address indicating a vertical scanning position for display and the like. The counter circuit 2 is also a circuit mainly composed of a counter, receives a horizontal synchronization signal HSYNC, resets its count value, and outputs a dot clock DC.
Upon receiving LK, the count value is incremented.
Then, the dot clock DCLK is the horizontal synchronization signal HSY.
Since the count value is synchronized with the NC, the count value is used as a horizontal address for indicating a horizontal scanning position.

The memory access circuit 3 generates a memory address signal A from a vertical address signal and a horizontal address signal, for example, by setting them as upper bits and lower bits, respectively. Further, based on the dot clock DCLK, for example, by dividing the frequency, a memory control signal T is also generated. Then, the character data of the SRAM 4 stored at the address indicated by the memory address signal A is read in accordance with the timing indicated by the memory control signal T.

The writing to the SRAM 4 is performed by the CPU.
(Not shown) and according to the data signal C
This is performed by the memory access circuit 3 outputting the memory address signal A, the data signal D, and the memory control signal T.
This write timing is performed by the memory access circuit in synchronization with a dot clock or the like. Alternatively, it is delayed by the memory access circuit 3 until that timing.
In this way, the readout timing is prioritized, and the screen display is prevented from being disturbed.

The character generator 5 includes an SRAM 4
From the matrix-like character patterns corresponding to the character data read out from the memory device, a pattern for one line indicated by a vertical address signal or the like is selected and output. The pattern for one line in the character pattern is latched by the shift register circuit 6 and is shifted by one bit at a time in accordance with the timing of the dot clock DCLK to be converted from parallel to serial to become a superimpose signal B.

[0009] On the other hand, although not shown in the figure, the horizontal synchronizing signal and the like are removed from the television video signal, and only the portion related to the video information is extracted as the video signal E. Then, the superimposing signal B is synthesized with the video signal E to generate a synthesized video signal F. A superimposed image of a character such as a channel number or time is displayed on the CRT 7 by scanning according to the composite image signal.

[0010]

In such a conventional superimposing circuit, a memory control signal and the like are generated based on a dot clock, and the suspension of the dot clock is asynchronously performed by an external horizontal synchronizing signal. Done. For this reason, depending on the timing of the horizontal synchronizing signal, access to the memory may be interrupted in the middle of a memory cycle. Therefore, a general-purpose memory having a function of detecting a change state of an address signal and suppressing access to a memory cell in an unstable state, that is, an asynchronous memory is used.

However, in such a general-purpose memory, a high speed enough to cover a waiting time in a stable state is required for a memory cell. In particular, for consumer use, cost constraints are severe, and it is urgent to reduce the cost of the memory portion, which accounts for the majority of the cost of the entire superimposed circuit. The memory cell is of a static type, but the circuit scale is large. An address decoder of a dynamic type is used.

A horizontal synchronization signal received from another circuit is a signal separated from a reception signal of a broadcast wave, a signal reproduced from magnetic recording, or the like. For this reason,
Noise is often superimposed on this signal. Especially when beard-like noise, so-called glitches, are superimposed,
One pulse turns into multiple pulses. This noise reaches the memory control signal via the dot clock. Then, the noise causes a malfunction of the memory, which is a problem. SUMMARY OF THE INVENTION An object of the present invention is to solve such a problem of the prior art, and to realize a superimpose circuit which can use a memory having a simpler function and is excellent in noise resistance. It is.

[0013]

In order to achieve the above object, a superimpose circuit according to the present invention is arranged such that a video signal based on data stored in a memory is converted into a television video signal or a partial video signal thereof. An oscillation circuit for generating a dot clock synchronized with the oscillation stop signal by stopping oscillation in response to the oscillation stop signal and starting oscillation upon release of the oscillation stop signal; A memory access circuit for generating a memory clock having a period corresponding to a memory cycle for reading the data from the dot clock based on the dot clock; and a memory clock for transmitting a horizontal synchronization signal included in or contained in the television video signal. The start timing of the horizontal synchronization signal is A synchronization signal generation circuit that generates a pulse signal delayed until a timing synchronized with the memory cycle, wherein the pulse signal is sent from the synchronization signal generation circuit to the oscillation circuit as the oscillation stop signal. is there.

[0014]

In the superimpose circuit of the present invention having such a configuration, the stop of the dot clock is not performed asynchronously by the start end of the horizontal synchronization signal, but by the oscillation stop signal, that is, the pulse synchronized with the memory cycle. This is done by a signal. Therefore, the timing of stopping the dot clock is synchronized with the memory cycle. The start of the dot clock is originally synchronized with the end of the horizontal synchronization signal, and the memory cycle starts based on the dot clock.

Therefore, a memory control signal is always output in a stable and repetitive state without occurrence of an incomplete memory cycle. Therefore, since the timing of stabilizing the address signal and the like is clearly determined in advance, a detection circuit and a circuit for generating a signal for suppressing access are not required on the memory side. Therefore, a memory that can operate only in a definite memory cycle, that is, a synchronous memory can be adopted. This synchronous memory has fewer additional circuits and a smaller circuit size than a general-purpose asynchronous memory, and does not require a waiting time. That is, a memory having low versatility and a simple function can be used.

Also, even if noise such as glitches is superimposed on the horizontal synchronizing signal, if it is in the middle of a memory cycle, it is ignored since it is not latched and has no effect on the operation of the memory. Furthermore, if it is at the timing of a memory cycle switch, the value affected by noise is latched, but the effect is that the next memory cycle is simply delayed, and there is a possibility of loss of stored data. No failures occur. At most, a temporary display disturbance due to a delay in the read timing is sufficient. Therefore, the superimpose circuit of the present invention is a circuit that can use a memory having a simple function and is resistant to noise.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a superimpose circuit having the configuration of the present invention will be described below with reference to the block diagram of FIG. This circuit is an example of a circuit for superimposing a character on a television video signal. Here, reference numerals 1 and 2 denote counter circuits, 5 denotes a character generator (cage generator), 6 denotes a shift register circuit (shift circuit), 7 denotes a CRT, and 8 denotes an oscillation circuit. Since these have the same configuration as the conventional example, they are denoted by the same reference numerals as the conventional example, and the description thereof will not be repeated. Reference numeral 30 denotes a memory access circuit, reference numeral 40 denotes a DDRAM, and reference numeral 90 denotes a synchronization signal generation circuit.

The memory access circuit 30 outputs a memory address signal A, a data signal D, and a memory control signal T based on the dot clock DCLK in the same manner as in the prior art. Further, by dividing the dot clock DCLK by three, for example, the memory clock M corresponding to the memory cycle is obtained.
CLK. In the present embodiment, this clock is newly generated. However, when a signal of the corresponding timing is present in the memory control signal T, the clock is used as the memory clock MCLK to reduce the circuit scale. A significant increase can be prevented.

The DDRAM 40 has a Display-Da
Although it is an abbreviation for ta-RAM, it is a synchronous memory whose operation is guaranteed only in a definite memory cycle. This DDRAM is not provided with an additional circuit for detecting a change state or the like of an address signal or suppressing an access signal to a memory cell until the change state stops. In addition, the cycle time of the DDRAM 40 is simply shorter than the cycle of the memory clock, and the operation speed of the memory cell is lower than that of the asynchronous memory including the waiting time within the same cycle. Therefore, memory is a simple function,
The configuration is sufficient. Furthermore, when not only the memory alone but also the superimpose circuit including the memory is integrated into an IC, the productivity is improved. As a result, cost can be reduced.

The synchronizing signal generating circuit 90 mainly includes a D-type flip-flop, and outputs a horizontal synchronizing signal HSY.
NC is latched at the timing of the memory clock MCLK to generate a synchronization signal HM. Furthermore, in this embodiment, the synchronization signal HM is generated by delaying the synchronization signal HM by one memory cycle. Then, at the timing of the synchronization signal HM, the output of the signals A, D, T, etc. is stopped, and the DD
Access to the RAM 40 stops. Further, at the timing of the synchronization signal HI, the dot clock DCLK stops, and the counter circuit 2 that outputs the horizontal address is reset.

As described above, by selectively using the two synchronization signals HM and HI synchronized with the memory clock MCLK,
Slight skew of signal timing due to variation in propagation delay time, so-called skew eliminates the effect,
More reliable operation can be expected. In addition, since the horizontal synchronizing signal is temporarily latched by the memory clock MCLK, M
The memory cycle is not interrupted by noise superimposed on the horizontal synchronizing signal shorter than the cycle of CLK. Therefore, noise resistance is also improved.

Further, since the synchronizing signal HI is generated by the logical sum of the latched signal and the horizontal synchronizing signal HSYNC, when the pulse of the horizontal synchronizing signal HSYNC ends, the synchronizing signal HI also ends. The dot clock DCLK is output again. Then, a memory clock MCLK is generated based on the dot clock DCLK, and a new memory cycle is repeated. As described above, since the memory cycle starts in synchronization with the horizontal synchronization signal HSYNC, the display position on the scanning line does not shift. Moreover, the memory cycle started in synchronization with the previous horizontal synchronization signal is not interrupted asynchronously on the way by the subsequent horizontal synchronization signal (see the waveform diagram in FIG. 2). Therefore, it is possible to use DDRAM which is a synchronous memory having a simple function.

In this way, the character data is read from the DDRAM 40, and the pattern for one line in the character pattern corresponding to the character data is converted from a parallel-serial signal to a superimpose signal B. Then, the superimposing signal B is synthesized with the other video signal E, and a superimposed video such as a channel number is displayed on the screen of the CRT 7. Although the present embodiment relates to character display, for example, in the case of title display, it has substantially the same configuration except that the character generator 5 is not provided. The recording circuit such as a VTR or a video camera has substantially the same configuration except that the carrier frequency of the video signal and the circuit after the composite video signal F are different.

[0024]

As can be understood from the above description, in the superimpose circuit having the configuration of the present invention, the start timing of the horizontal synchronizing signal stops the dot clock in accordance with the synchronizing signal corresponding to the memory cycle. . As a result, a memory having a simple function can be used, and the memory is less likely to be affected by superimposed noise. As a result, there is an effect that the performance can be improved while reducing the cost.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of a superimpose circuit having the configuration of the present invention.

FIG. 2 is a waveform chart for explaining the operation.

FIG. 3 is a block diagram of a conventional superimpose circuit.

[Explanation of symbols]

 1, 2 counter circuit 3 memory access circuit 4 SRAM 5 character generator (cagen) 6 shift register circuit (shift circuit) 7 CRT 8 oscillation circuit 30 memory access circuit 40 DDRAM 90 synchronization signal generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/278 H04N 5/445 G09G 5/00-5/22

Claims (1)

(57) [Claims] 1. A superimpose circuit in which a video signal based on data stored in a memory is combined with a television video signal or a partial video signal thereof, wherein the oscillation is stopped in response to an oscillation stop signal and the oscillation stops. An oscillation circuit that generates a dot clock synchronized with the oscillation stop signal by starting oscillation when the signal is released, and a memory clock having a cycle corresponding to a memory cycle for reading the data from the memory based on the dot clock And a horizontal access signal included in or contained in the television video signal is latched at the timing of the memory clock so that the start timing of the horizontal access signal is set in the memory cycle. Synchronous signal generation that generates a pulse signal delayed until synchronized And a raw circuit, wherein the pulse signal is sent from the synchronization signal generation circuit to the oscillation circuit as the oscillation stop signal.