JPH05308544A - Video signal processor - Google Patents

Abstract

PURPOSE:To prevent the generation of a skew at the time of passing ahead/ being passed behind between a writing-in and a reading-out addresses the video signal processor to synchronize two independent video signals using a field memory. CONSTITUTION:The first video signal from an input terminal 8 is written in a field memory 1 at a timing generated at a timing generator 2 and a write address counter 3, and data is read from the field memory 1 by the timing generator 2, a read address counter 4, and a read address adder 5 at the timing generated with the second video signal from an input terminal 9 as a reference. Passing ahead/being passed behind between the writing-in address and the reading-out address is detected by a passing detector 7, the read address is controlled by the read address adder 5 based on the output of an address difference increase/decrease detector 6 to detect the increase/decrease of the address difference, and the timing of horizontal synchronizing signals is made fixed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus for synchronizing video signals of video equipment such as televisions and VTRs.

[0002]

2. Description of the Related Art A conventional video signal processing apparatus for synchronizing two independent video signals using a field memory will be described. FIG. 4 is a block diagram showing the configuration of a conventional video signal processing device that synchronizes two video signals by using a field memory that performs writing and reading asynchronously. The first video signal is input to the input terminal 26, and the write address counter 23 and the timing generator 25 are input.
Thus, it is written in the field memory 22 at a timing based on the first video signal. Further, the written signal is read from the field memory 22 by the read address counter 24 and the timing generator 25 at the timing based on the second video signal.

[0003]

However, since the write and read operations are performed asynchronously in the device having the above-mentioned configuration, the write address and the read address are overtaken, and the field of the video signal read at that moment is preceded. Alternatively, there is a problem that a skew occurs on the screen because the field changes to the next field.

This problem will be described with an example. FIG. 5 shows the horizontal synchronizing signal of the memory output when overtaking occurs. During normal writing and reading operations, the horizontal driving period signal is generated in units of 1H (H: horizontal scanning period). The drawing at this time is shown in FIG. As shown in FIG. 5, if the even field is read before the overtaking occurs, the previous (or next) field is read from the place where the overtaking occurs, so that the horizontal field signal is shifted by 0.5H as an odd field. As a result, the horizontal synchronizing signal becomes discontinuous as shown in FIG. 5, and a skew occurs on the screen as shown in FIG. 6B, which makes the screen unsightly.

In order to solve this problem, there is a method of using two or more sets of the video signal processing device of FIG. 4 and switching their outputs before overtaking occurs, but the memory capacity is required to be twice or more, There was a problem that the cost would go up.

The present invention eliminates the above problems, and provides a video signal processing device which can obtain a video signal in which skew does not occur even when overwriting of write and read addresses occurs and which can be realized at low cost. To aim.

[0007]

In order to achieve this object, the video signal processing device of the present invention writes a video signal in synchronization with a first video signal and reads it out in synchronization with a second video signal. And a write address counter for generating a write address for the field memory, a read address counter for generating an address serving as a reference of a read address given to the field memory, and a timing signal from the first and second video signals. The output of the write and read address counters and the timing generator that outputs to the field memory, write and read address counters, and the outpacing detector that compares the values of the write and read addresses given to the field memory and detects address overtaking Compare the values, increase the address difference, A read address adder that detects a small difference, and a read address adder that increases / decreases the output value of the read address counter according to the output of the overtaking detector and the address difference increase / decrease detector, and gives the output value to the field memory as a read address. It has and.

[0008]

According to the present invention, the read timing is set to 0.5H or (2n-1) * 0.5H (n: 1, when the write and read addresses are overtaken.
2, 3, ...) By shifting the timing, the timings of the horizontal synchronizing signals can be aligned at 1H intervals, skew can be prevented, and the cost can be reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a video signal processing apparatus according to an embodiment of the present invention. This video signal processing device is intended to synchronize the vertical synchronization of two video signals at regular intervals.

In FIG. 1, the first video signal is input terminal 8
It is input to the field memory 1 and the timing generator 2 from Further, the second video signal is input to the timing generator 2 from the input terminal 9.

The timing generator 2 outputs a timing signal for writing from the first video signal to the field memory 1 and the write address counter 3, and a second video signal from the second video signal to the field memory 1 and the read address counter 4. A timing signal for reading is generated.

The address difference increase / decrease detector 6 monitors and increases the difference between the output value of the write address counter 3 and the output value of the read address counter 4 (output value of write address counter 3-output value of read address counter 4). "H" is output when the output is being performed, and "L" is output when the output is being reduced.

The overtaking detector 7 compares the output value of the write address counter 3 with the output value of the read address adder 5, outputs "H" when overtaking occurs, and the output of the read address adder 5 is reset. Hold until After that, "L" is output.

The read address adder 5 is an overtaking detector 7
And a predetermined value is added to the output of the read address counter 4 according to the state of the address difference increase / decrease detector 6.

The basic operation of the read address adder 5 when the read address overtakes the write address will be described with reference to FIG. FIG. 2 shows the horizontal synchronizing signal of the memory output. When the read address overtakes the write address, the address difference decreases. When an overtaking occurs at time A in FIG. 2A, the read timing is set to 0.5H in the direction in which the address difference decreases.
In order to shift it, the value of 0.5H is added to the output value of the read address counter 4 to obtain the read address. That is, as shown in FIG. 2B, at the moment of passing, reading is started from the data at the point B 0.5 H after the point A in FIG. 2A. As a result, the horizontal synchronization is aligned at 1H intervals, and no skew occurs on the screen. If overtaking occurs again, 0.5H is added. In this way, 0.5H may be added each time overtaking occurs, but it is not preferable because the synchronization relationship of the vertical synchronization of the first and second video signals shifts by 0.5H each time 0.5H is added. Therefore, it is necessary to subtract the added read address. In this case, in order to prevent skew when the read address is subtracted, it is necessary to subtract in 1H units.

When the write address exceeds the read address, contrary to the case where the read address exceeds the write address, 0.5H is subtracted when the overtake occurs,
In order to maintain the synchronization relationship of vertical synchronization, it is sufficient to add in 1H units.

FIG. 3 shows a specific example of the read address adder 5 which satisfies the above basic operation. In FIG. 3, the output of the read address counter 4 is input from the input terminal 18 to the adder 12
Entered in. The outputs of the address difference increase / decrease detector 6 and the overtaking detector 7 are input to the up / down counter 17 through input terminals 19 and 20, respectively.

The up / down counter 17 is "1",
It has three values of "2" and "3", and when the address difference increase / decrease detector 6 is "H", that is, when the address difference is increasing, it serves as a down counter. Further, the address difference increase / decrease detector 6
Is "L", that is, when the address difference is decreasing, the counter is an up counter. Then, each time the overtaking detector 7 becomes "H", it counts up or down.

13, 14, and 15 are 0H and 0.5, respectively.
H, 1H count value, changeover switch 1
6 is input.

The changeover switch 16 selects and outputs the terminal A when the output value of the up / down counter 17 is "1", the terminal B when the output value is "2", and the terminal C when the output value is "3".

The adder 12 adds the input value from the input terminal 18 and the output value of the changeover switch 16. Adder 1
The output of 2 is output from the output terminal 21 to the field memory 1 and the overtaking detector 7.

When the read address overtakes the write address, the output of the address difference increase / decrease detector 6 is "L", and the output value of the up / down counter 17 increases every time the overtaking detector 7 becomes "H". .. Changeover switch 1
When 6 is the terminal A, the value of the read address counter is directly output to the output terminal 21. At this time, when an overtaking occurs and the overtaking detector 7 becomes “H”, the changeover switch 16
Is connected to the terminal B, and a value obtained by adding 0.5H to the output value of the read address counter 4 is output. When overtaking occurs thereafter, the changeover switch 16 is connected to the terminal C,
The value added with 0.5H is output. When overtaking occurs thereafter, the changeover switch returns to the terminal A, and the value obtained by subtracting 1H is output.

When the write address overtakes the read address, conversely, 0.5H is subtracted every time overtaking occurs → 0.
Repeat 5H subtraction → 1H addition.

The specific example of the read address adder 5 can be modified in various ways based on the basic operation, and these modifications are not excluded from the scope of the present invention.

[0026]

As described above, according to the present invention, the passing of the write address and the read address is detected, and the read timing is shifted by 0.5H or 1H, so that the intervals of the horizontal synchronizing signals are aligned and the skew is generated. A video signal that does not occur can be obtained. As a result, a high-quality video signal can be obtained with a small memory, so that the hardware can be constructed at a low cost and its practical effect is extremely large.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a video signal processing device showing an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a horizontal synchronization signal output from a field memory during overtaking in the same embodiment.

FIG. 3 is a schematic configuration diagram showing a specific example of a read address adder in the same embodiment.

FIG. 4 is a schematic configuration diagram of a video signal processing device using a conventional field memory.

FIG. 5 is a schematic diagram showing a horizontal sync signal of a field memory output and an even / odd field when overtaking in a conventional example.

FIG. 6 is a schematic diagram showing a screen when overtaking in a conventional example.

[Explanation of symbols]

 1 field memory 2 timing generator 3 write address counter 4 read address counter 5 read address adder 6 address difference increase / decrease detector 7 overtaking detector 8 input terminal 9 input terminal 10 output terminal 11 output terminal

Claims (1)

[Claims] 1. A field memory for writing a video signal in synchronism with a first video signal and reading for a video signal in synchronism with a second video signal, and a write address counter for generating a write address for the field memory. A read address counter for generating an address serving as a reference of a read address given to the field memory, and a timing signal generated from the first and second video signals,
A timing generator that outputs to the field memory, the write and read address counters, an overtaking detector that compares the values of write and read addresses given to the field memory, and detects an address overtaking, and the write and read address counters. Comparing the output value of, the address difference increase / decrease detector for detecting the increase / decrease of the address difference, the output value of the read address counter is increased / decreased according to the output of the overtaking detector and the address difference increase / decrease detector, A video signal processing device comprising: a read address adder for providing the output value to the field memory as a read address.