JPH04356876A - Synchronizer - Google Patents

Abstract

PURPOSE:To prevent scan lines from being inverted by difference between respective odd-numbered and even-numbered fields by using one field memory. CONSTITUTION:A one-field memory 1 is provided to store video signals for one field, and a reset signal generation part 2 is provided to control write and read. The reset signal generation part 2 is equipped with a V separation circuit 21, V latch circuit 22 to output the transformation field pulse of a duty ratio 263:262, AND circuit 23 to output a mask signal by calculating a logical condition for getting '1' in the case of the odd-numbered frame and getting '0' in the case of the even-numbered frame, 262 counter 24, OR circuit 25 to output a write reset signal, write edge detection circuit 26 and read edge detection circuit 27. Thus, since the reset signal generating means adjusts the write timing of a write synchronizing signal based on a read synchronizing signal and outputs a write reset signal and input video signals are written in the one-field memory at write timing specified by this write reset signal, the scan line is prevented from being inverted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizer that outputs a synchronizing signal in a video signal input to a one-field memory by matching it with a reference synchronizing signal.

0002

2. Description of the Related Art Conventionally, this type of synchronizer has two field memory systems in which an input video signal is sequentially stored two fields (one frame) at a time and outputted, and one in which a video signal is sequentially stored and outputted one field at a time. There is a field memory method. The one-field memory type synchronizer has a problem in that a predetermined field of the input video signal is truncated or repeatedly read out due to the accumulation of synchronization deviations between the input and output. side), if the odd and even numbers of the fields do not match, the one that newly becomes the odd field when reading the 1 field memory is 1H.
By delaying (horizontal scanning period), reversal of scanning lines occurring between the input video signal and the output display video signal is adjusted. When reversal occurs, the vertical relationship between the even field scanning line and the odd field scanning line of the input video signal is reversed and the continuity of the original image is disrupted, which is very inconvenient. This is an odd number (52
This is due to the NTSC system, in which one frame consisting of five (5) lines is displayed in two fields by interlaced scanning.

FIG. 5 shows a schematic diagram of a conventional synchronizer using a one-field memory. In the figure, the conventional synchronizer writes the input video signal So to the one-field memory 1 based on the write reset signal RSTw and the system clock 4fsc1, which has a frequency four times that of the color subcarrier on the input side, and the written video Read the signal Based on the reset signal RSTR and the system clock 4fsc2 on the output side, display the display video signal Sv
The configuration is such that it is outputted via the odd/even determination circuit 3.

[0004] Here, the odd/even determination circuit 3 detects the odd/even field state in the input video signal So, and determines whether the odd/even fields on the input side and the output side (display side) do not match. If so, adjustments such as outputting through a field 1H delay circuit are made based on this detection result.

[0005]

Since the conventional synchronizer is constructed as described above, the two-field memory type synchronizer has a huge memory capacity and the device itself becomes expensive. In addition, in the case of a one-field memory type synchronizer, it is necessary to detect whether the fields are odd or even in the input video signal, which complicates the device itself. There was a problem in that an odd/even judgment circuit had to be provided separately to judge whether the field matched or did not match an even field.

The present invention has been made to solve the above problem, and is capable of preventing reversal of scanning lines caused by differences in odd and even numbers of each field in each input and output video signal with a simple configuration. The purpose is to propose a synchronizer that can.

[0007]

[Means for Solving the Problems] FIG. 1 shows a diagram illustrating the principle of the present invention. In the figure, the synchronizer according to the present invention writes an input video signal to a one-field memory (1) that stores only one field of a video signal based on a write synchronization signal, and outputs an input video signal asynchronously to the write synchronization signal. The video signal of the one field memory (1) is read based on a read synchronization signal including a signal indicating the starting point of each field in the video signal, and the odd and even numbers of fields in the input video signal and the read output video signal are read out. A synchronizer that adjusts reversal of scanning lines based on differences, comprising a reset signal generating means (2) that adjusts the write timing of a write synchronization signal based on the read synchronization signal and outputs a write reset signal, and The input video signal is written into the 1-field memory (1) at the write timing specified by .

[0008]

[Operation] In the present invention, the reset signal generating means adjusts the write timing of the write synchronization signal based on the read synchronization signal and outputs the write reset signal, and the input video signal is output at the write timing specified by the write reset signal. By writing the video signal into the 1-field memory, the video signal is written in a format that matches the field to be read, not when reading the video signal from the 1-field memory, and the scanning line on the input and output sides is Reverse rotation is prevented by a simple device configuration.

[0009]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 2 and 3. FIG. 2 is a detailed block diagram of main parts of the synchronizer according to the present embodiment, and FIG. 3 is an operation timing chart of the present embodiment. In each of the figures, the synchronizer according to this embodiment includes a one-field memory 1 that stores one field of video signals, and a reset signal generator 2 that generates a reset signal to control writing and reading of this one-field memory 1. This is a configuration that is equipped with.

The 1-field memory 1 is constructed in the same manner as the prior art shown in FIG.
w and the system clock 4fsc1, and this written video signal is read out as a display video signal Sv based on the read reset signal RSTR specifying the image starting point on the display side and the system clock 4fsc2, and this read out video signal The configuration is such that the display video signal Sv is output to a display device (not shown).

The reset signal generating section 2 includes a V separation circuit 21 that separates a vertical synchronizing signal SYNCV from a synchronizing signal SYNC for image synchronization of the input video signal So, and a field pulse obtained by the separated vertical synchronizing signal SYNCV. fPw (duty ratio 262.5:262
．． 5) based on the horizontal oscillation frequency signal Hw on the input side and outputs it as a converted field pulse fPw1 with a duty ratio of 263:262, and a converted field pulse f with a duty ratio of 263:262.
Pw1 and the frame pulse FPR, which takes 1 for odd frames and 0 for even frames, in the display video signal Sv on the display side, are found to have an AND condition, and a mask signal fPM is obtained.
AND circuit 23 that outputs this mask signal fPM
The horizontal oscillation frequency signal Hw of the input video signal So is integrated to obtain an even frame starting point signal fP.
262 counter 24 that calculates E, an OR circuit 25 that calculates the OR condition of this even frame starting point signal fPE and the mask signal fPM and outputs a write reset signal RSTME, and a system clock that inputs this write reset signal RSTME. 4fsc1 and outputs the write reset signal RSTw to the one field memory 1, and a display video signal Sv.
This configuration includes a read edge detection circuit 27 that maintains the timing of the display side system clock 4fsc2 using the frame pulse FPR and outputs a read reset signal FPR to the one-field memory 1.

Next, the operation of the synchronizer of this embodiment based on the above configuration will be explained with reference to FIGS. 3 and 4. FIG. 4 shows a basic timing chart of a general synchronizer. First, this basic operation timing starts from the input side with a frame pulse FPw with a duty ratio of 263:262.
(not shown) is input, this frame pulse F
By detecting the edge of Pw, the input video signal So
The write reset signal RSTW1 on the input side is obtained at the leading edge of the field at .

Here, when the relative relationship between the input and display side times is the frame pulse FRR on the display side as shown in (a) in the same figure, the frame pulse FRR from the even field (262H) as shown in (b) in the same figure. The write reset signal RSTW1 is output to the 1-field memory 1 and written in the order of the odd field (263H), and when it is read out again, it is read out as the display frame immediately after writing, as shown by the dashed line arrow in the figure, so the input side Since both the display side and the display side are even fields (or odd fields), "field reversal" does not occur. However, as shown in (c) of the same figure, from the odd field (263H) to the even field (262H)
When the write reset signal RSTw2 is outputted and written to the one-field memory 1 in the order of H) and further read out, "field reversal" occurs because the field states on the input side and the display side are different. . In order to prevent this "field reversal," the horizontal scanning period of the odd field (263H) is adjusted to the even field of 262H, and the even field (262H) is By adjusting the field and making it the read reset signal RSTw3, "
Prevent "field reversal".

Next, a specific operation for preventing "field reversal" in this embodiment will be explained. First, it is assumed that the frame pulse FPR on the display side is displayed in the field order of odd number→even number→odd number as shown in FIG. 3(a). Here, synchronization signal S of input video signal So
YNC is input to the V separation circuit 21, and this V separation circuit 2
1, the vertical synchronizing signal SYNCv is separated and the field pulse fPw on the input side (duty ratio 262.5:26
2.5) (see FIG. 3(c)).

An AND circuit 23 calculates a logical product condition for this converted field pulse fPw1 and the frame pulse FPR on the display side, and the converted field pulse fPw1 is
Of these, pulses Q located in even fields in the frame pulse FPR on the display side are masked, and pulses P located in odd fields in the frame pulse FPR are outputted to output a mask signal fPM (see FIG. 3(e)). reference).

Further, the mask signal fPM is inputted to the 262 counter 24 as a reset signal, and the 262 counter 24
The counter 24 receives 262 digits from the horizontal oscillation frequency signal Hw.
H is integrated to output an odd field starting point signal fPE which becomes the starting point of the next odd field in the frame pulse FPR on the display side (see FIG. 3(f)). The mask signal fPM and the odd frame starting point signal fPE are logically summed by the OR circuit 25, and the write reset signal RSTME is output (see FIG. 3(g)). This write reset signal RSTME is applied to the write edge detection circuit 26.
The signal is synchronized with the system clock 4fsc1 on the input side and output to the 1-field memory 1. This 1-field memory 1 receives the write reset signal RST.
By W, the input video signal So is sequentially written field by field.

Furthermore, the write reset signal RSTW
The video signal written by the read edge detection circuit 2
At step 7, the edge of the frame pulse FPR on the display side is detected as the starting point of the field to be read out, and is synchronized based on the system clock 4fsc2 and read out based on the output read reset signal RSTR as a display video signal Sv. (omitted).

Note that when the present invention is used to display a plurality of video signals on a display device comprising a plurality of display sections, each video signal can be read out from the field memory at a common timing. In addition to the NTSC system, the synchronizer according to the present invention also uses a SECA system.
It can also be applied to M system and PAL system.

[0019]

[Effects of the Invention] As explained above, in the present invention,
The reset signal generating means adjusts the write timing of the write synchronization signal based on the read synchronization signal, outputs a write reset signal, and writes the input video signal to the one field memory at the write timing specified by the write reset signal. This has the effect of preventing reversal of scanning lines on the input side and output side with a simple device configuration. Additionally, when applied to a multi-video display device consisting of multiple display units, the read timing from the field memory for multiple input sources can be made common, resulting in an error in the read timing on the output side (display side). This has the effect of eliminating the factor.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a detailed block diagram of main parts of an embodiment of the present invention.

FIG. 3 is an operation timing chart of an embodiment of the present invention.

FIG. 4 is a general operation timing chart that is a premise of the present invention.

FIG. 5 is a schematic configuration diagram of a conventional synchronizer.

[Explanation of symbols]

1...1 field memory 2...Reset signal generation section 3...Odd-even judgment circuit 21...V separation circuit 22...V latch circuit 23...AND circuit 24...262 counter 25...OR circuit 26...Write edge detection circuit 27...Read edge detection circuit

Claims (2)

[Claims] [Claim 1] 1 for storing one field of a video signal
The input video signal is written into the field memory (1) based on the write synchronization signal, and the input video signal is written in the field memory (1) based on the read synchronization signal, which is asynchronous to the write synchronization signal and includes a signal indicating the starting point of each field in the output video signal. In a synchronizer that reads a video signal from a field memory (1) and also adjusts inversion of scanning lines based on a difference between odd and even numbers of fields between the input video signal and the read output video signal, based on the readout synchronization signal. a reset signal generating means (2) for adjusting the write timing of a write synchronization signal and outputting a write reset signal; A synchronizer characterized by writing. 2. The synchronizer according to claim 1, wherein the reset signal generating means (2) detects that the first field to start reading out of the fields to be written into the one-field memory (1) is an even number. In some cases, the vertical synchronization signal that is the starting point of the field of the input video signal is used as a reference, and when the field to start reading first is an odd number, the horizontal synchronization signal corresponding to an even field from the vertical synchronization signal of the input video signal is used as the reference. A synchronizer that outputs a write reset signal based on a time when a multiple of a scanning period has elapsed.