JP2958929B2 - Time axis correction method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis correcting apparatus using a field memory, and more particularly, to a time axis correcting method and apparatus for obtaining an output while maintaining continuity of a color signal using a field memory.

[0002]

2. Description of the Related Art In a time axis correction method using a field memory, sampled composite video signal data is stored in a field memory in synchronization with a signal having jitter, and the stored composite video signal data is subjected to jitter correction. The time axis is corrected by reading out the signals not included. in this case,
Conventionally, a composite video signal is sampled by a clock pulse synchronized with the composite video signal, A / D converted, and A / D conversion is performed.
The D-converted composite video signal data is written to the field memory based on a clock pulse synchronized with the composite video signal including jitter, and the write address of the field memory is a signal output from the memory controller and synchronized with the reproduced vertical synchronization signal. (WACLR) to clear.

The reading of composite video signal data from the field memory is performed by using a read clock pulse that does not include jitter generated by a crystal oscillator. The read-side color phase information (WRCOL) and the read-side color phase information (RDCOL) are read. When the values match, the address on the read side is cleared by a signal (RACLR) synchronized with the reference vertical synchronization signal obtained by dividing the read clock pulse.
And the color phase information (WRCOL) on the writing side
If the read-out color phase information (RDCOL) does not match the read-out color phase information (RDCOL), the signal (RACLR) is shifted by a half cycle of the color subcarrier. Therefore, the continuity of the color phase on the reading side can be maintained regardless of the relationship between the color phase on the writing side and the color phase on the reading side.

[0004]

However, when the reference position on the writing side and the reference position on the reading side are determined using only the color phase information, the continuity of the color phase is determined when the fields are the same. Can keep. However, when the fields on the write side and the read side are different, there are problems that some lines cannot be read, or that uncertain data is read. That is, when the field length of the composite video signal is written to the field memory as odd fields with 263 scan lines and the even fields as 262 scan lines, and when read as odd fields with respect to the field memory in which information of odd fields is written. The data of the 263rd scanning line is not read out, and when read as an odd field in the field memory in which the information of the even field is written, there is a problem that the data of the 263th scanning line becomes indefinite data. Was.

According to the present invention, even when the color phase differs between the writing side and the reading side, the continuity of the color phase is maintained, the data of all the written scanning lines are read, and the indefinite data is read. It is an object of the present invention to provide a method and apparatus for correcting a time axis without any problem.

[0006]

Time base correction method of the present invention SUMMARY OF], the reference in the time base corrector for correcting a time axis comprises a field memory of the storage capacity one field, which is synchronized with the standards vertical synchronizing signal signal and a signal obtained by the reference signal to half the period duration delay of the color burst signal period, the signal of the reference signal delayed by one horizontal scanning period, the criteria signals (one horizontal scanning period + color burst signal period 1 / 2 period period) and a delayed signal, each of the information in the type information and the color phase information type information and the color phase information and the read side field fields write-out write side
It is characterized in that a match of the information is determined, and a selection is made based on a result of the determination to provide an address clear signal on the read side.

A time axis correcting apparatus according to the present invention is a time axis correcting apparatus having a field memory for one field of storage capacity for correcting a time axis. First match determining means for determining the match with the type of the field written in the field, and the color phase information of the field to be read next to the address clear on the read side and the color phase information of the field written in the field memory. Second match determining means for determining a match, reference signal generating means for generating a reference signal synchronized with a reference vertical synchronization signal, and a first delay circuit for delaying the reference signal for a period of one half of a color burst signal cycle A second delay circuit that delays the reference signal by one horizontal scanning period; and a second delay circuit that delays the reference signal by (one horizontal scanning period + A third delay circuit for delaying the reference signal when the first and second coincidence determining means determine a match, and a third delay circuit for delaying the reference signal when the first and second match determining means determine a match. 2 When the match determination means does not determine a match, the output of the first delay circuit is output. When the first match determination means does not determine the match and when the second match determination means determines the match, the reference signal and the second delay circuit are output. If the first and second match determination means do not determine that both match, the output of the third delay circuit and the output of the first delay circuit are alternately selected, and the address on the read side is cleared. characterized by comprising a selection means for a tomorrow Ru signal.

[0008]

According to the time axis correction method and apparatus of the present invention,
When the field type and the color phase information match on the writing side and the reading side, the reference signal is used. When the field type matches and the color phase does not match, the reference signal is used for a half cycle of the color burst signal cycle. If the field types do not match and the color phases match in the signal delayed for a period, the reference signal is alternately changed by a signal delayed by one horizontal scanning period and the reference signal, and the reference signal is divided by 1 / of the color burst signal period. If the field type and the color phase information do not match in the signal delayed by two periods, the reference signal is delayed by a half period of the color burst signal period and the reference signal is (1 horizontal scanning period + color) The address on the read side is alternately cleared with the delayed signal (a period of 周期 cycle of the burst signal period). The continuity of the side of the color phase is maintained,
Data of all the written scanning lines is read out, and indefinite data is not read out.

[0009]

The present invention will be described below with reference to examples. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention.

In this embodiment, the sampling in the A / D converter D is performed at a clock pulse synchronized with the reproduced composite video signal, for example, at a frequency of 4 fsc, which is four times the color subcarrier.
The sampled composite video signal data is written into the field memory M based on a clock pulse synchronized with the composite video signal containing jitter, and the write address of the field memory M is synchronized with the reproduced vertical synchronization signal output from the memory controller C. Cleared by the set signal (WACLR).

On the other hand, the reading of the coded video signal data from the field memory M is performed by a read clock pulse having a frequency of 4 fsc and containing no jitter generated by the crystal oscillator 1 provided in the memory controller C. The memory controller C includes a timing signal generation circuit T and a switching circuit S.

The timing signal generating circuit T includes a crystal oscillator 1 for oscillating a read clock pulse synchronized with a reference vertical synchronizing signal, and a reference signal (CL generated by dividing the read clock pulse output from the crystal oscillator 1). ), A delay circuit 3 that delays and outputs the reference signal (CL) by two read clock pulse periods,
The delay circuit 4 for delaying the reference signal (CL) by 1H period (H is a horizontal scanning period) and outputting the delayed signal and the reference signal (CL) by 2
A delay circuit 5 is provided which delays and outputs the sum of the read clock pulse period and the 1H period.

The switching circuit S has a write-side color phase information (WRCOL) such as a phase of a color burst signal.
Discrimination circuit 6 for detecting coincidence between the read-side color phase information (RDCOL) and the read-side color phase information (RDCOL).
DFLD) type and read field (WRFL)
D) The coincidence discriminating circuit 7 for detecting coincidence with the type, the outputs of the coincidence discriminating circuits 6 and 7 are decoded and, based on the decoded output, one of the reference signal (CL) and one of the outputs of the delay circuits 3, 4, 5 And a selection circuit 8 that outputs a signal (RACLR) for clearing the read-side address.

Here, when the coincidence discriminating circuits 6 and 7 determine the coincidence, the field type, the color phase, and the field type of the composite video signal set on the next reading side when the address on the reading side of the field memory M is cleared. In the composite video signal written in the field memory M, and the match with the color phase are determined.

In the embodiment constructed as described above,
When the type of the write-side field (WRFLD) matches the type of the read-side field (RDFLD), and the write-side color phase information (WRCOL) and the read-side color phase information (RDCOK) match. , As shown in FIG. The reference signal (CL) is selected as the signal (RACLR). For example, the reference signal (C
L) is output as a signal (RACLR) at the N point of the odd field on the read side as shown in FIG.
The selection circuit 8 also operates in the next even field on the read side.
, The reference signal (CL) is selected and the signal (RACL)
R). Accordingly, in the next even field on the read side, an output 263 lines after the point N is output as a signal (RACLR) for clearing the address on the read side at the point O in FIG.

In the next odd field on the read side, the reference signal (CL) is selected by the selection circuit 8 and output as a signal (RACLR). That is, the output 262 lines after the point O is selected, and is output at the point P in FIG. 2 as a signal (RACLR) for clearing the read-side address. Therefore, as in the conventional case, the field length of the composite video signal is written in the field memory M by maintaining the continuity of the color phase on the read side with the odd field being 263 scanning lines and the even field being 262 scanning lines. All the composite video signal data is read.

Next, when the type of the field on the writing side and the type of the field on the reading side match, but the color phase on the writing side and the color phase on the reading side are mutually inverted, FIG. It is as follows. In the odd field on the reading side, the output of the delay circuit 3 is selected by the selection circuit 8 and is output as a signal (RACLR) for clearing the address on the reading side. Therefore, it is output at the point (N + 2CK) delayed by two read clock pulse periods from the point N shown in FIG.

The output of the delay circuit 3 obtained by reading the next reference signal (CL) by two and delaying the clock pulse period is output as a signal (RACLR) for clearing the read address. Therefore, 2H delayed by 1H from the (N + 2CK) point
The output after 63 lines is selected and delayed by 2 read clock pulse periods from point O shown in FIG. 2 (O + 2CK)
Will be output at the point. Subsequently, the selection circuit 8
At the output of the delay circuit 3, that is, the immediately preceding signal (RA
The output after 262 lines from (CLR) is selected, and is output at a point (P + 2CK) as a signal (RACLR) for clearing the read-side address.

Therefore, in this case, the address on the read side is cleared at the point of time two read clock pulses behind each point in the case shown in FIG. 2, and the color phase on the read side is the same as that in FIG. Because of the inversion, the continuity of the color phase on the read side is maintained, and all the composite video signal data written in the field memory M is read.

Next, when the type of the field on the writing side does not match the type of the field on the reading side, but when the color phase on the writing side matches the color phase on the reading side, it is as shown in FIG. , The output of the delay circuit 4 and the reference signal (CL) are alternately selected. The output of the delay circuit 4 is selected in the odd field on the read side, and is output as a signal (RACKR). Next, the reference signal (CL) is selected and output as a signal (RACKR). Therefore, as shown in FIG. 4, the read address is cleared at the point (N + 1H) with respect to the point N in FIG. 2, and then the reference signal (CL) outputted with a delay of 262 lines, that is, the point O in FIG. 2 (point O in FIG. 2).

Subsequently, the output of the delay circuit 4 is selected in the selection circuit 8. Therefore, the output after 263 lines is selected and output as a signal (RACLR) for clearing the address on the read side. Therefore, the signal is output at the point (P + 1H) in FIG.

In this case, if the writing side is an odd-numbered field and the reading side is an even-numbered field, the composite video signal data of the last 263th line cannot be read out.
The signal (RAC) when the next read side is an odd field
(KR) is delayed by 1H (P + 1 in FIG. 5).
H). When the read side is an even field, the position of the signal (RACKR) is the same as the point O in FIG. This means that the even field has 262 lines and the odd field 2
Since there are 63 lines and the write-side field is an even-numbered field, even if the read-side field is an odd-numbered field, it is cleared by 262 lines and reduced by one line to read the composite video signal data of the write-side even-numbered field. This is because even if reading is performed in an odd field on the side, undefined data is not read. By doing so, the continuity of the color phase on the reading side is maintained, and undefined data is not read.

Next, when the type of the field on the writing side and the type of the field on the reading side are different and the color phase on the writing side and the color phase on the reading side are different, the output of the delay circuit 5 and the delay circuit 3 are alternately selected. In this case, as shown in FIG.
The output of the delay circuit 5 is selected in the odd field on the read side, and is output as a signal (RACKR).
Then, the output of the delay circuit 3 is selected, and the signal (RAC) is selected.
KR). Therefore, as shown in FIG. 5, the read address is cleared at the point (N + 1H + 2 read pulse period) with respect to the point N in FIG.
That is, (O + 2 read pulse period) in FIG.
You will be cleared at points.

That is, the address on the read side is cleared at a position delayed by a half cycle of the color subcarrier from each point in FIG. 4, so that the continuity of the color phase on the read side is maintained and the data is written. All data will be read.

Next, the case of a still picture will be described. In the case of a still image, it is as shown in FIG. In this case, the color phase and the field information on the writing side do not change during the still image, and only the information on the reading side changes. Therefore, the continuity of the color phase can be maintained by combining the above-described cases corresponding to the color phase relation and the field relation, respectively. further,
If the odd field becomes a still image, all lines can be read if the read side is an odd field, and if the even field becomes a still image, undefined data will come out if the read side is an even field. Nor.

In the above-described embodiment, the delay circuit 3
Exemplifies a case of delaying by two reading clock pulse periods, and similarly illustrates a case of delaying the delay circuit 5 by (1H + reading clock pulse period). However, the delay circuit 5 may be advanced by two reading clock pulse periods. In this case, the delay circuit 5 delays (1H-readout clock pulse period).

[0027]

As described above, according to the time axis correction method and apparatus of the present invention, the reference signal synchronized with the reference vertical synchronizing signal and the signal obtained by delaying the reference signal by a half period of the color burst signal period. A signal obtained by delaying the reference signal by one horizontal scanning period and a signal obtained by delaying the reference signal by (one horizontal scanning period + a half period of the color burst signal period) are used to determine the type information and color phase information of the field on the writing side, and Since the read side address clear signal is selected based on the read side field type information and the color phase information, even when the write side and the read side have different color phases, the continuity of the color phase is maintained, There is an effect that data of all the written scanning lines is read out, and undefined data is not read out.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining the operation of one embodiment of the present invention, showing a case where the types of fields match and the color phases also match.

FIG. 3 is an explanatory diagram for explaining the operation of the embodiment of the present invention, showing a case where field types match and color phases do not match;

FIG. 4 is an explanatory diagram for explaining the operation of the embodiment of the present invention, showing a case where field types do not match and color phases match.

FIG. 5 is an explanatory diagram for explaining the operation of the embodiment of the present invention, showing a case where the field types do not match and the color phases do not match;

FIG. 6 is an explanatory diagram for explaining the operation of the embodiment of the present invention, showing a case of a still image.

[Explanation of symbols]

 D A / D converter M Field memory C Memory controller T Timing signal generation circuit S Switching circuit 1 Crystal oscillator 2 Reference signal generation circuits 3, 4, and 5 Delay circuits 6 and 7 Match determination circuit 8 Selection circuit

Claims (2)

(57) [Claims] 1. A time base corrector for correcting a time axis comprises a field memory of the storage capacity one field, and the reference signal synchronized with the standards vertical synchronizing signal, a reference signal of the color burst signal period 1 / and two periods period delayed signal of the signal of the reference signal delayed by one horizontal scanning period, the criteria signals (one horizontal scanning period + color burst signal period 1 /
And 2 periods of the period) delayed signals, to determine a match of the respective information in the type information and the color phase information type information and the color phase information and the read side field fields write-out write side, the determination result
A time axis correction method, wherein the time axis correction signal is selected on the basis of an address clear signal on the read side. 2. A time axis correction apparatus for correcting a time axis by providing a field memory for a storage capacity of one field, comprising: a field type to be read next to an address clear on a read side; First match determining means for determining a match with the type; and second match determining means for determining a match between the color phase information of the field to be read after the address clear on the read side and the color phase information of the field written in the field memory.
Coincidence determining means; reference signal generating means for generating a reference signal synchronized with a reference vertical synchronizing signal; a first delay circuit for delaying the reference signal for a half period of a color burst signal cycle; A second delay circuit that delays by one horizontal scanning period; a third delay circuit that delays the reference signal by (one horizontal scanning period + a half period of the color burst signal period); first and second coincidence determining means When the first match determining means determines that there is a match, the first match determining means determines the match, and when the second match determining means does not determine the match, the output of the first delay circuit is determined. And the second match determining means determines that there is a match, the reference signal and the output of the second delay circuit are alternately output. If the first and second match determining means do not determine that both match, the third delay circuit does not. Output and first delay circuit Select and alternately output, time base correction apparatus characterized by comprising a selection means for the address of the read side and clear tomorrow Ru signal.