JPS6242555B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a television receiver (Pict
-ure in Picture (hereinafter abbreviated as PinP TV). In recent years, in order to make effective use of cathode ray tubes in television receivers, other television programs have been reduced and displayed on a portion of the original television screen.
A so-called small screen insertion (PinP) television has been announced (Nikkei Electronics, December 26, 1977 issue, pp. 127-134, etc.). The concept of this PinP will be briefly explained below with reference to FIGS. 1 to 4.

Figure 1 is a conceptual diagram of PinP, where 1 is the television receiver, 2 is the cathode ray tube, 3 is the main screen section, and 4 is the television receiver.
is a small screen section that is inserted by shrinking another TV screen, and the main screen and small screen are designed so that each channel can be selected independently.

FIG. 2 shows an example of a method for inserting a small screen. is the small screen before reduction, and is the parent screen into which the small screen was inserted. If the screen reduction rate is the scanning period after reduction/the scanning period of the original signal, then if the screen reduction rate of the small screen is 1/3 vertically and horizontally, then the ratio of 1 in 3 scanning lines from the screen of the small screen is , extract it, compress the horizontal period to 1/3 on the time axis, synchronize with the main screen, and insert it into the main screen.
Scanning lines ~ show part of the scanning lines before and after reduction.

FIG. 3 shows the state of small screen insertion on a time axis.
is the video signal before the reduction of the small screen, and is the video signal of the main screen with the small screen inserted. As shown in Figure 2, one out of every three scanning lines is extracted from the small screen video signal and written into an analog or digital field memory to determine the small screen insertion position (bold line part) of the main screen video signal. A two-screen television signal can be obtained by reading out the signal using a clock that is three times as large as the clock signal. At this time, field memory for fields A and B2 is required. That is, when reading memory A, the next field is written to memory B, and when reading memory B, the next field is written to memory A.

FIG. 4 shows a configuration diagram of a conventional example of parts related to the present invention. 11 is an antenna, 12 is a small screen insertion circuit, 13 is a video processing circuit, 14 is a cathode ray tube, 2
1 is a main screen tuner, 22 is an F/video detection circuit, 23 is a sync separation circuit, 31 is a small screen tuner, 32 is an IF/video detection circuit, 33 is a sync separation circuit, 34 and 35 are field memories, A ,B,
36 is a write clock generation circuit, and 37 is a read clock generation circuit.

The small screen video signal obtained by the tuner 31 and the F/video detection circuit 32 is written into, for example, the A field memory 34 by a write clock generation circuit 36 whose timing is determined by a synchronization separation circuit 33. During this time, the video signal of the previous field written in the B field memory 35 is inserted into the reading clock generation circuit 37 whose insertion timing is determined according to the synchronization signal separated by the synchronization separation circuit 23 from the video signal of the main screen. The small screen insertion circuit 12 inserts the video signal of the main screen.

As explained above, the conventional two-screen television achieves its purpose by alternately using two field memories. At this time, the required amount of field memory is 262.5 x 1/3 x 100 x 8 = 70,000 bits if the scanning line is 1/3, the number of horizontal period samples is 100, and each sample is 8-bit digital memory. . Two fields require 140K bits of memory, which is a major obstacle in constructing a two-screen TV.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and to provide a two-screen television in which the amount of memory is reduced by approximately half.

In order to achieve the above object, in the present invention, the video signal of the small screen is transmitted in one horizontal period (one line).
When writing to the field memory in units, on the other hand, when the timing corresponding to the insertion position of the parent screen comes,
The readout is performed using a fast clock that matches the screen reduction rate. FIG. 5 is a diagram showing this timing. If the write timing W and the read timing R do not overlap as shown in a, the contents of A are read out as A' and the contents of B are read out as B'. On the other hand, if the read timing overlaps with the writing period as shown in b, the newly written B′ ₁ , C′ ₁ , etc. are read from the beginning of the memory, but the write and read addresses of the memory Since the write update has not yet been performed after the field matches, the field was written in the previous field.
A′ ₂ , B′ ₂ , etc. will be read. In these cases, the small screen and the main screen are completely independent transmission systems, and the synchronization relationship between them is not defined at all, so there is a high probability that the read timing will occur during the write timing. In the present invention, writing and reading are performed sequentially within one horizontal scan as described above, so the maximum time for writing a small screen cannot be the entire period as shown in FIG. In this case, the screen reduction rate/screen reduction rate + 1×63.5 μs results in a slight loss of the inserted screen, but since the missing portion includes the horizontal retrace period, there is no major effect.

Hereinafter, the present invention will be explained in detail with reference to Examples.

In this example, the reduction rate of the small screen is reduced to 1/3 in both the vertical and horizontal directions.
However, it goes without saying that the present invention is not limited to this. FIG. 6 is a block diagram of the present invention. The same numbers as in FIG. 4 indicate blocks with the same function.

41 is one field memory that can be accessed for each line; 42 is a write clock generation circuit; 4
3 is a read clock generating circuit. FIG. 7 is a timing diagram of FIG. 6. is the video signal of the small screen diagram, is the video signal of the main screen, is 1 field
(F) Memory, is the write timing, and is the read timing. The video signal for the small screen is 3 lines in 1
One line among them is sampled as a group, and the sixth
The data is written into the 1-field memory 41 shown in the figure. At this time, the entire line is not sampled, but only the 3/4 line, for example, excluding the front and rear ends of the line such as the horizontal retrace period, is written. Next, the small screen signal written in the one field memory is read out at a predetermined insertion position on the main screen.

Since the clock frequency is tripled for reading, it can be read in 1/4 line time. As a result, if you start reading immediately after writing ends, writing and reading will not overlap for 1 field memory, and 1 field memory will not overlap.
The purpose of PinP can be achieved by the memory capacity of the field.

In the above embodiment, there are restrictions on the synchronization relationship between the small screen video signal and the main screen video signal. That is, for example, when reading is performed immediately after the write timing, the inserted small screen will protrude from the cathode ray tube when the synchronization position of the main screen corresponds to the horizontal retrace period. In order to eliminate such restrictions, a configuration as shown in FIG. 8 may be used.

9 and 10 are timing diagrams. 8th
In the figure, the same reference numerals as in FIG. 6 represent the same parts.
51 is a 1-line memory or a 1-horizontal scanning period memory such as a 1-line variable delay line. FIG. 9 is a timing diagram when a 1-line memory is used as the memory 51, and represents the timing of the 1-line memory. The video signal of the small screen is once written into the 1-line memory 51, and then written into the 1-field memory 41 by detecting the timing when the 1-field memory 41 is not reading.
At this time, it is necessary that the read timing of the 1-line memory 51 does not overlap with the write timing. 1
The field memory 41 is read out at the timing of inserting the main screen.

FIG. 10 shows a case where the 1-line memory 51 in FIG. 8 is used as a variable delay line, and the concept is exactly the same as that in FIG. 9. Of course, when using a variable delay line, the write and read timings may overlap, so
It is sufficient to obtain a delay of one line. Although the memories in the above configuration are not specifically defined as being digital or analog, there is no problem with either being used in practice.

By the way, as mentioned above with respect to Fig. 5b,
If the read timing overlaps with writing to one field memory, the first part of the memory, for example B′ ₁
In this case, the contents of the B field are written, but in the latter part, the contents of the B field are not written at the end, so the contents _A'2 of the A field before that are read out. So let's consider TV interlacing. The television field is divided into odd (O) field and even (E) field, which exist alternately on the time axis. In terms of space, the O field and E field have images that fill in the gaps between each other, and even on a cathode ray tube, they are scanned in an interlaced manner to fill in the gaps between each other. FIGS. 11b and 11d are diagrams showing the screen state when the state shown in FIG. 5 is reproduced on a small screen ignoring interlacing, and FIG. 11a is a diagram showing the correct reproduction method. The horizontal lines indicate horizontal scanning lines, the numbers on the left indicate their contents, and the symbols on the right indicate the horizontal scanning line number from the top of the O and E fields. For example, O1 is the top of the O field, and E4 is the fourth horizontal scanning line from the top of the E field.

Now, in the case of Fig. 5a, the video signals written in the memory are only for the O or E field, respectively, so the read timing is as shown in the figure, and the same O field as the written field is used. Alternatively, if the data is read in field E, it will be reproduced correctly without any problem as shown in FIG. 11a.
However, when the read timing becomes opposite to the above, as shown by O and E in the cutout, the contents of the O field are read to the E field, the contents of the E field are read to the O field, and the first
As shown in Figure 1b, the playback screen becomes jagged.
(This is especially clear when you think of the diagonal line pattern.) Also, in the case of Figure 5b, if the field is in the state shown in the figure, the reading field will be in the middle (parts B' ₁ and C' ₁ ). Since they match, correct playback is possible, but from the middle (parts A′ ₂ and B′ ₂ )
The fields of the continuation will no longer match - that is, the video signal in the E field will be read out in the O field, or vice versa, so there will be a jagged part from the middle (in this case from O3 and E3) as shown in Figure 11c. The screen will appear. In addition, if the successive fields in Figure 5b are reversed as shown in the brackets, as shown in Figure 11d, it will reach the middle (in this case O2,
Up to E2), the screen is jagged, and after that, the screen plays correctly.

In this way, in PinP TVs, the interlacing may cause images on the small screen to become jagged and difficult to view, so it is necessary to further improve this point in order to obtain a good small screen.

As mentioned above, there are three possible cases where the interlace is reversed on a small screen, resulting in a jagged screen. However, it is difficult to solve this problem at the same time, so in the present invention, we first take measures to interlace correctly at the beginning of the small screen, and then detect that the field of image content changes in the middle of the small screen. At that point, the read address is corrected to interlace correctly.

To this end, in the present invention, it is first necessary to generate a signal indicating whether the field being read or written to the memory is an O field or an E field. Figure 12 is a diagram showing the difference between the O field and the E field, where a is the vertical synchronizing signal (V signal), b
is a horizontal synchronization signal (H signal). As shown in the figure, the number of H signals in one field and the phase relationship between the H signal and the V signal are different between the O field and the E field. Therefore, whether it is an O field or an E field can be easily detected by counting the number of H signals in one field or by detecting the phase between the H signal and the V signal.

Next, we will show how to detect whether or not interlacing is performed correctly at the beginning of a small screen. Figure 13 is a diagram showing how the timing of writing (synchronization of small-screen video signals) and reading (synchronization of TV) becomes different. In this case, the timing of reading is different from the timing of writing shown in a. It shows that the delay is in order of b, c, and d. Now, if the reading timing is between b and c in the figure, at the beginning of reading in the O field (part A), the A of the O field is
The contents of the section will be read out, and will be correctly interlaced at the beginning of the small screen. On the other hand, if the readout timing is between c and d, the contents of the A section of the E field will be read at the beginning of the readout in the O field (part A), so the interlace will be reversed at the beginning of the small screen. , the screen becomes jagged. Since the case d is the same as the case b in terms of the phase relationship between writing and reading, it is sufficient to consider the above two cases. Let x be the time from the beginning of the field of the small screen video signal (more precisely, the switching point of O field and E field detection output) to the end of writing of the first 1H, and from the beginning of the field of the TV image,
If the time until the start of reading out the small screen is y, then normally y>x, so the field of the small screen video signal and the field of the TV video signal are separated at timing t, which is x ahead of the start of reading out the small screen. The above two cases can be discriminated by determining whether the polarity (O field or E field) of the field matches. That is, if the polarities of the fields of both images match at timing t, interlacing is performed correctly at the beginning of the small screen, and if they do not match, the polarities are reversely interlaced.

Next, a method for correcting interlace at the beginning of a small screen will be explained. FIG. 14a is the same as FIG. 11b, and is a conceptual diagram when reverse interlacing occurs at the beginning of the small screen. To correct this, either delay the read address by one time (one line) using the O field when reading from the memory, as shown in Figure 14b, or
The read address may be advanced by one time (one line) using the E field as shown in FIG.

Next, a method for detecting a case where the interlace is reversed in the middle of a small screen will be explained. When the field polarity of the readout content is reversed in Figure 5b, i.e. B' ₁ and
At the boundary between A' ₂ or C' ₁ and B' ₂ , the address signal written into the 1-field memory matches the address signal read from the 1-field memory. In this case, depending on how the address signal is created, whether the match is included in B′ ₁ or C′ ₁ or A′ ₂ or B′ ₂ changes, but generally speaking, the vicinity of the match when both address signals match The field polarity of the read content is inverted. Therefore, depending on the system, it is only necessary to decide whether to correct it when both addresses match or to correct it during the next readout.

A correction method when the interlace is reversed in the middle of a small screen will be explained. Similar to FIG. 11c, FIG. 15a is an example in which the interlace is reversed from the third line of each field. In this case, Figure 15b
When reading from the memory after interlace reversal, the read address may be delayed by one using the O field, as shown in FIG. 3, or the read address may be advanced by one using the E field, as shown in FIG. Figures 15 d and g show the above-mentioned first
This is an example in which interlace correction is performed at the beginning of a small screen using the method b or c in FIG. 4, and FIG. 15 d is based on method b, and FIG. In these cases, after the interlace is reversed in the middle, the read address is set to 1 in the O field when reading from the memory, as shown in Figure 15 e or h.
or E as shown in f and i in the same figure.
All you have to do is delay the read address by one field.

FIG. 16 shows a specific example of the interlace correction circuit of the present invention, which is a peripheral circuit of the field memory 41 shown in FIGS. 6 and 8, and 63 is a memory drive circuit.

First, the operation of interlace correction at the beginning of a small screen will be explained. O field signal (high signal at O field) output 122 of the field polarity detection circuit 641 of the small screen video signal 102 and E of the field polarity detection circuit 642 of the TV video signal 105
The field signal output 121 and the timing t (see FIG. 13) signal output 124 of the timing generation circuit 644 are ANDed. The output of this AND is used when the TV image is an even field signal when the field polarities of the small screen video signal and the TV video signal do not match at timing t (that is, it is necessary to correct interlace at the beginning of the small screen). This is a signal that goes high when . Therefore, input this signal to the read address advance circuit 643,
When reading out the small screen reproduction signal starting x after this signal (see FIG. 13), the correction shown in FIG. 14c can be performed by advancing the readout address by 1.

Next, the operation of interlace correction in the middle of a small screen will be explained. As explained with reference to FIG. 15, when performing interlace correction in the middle of a small screen, it is necessary to change the correction method depending on whether or not the correction is performed at the beginning of the small screen. To this end, in FIG. 16, a correction detection circuit 648 first generates a signal indicating whether or not correction has been made at the beginning of the small screen, and this signal is sent to the polarity selection circuit 64.
Enter 7. In response to this input, the polarity selection circuit 647 outputs, as the selected polarity signal 126, the O field signal of the television image when there is no correction, and the E field signal of the television image when there is correction. This signal 126 is ANDed with the address match signal output 125 of the address match detection circuit 646 and input to the read address delay circuit 645.
In other words, if no correction is made at the beginning of the small screen, the correction shown in Figure 15b is performed by delaying the address by one in the O field when the address matches, and if the correction is made at the beginning of the small screen, the address is changed in the E field when the address matches. By delaying by one, the correction shown in FIG. 15i is performed. Circuit configurations using other methods can also be easily implemented by those skilled in the art based on the above description, so a detailed description will be omitted.

As described above, by means of the present invention, a small screen with good image quality without jaggedness can be obtained by simply preparing one field memory.

As explained above, according to the present invention, the amount of memory required for PinP can be reduced by almost half, resulting in significant reductions in circuit scale and cost.

[Brief explanation of the drawing]

Figure 1 is a conceptual diagram of PinP, Figures 2 and 3 are diagrams for explaining the small screen insertion method, Figure 4 is a block diagram of the conventional device, and Figure 5 is the one-field memory of the present invention. Diagram showing write/read timing,
FIG. 6 is a block diagram of an embodiment of the present invention, FIG. 7 is a timing diagram thereof, FIG. 8 is a block diagram of a configuration example that eliminates the write/read timing constraints in FIG. 6, and FIG. Figure 10 is a timing diagram of Figure 8, Figure 11 is a conceptual diagram showing how it is played back on a small screen without interlace correction, and Figure 12 is a synchronization signal to show the difference in polarity of fields on a TV screen. Waveform diagram, Figure 13 is a diagram showing the detection method when reverse interlacing occurs at the beginning of a small screen, Figure 1
Figure 4 is a conceptual diagram showing a method of interlace correction at the beginning of a small screen, Figure 15 is a conceptual diagram showing a method of interlace correction in the middle of a small screen, and Figure 16 is an interlace correction unit of the present invention. FIG. 2 is a block diagram showing an example of the configuration of main parts of the device. 3... Main screen section, 4... Small screen section, 12... Small screen insertion circuit, 41... Field memory, 42
...Clock generation circuit for writing, 43...Clock generation circuit for continuous output, 51...1 horizontal scanning period memory, 63...Memory drive circuit, 641, 642...
...Field polarity detection circuit, 643...Read address advance circuit, 645...Read address delay circuit, 6
46...Address matching detection circuit, 648...Correction presence/absence detection circuit.

Claims (1)

[Claims] 1. In a two-screen television receiver in which a second television screen is compressed into a part of the first television screen and inserted as a small screen, 1.
one field memory for video signals; means for directly writing the video signal of the small screen into the one field memory every horizontal scanning period using a first clock; means for reading out the first clock with a second clock that is multiplied by the screen compression rate of the small screen and inserting the second television screen into the first television screen, the small screen video signal to the first field memory; Write time of horizontal scanning period (small screen reduction rate) /
(Small screen reduction rate + 1) or less. 2 In a two-screen TV receiver that compresses the second TV screen into a part of the first TV screen and inserts it as a small screen, it is possible to write in every horizontal scanning period and continue reading.
one field memory for video signals; means for writing the video signal of the small screen into the one field memory every horizontal scanning period using a first clock; means for inserting the second television screen into the first television screen by reading out the clock by a second clock multiplied by the screen compression ratio of the small screen; and determining the polarity of the fields of the first and second television screens, respectively. means for detecting, and a time at which information for the first horizontal scanning period is started to be read from the memory for the time period from when the polarity of the field of the second television screen is switched to when the information for the first horizontal scanning period is finished being written to the memory; means for detecting whether or not the field polarities of the first and second television screens match at an earlier time; and if the field polarities do not match, the memory means for performing a first correction of interlace by shifting the address read from the field by one horizontal scanning period in either polarity field; means for detecting the presence or absence of the first correction of interlace; means for detecting that the write address of the memory matches the read address; and a means for detecting that the write address of the memory matches the read address; A two-screen television receiver comprising means for performing a second interlace correction by shifting the address read from the memory by one horizontal scanning period using a polarity field. 3. Claim 2, characterized in that the writing time of the small screen video signal into the one field memory is set to less than (small screen reduction rate)/(small screen reduction rate + 1) of the horizontal scanning period. Dual screen TV receiver as described. 4 Furthermore, a video signal memory for one horizontal scanning period is provided, and the small screen signal is once written in the one horizontal scanning period memory, and then when the one field memory is not reading out, the one horizontal scanning period memory is written. 3. The two-screen television receiver according to claim 2, wherein the signal is transferred to the one-field memory. 5. The two-screen television receiver according to claim 4, wherein the one-horizontal scanning period memory is replaced with a variable delay line.