JPS6223507B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving image quality when a sub-screen is a still image in a two-screen television receiver.

A two-screen TV having one field of field memory is realized by the method described below. Figure 1 is a configuration diagram of a two-screen television with one field memory, in which 1 is an antenna, 2 is a main screen tuner, 3 and 9 are IF/
A video detection circuit, 4 a sub-screen insertion circuit, 5 a video processing circuit, 6 a cathode ray tube, 7 and 14 a sync separation circuit, 8 a sub-screen tuner, 10 an A/D circuit,
11 is a 1-line memory, 12 is a 1-field memory, 13 is a D/A circuit, 15 is a write address generation circuit, 16 is a read address generation circuit, 17 is an interlace correction circuit, and 18 and 19 are field polarity determination circuits. It is.

FIG. 2 is a diagram showing a state in which a sub-screen is inserted in a two-screen television having one field memory.

is the video signal of the child screen, is the composite video signal after inserting the reduced child screen video signal into the main screen video signal, is the timing of accessing the field memory, of which is the timing of writing to the field memory, is the timing of writing from the field memory This is the read timing. Or it is the writing timing to 1 line memory.

A television signal input from an antenna 1 is tuned by a main screen tuner 2, detected and amplified by an IF/video detection circuit 3, and then supplied to a child screen insertion circuit 4 and a synchronization separation circuit 7. On the other hand, the above television signal is tuned by the small screen tuner 8, detected and amplified by the IF/video detection circuit 9, and then sent to the A/D circuit 10 and the sync separation circuit 14.
is supplied to The small screen video signal digitized by the D/A circuit 10 is written into the one-line memory 11 according to the address generated by the write address generation circuit 15, and according to the address generated by the read address generation circuit 16. 1 line memory 11 to 1 field memory 12
After being transferred to , it is read out from the 1-field memory in accordance with the address generated by the read address generation circuit 16 as well. The digitized reduced small screen video signal read out from the 1 field memory 12 is converted into an analog signal by the D/A circuit 13 and then supplied to the small screen insertion circuit 4.

The reduced child screen signal is combined with the main screen video signal from the IF/video detection circuit 3 in the child screen insertion circuit 4, and is supplied to the video processing circuit 5 as a composite video signal in which the child screen is inserted into the main screen. It is displayed on the cathode ray tube 6.

The process of receiving the television signal by the antenna 1 and displaying it as a parent-child screen image on the cathode ray tube has been described above. Next, the process of reducing the child screen video signal will be described. The write address generation circuit 15 starts generating addresses after a predetermined time has elapsed in synchronization with the horizontal synchronization signal from the synchronization separation circuit 14 as shown in FIG. Then, in synchronization with the vertical synchronization signal from the synchronization separation circuit 14, after a predetermined period of time has elapsed, the address is sent to one line memory 11 once per horizontal scanning period according to the compression ratio. supply. The read address generation circuit 16 starts generating addresses after a predetermined time has elapsed in synchronization with the horizontal synchronization signal from the synchronization separation circuit 7, and stops generating addresses after a predetermined time has elapsed, as shown in FIG. . The frequency of this address is determined by the write address generation circuit 1.
If the compression ratio is 1/3 of the frequency of address 5, the frequency will be tripled, and in synchronization with the vertical synchronization signal from the synchronization separation circuit 7, it will be displayed as a sub-screen or moved to the position. After the time has elapsed, supply to the field memory 12 is started, and the supply is stopped after the time has elapsed. Further, as shown in FIG. 1, the read address generation circuit 16 generates 1
Generates an address for transferring data from the line memory 11 to one field memory 12, and depending on the compression ratio, for example, when the compression ratio is 1/3, the address for writing to one line memory 11 is generated once every three horizontal scanning periods. Addresses are supplied to the 1-line memory 11 and the 1-field memory 12 during a period when the address is not supplied from the generation circuit 15.

As described above, a reduced small screen video signal is obtained by digitizing the small screen video signal, sampling it according to the compression ratio, writing it into a memory, reading it out at a speed corresponding to the compression ratio and converting it into analog.
By combining this with the main screen video signal, a parent-child composite video signal is obtained, which can be displayed on a cathode ray tube as a two-screen television.

By the way, let us consider the phase relationship between the main screen video signal and the sub-screen video signal. FIG. 3 is a diagram showing a case (a) in which reading and writing of the field memory do not overlap and a case (b) in which they overlap due to the phase relationship between the two. In the case of b, the reading timing overlaps with writing to the 1-field memory, so the content of the B field is written in the first part of the memory, for example B' ₁ , but the content of the B field is written in the later part. Since A'2 has not been written, the contents _A'2 of the previous A field will be read. So let's consider TV interlacing. The television field is divided into an odd (O) field and an even (E) field, which exist alternately on the time axis. Spatially, O field and E
The field has images that fill in the gaps between each other, and even on the cathode ray tube, the images are scanned in an interlaced manner that fills in the gaps between each other. Figure 4b
-D are diagrams showing screen states when the state shown in FIG. 2 is reproduced on a small screen while ignoring interlacing, and "a" is a diagram showing the correct reproduction method. The horizontal lines indicate horizontal scanning lines, the numbers on the left indicate their contents, and the symbols on the right indicate the horizontal scanning line number from the top of the O and E fields. For example, O1 is the top of the O field, and E4 is the fourth horizontal scanning line from the top of the E field.

Now, in the case of Fig. 3a, the video signals written in the field memory are only for the O or E field, respectively, so the readout timing is as shown in the figure, and moreover, it is the same as the written feed. If you read it in field O or E,
The data is reproduced correctly without any problems as shown in FIG. 4a. However, the read timing is opposite to the above,
When the O and E in the box become as shown, the contents of the O field will be read to the E field, and the contents of the E field will be read to the O field.
As shown in FIG. 4b, the playback screen becomes jagged. (This is especially clear when you think of the diagonal line pattern.) Also, in the case of Figure 3b, if the field is in the state shown in the figure, it will reach halfway (parts B' ₁ and C' ₁ ).
Since the reading and writing fields match, correct playback is possible, but from the middle (parts A' ₂ and B' ₂ ), the reading and writing fields no longer match - that is, the E field's video signal is the O field. , or vice versa, so Figure 4c
As shown in the figure, the screen becomes jagged from the middle (from O3 and E3 in this case). Also, if the readout field is reversed as shown in the box in Figure 3b, the field will be read halfway (in this case O
2, up to E2) is a jagged screen, and after that the screen is played correctly.

As mentioned above, on dual-screen TVs, the image quality of the sub-screen may deteriorate due to interlacing, so
In order to improve the image quality, if the interlacing is reversed, correction is performed to restore normal interlacing. An example of this interlace correction for the case c in FIG. 4 is as follows. In FIG. 5, a is an example in which interlace correction is not performed, that is, the interlace is reversed from the third line of each field, as in c in FIG. In this case, as shown in Figure 5b, when reading from the memory after interlace reversal, the read address is delayed by one using the O field, or
The read address can be advanced by one using the E field as shown in FIG. In this way, although the seam is somewhat discontinuous at the correction start point, it is possible to realize a child screen that is well interlaced thereafter.

In FIG. 1, this means that the field polarity determination circuit 18 determines the polarity of the field on the main screen based on the vertical and horizontal synchronization signals from the synchronization separation circuit 7, and the vertical and horizontal synchronization signals from the synchronization separation circuit 14 as well. Based on the horizontal synchronization signal, the field polarity determination circuit 19 determines the polarity of the field on the sub-screen, and based on the line memory → field memory transfer address and field memory read address of the read address generation circuit 16, an interlace correction circuit is activated. At step 17, the read address generation circuit 16 is controlled according to the correction method described above. As described above, a two-screen television with one field memory realizes a good sub-screen image.

By the way, in the above-mentioned two-screen TV, the read address generation circuit 16 is the one-line memory 11,
When the supply of the transfer address to the field memory 12 is stopped, the read address generation circuit 16 supplies only the read address of the field memory, and after that, the contents before the supply of the transfer address is stopped as a reduced sub-screen signal. Since each field is read out, the sub-screen can be a still image. However, normally, the vertical synchronization signal of the main screen video signal and the vertical synchronization signal of the sub-screen video signal are
If there is a slight frequency difference and the above-mentioned interlace correction is activated, this slight frequency difference causes the interlace correction start point to move vertically on the child screen. This phenomenon is hardly noticeable when viewing the sub-screen as a moving image because the contents of the entire sub-screen changes, but it has the disadvantage that it is extremely difficult to view when the sub-screen is a still image.

SUMMARY OF THE INVENTION An object of the present invention is to provide a two-screen television receiver having one field memory that improves image quality deterioration of a sub-screen image due to interlace correction when the sub-screen is a still image.

When a sub-screen is a still image in a two-screen television having one field memory, the image quality of the sub-screen deteriorates due to interlace correction. Therefore, when writing to the field memory is stopped, interlace correction is also stopped, thereby preventing deterioration in the image quality of the still child screen.

FIG. 6 shows an embodiment of the present invention. In FIG. 6, the same parts as in the conventional example shown in FIG. 1 are denoted by the same numbers.

20 is a sub-screen switch for making the sub-screen a still image, and 21 is a power supply. When the small screen still switch is open as shown in the figure, the read address generation circuit 16 and the interspace correction circuit 17 operate as described in the conventional example.
On the other hand, when the sub-screen static switch 20 is closed and the power supply voltage is supplied to the read address generation circuit 16 and the interlace correction circuit 17, the read address generation circuit 16 is activated to transfer data from the line memory to the field memory. Address supply is stopped, and interlace correction circuit 17 further controls read address generation circuit 16 to stop performing interlace correction.

In the above configuration, closing the child screen freeze switch 20 stops writing to the field memory and also stops interlace correction, so even if the phase difference between the main screen video signal and the child screen video signal changes, The interlace correction start point moves up and down on the sub-screen which has become a still image, and the sub-screen image does not deteriorate.

As described above, according to the present invention, when the sub-screen of a two-screen television having one field memory is a still image, image deterioration caused by the interlace correction circuit can be improved.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a two-screen TV receiver with one field memory, Figure 2 is a timing chart showing the insertion state of a child screen, and Figures 3a and b are the phases of the main screen video signal and the child screen video signal. FIGS. 4a to 4d are state diagrams showing the case where interlace becomes abnormal due to the phase relationship between the main screen video signal and the child screen video signal; FIG.
Figures a to c are state diagrams when interlace correction is performed, and Figure 6 is a block diagram showing one embodiment of the present invention. 16: Read address generation circuit, 17: Interlace correction circuit, 20: Small screen freeze switch.

Claims (1)

[Claims] 1. In order to compress the second television screen into a part of the first television screen and insert it as a small screen, it has one field memory of a video signal that can be written and read every one horizontal scanning period, and The small screen is written in the field memory with a first clock every horizontal scanning period, and outside the writing time, the first clock is read out with a second clock that is multiplied by the screen compression rate of the small screen, and the second clock is read out. In a two-screen television receiver having a television screen inserted into a first television screen, means for detecting the polarity of the fields of the first and second television screens, respectively; Based on the polarity of
and means for correcting interlace by controlling a read address when reading from the one-field memory, and the means for correcting interlace when writing to the one-field memory is stopped. , a two-screen television receiver characterized in that interlace correction is stopped.