JP3179412B2 - Multi-screen control circuit of MPEG decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multi-screen control circuit and method for displaying a plurality of screens, and more particularly, to a DVD.
The present invention relates to a multi-screen control circuit and a method incorporated in an MPEG decoder used for such purposes.

[0002]

2. Description of the Related Art A multi-screen control circuit configured for an MPEG decoder for DVD generally has a function of displaying a small screen obtained by reducing a video signal of a full screen size. As a method for realizing such a multi-screen display function, small-screen data is alternately written to small-screen display corresponding positions in two field memories provided for each of the first field and the second field, A method of reading the entire screen for each field is adopted. At this time, reading from each field memory
It is performed for each horizontal synchronization signal of the scanning line.
This is performed while reducing the entire screen size data to the child screen size. Specifically, writing is performed at a timing at which the synchronization signal is thinned out according to the screen reduction ratio.

Therefore, memory access is performed at a frequency of several times of reading for one writing, but the same time is required from the start to the end of each of reading and writing for one screen. For this reason, depending on the display designation position of the child screen and the selection state of the field memory to be read, there is a disadvantage that an overtaking phenomenon occurs in which an area of the field memory in which data writing has not yet been performed is read first.

FIGS. 15 and 16 are diagrams for explaining the overtaking phenomenon. The example shown in FIGS. 15 and 16 is a case where a child screen reduced to one third is displayed at one third of the entire screen. Here, V is the time required to read one field and the time required to write one field. FIG.
, The relationship between the memory read address and the read time is represented by READ, and the relationship between the memory write address and the write time is represented by WRITE. For reading three lines of the entire screen, writing of one line of the child screen is performed. Therefore, while reading one third to two thirds of the display lines of the full screen, writing of the child screen is overtaken by reading, Lower half of child screen
However, the image is not updated. The hatched portions in FIGS. 15 and 16 indicate the overtaking occurrence areas.

FIG. 12 is a block diagram showing the configuration of a conventional example of a circuit proposed to solve the above-mentioned overtaking phenomenon.

In this conventional example, two field memories 12 are used.
01, 1202, a write address generation circuit 1203,
Read address generation circuit 1204, sync separation circuit 12
05, an MPEG decoding unit 1206, a read memory determination circuit 1207, and a switch 1208.

[0007] From the synchronization separation circuit 1205 to the write address generation circuit 1203, the read address generation circuit 120
4 and the MPEG decoding unit 1206 are supplied with a field pulse 1205a and a synchronous clock 1205c, and each of the supplied units operates in synchronization with the pulse and the clock.

[0008] The MPEG decoding unit 1206 stores the decoded image data 1206a in the field memories 1201 and 1202.
And a sub-screen synchronization clock 1206c synchronized with the sub-screen is sent to the write address generation circuit 1203, and a data discrimination signal 1206 indicating the content of the image data is provided.
b is sent to the read memory generation circuit 1207.

A write address generation circuit 1203 receives a write address (WADR) 1203 from each of these inputs.
a and a write enable (WE) 1203b, and the read address generation circuit 1204 generates a read address (RADR) 1204a and a read enable (RE) 1204b, and
01, 1202. Read memory decision circuit 1
Reference numeral 207 inputs a small screen display position and a data discrimination signal 1206b given from the outside, and generates a read field signal 1207b. Write enable 1203b
WE1 and WE2 that receive a write enable signal 1203b and a data discrimination signal 1206b, and select one of the field memories 1201 and 1202 by a logic circuit composed of two AND circuits and one inverter. Is generated and each field memory 1
201 and 1202. Read enable 1
RE1, which receives a read enable 1204b and a read field signal 1207b as inputs, and selectively selects one of the field memories 1201 and 1202 by a logic circuit composed of two AND circuits and one inverter. RE2 is generated and output to each of the field memories 1201 and 1202. The read field signal 1207b generated by the read memory determination circuit 1207 is also output to the switch 1208.

The data discrimination signal 1206b indicates the display position of the sub-screen and the field data of the image data 1206a reduced for the sub-screen, and the read memory determination circuit 1207 which inputs this data causes the above-mentioned overtaking phenomenon to occur. It determines which of the field memories is not to be read, and outputs a read field signal 1207b.

Although the overtaking phenomenon does not occur in the circuit shown in FIG. 12 configured as described above, the image quality may be deteriorated. The problem will be described with reference to FIG. 14 showing the operation timing of the circuit shown in FIG.

FIG. 14A is a timing chart at the time of normal operation, and FIG. 14B is a timing chart at the time of deteriorating image quality. In FIGS. 14A and 14B, the first field corresponding data is Top and the second field corresponding data is Bottom. FIGS. 14 (a) and (b)
FIG. 9 is a timing chart when the read memory determination circuit 1207 determines that the read field signal 1207b has the opposite phase to the data determination signal 1206b from the input position of the child screen display and the data determination signal 1206b. The scanning fields in FIGS. 14A and 14B are signals indicating which field is being scanned by a scanning line when image data is displayed.

When the data discrimination signal 1206b and the scanning field are in opposite phases, as shown in FIG.
Since the field image data is output during the first field of the scanning field and the second field image data is output during the second field of the scanning field, the image data output from the MPEG decoding unit is faithfully reproduced. However, in the MPEG decoder, since it is not determined which of the first field image data and the second field image data is reproduced first, as shown in FIG. 14B, the data discrimination signal 1206b and the scanning field have the same phase. In this case, the second field image data is output when the scanning field is the first field, and the first field image data is output when the scanning field is the second field.

As a countermeasure for alleviating the above-mentioned deterioration in image quality, for example, a circuit shown in FIG. 13 is known. The field memories 1301 and 1302, the write address generation circuit 1303, and the read address generation circuit 13 in FIG.
04, sync separation circuit 1305, MPEG decoder 130
6. Read memory determination circuit 1307 and switch 1
The configuration and operation of the field memory 309 are the same as those of the field memories 1201 and 1202 shown in FIG.
203, the read address generation circuit 1204, the sync separation circuit 1205, the MPEG decoder 1206, the read memory determination circuit 1207, and the switch 1208 are the same, and the description is omitted.

In the circuit shown in FIG.
05 is configured to output a field discrimination signal 1305b indicating which field is the current parent screen, and a center-of-gravity correction filter 1308 is newly provided. The center of gravity correction filter 1308 includes a switch 1309
Output, read enable 1307a and field discrimination signal 1305b are input, and when the read memory decision circuit 1307 decides to read image data of the field opposite to the field discrimination signal 1305b, the center of gravity is corrected for the output of the switch 1309. is there.

[0016]

Among the above-mentioned prior arts, the one shown in FIG. 12 does not cause the overtaking phenomenon, but has a problem that the image quality may be deteriorated.

Further, in the example shown in FIG. 13, the correction of the center of gravity is performed, but this is merely a correction of the image quality.
There is a problem that an image cannot be faithfully reproduced. SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the conventional technology, and has been made in consideration of an MPEG decoder capable of preventing an overtaking phenomenon without deteriorating image quality and faithfully reproducing an image. An object is to realize a multi-screen control circuit.

[0018]

According to the present invention, a multi-screen control circuit of an MPEG decoder outputs a field pulse synchronizing with a main screen and a field discrimination signal indicating whether the main screen is the first field or the second field. A sync separation circuit for outputting, a first field memory and a second field memory provided corresponding to the first field and the second field of the small screen, and a small screen display position supplied from the field pulse and externally And an offset circuit that outputs an offset field pulse to which an offset amount corresponding to a timing at which a child screen in the parent screen is displayed is provided, and a video signal is decoded and decoded based on the offset field pulse. The screen is either the first field or the second field M to output the data discrimination signal indicating the
A PEG decoding unit, read memory selecting means for supplying a read address to a field memory provided for a field indicated by the field discrimination signal based on the field pulse, and the data discrimination based on the offset field pulse Write memory selection means for supplying a write address to a field memory provided for a field indicated by the signal.

In this case, the synchronizing separation circuit outputs a synchronizing clock synchronized with the main screen, the offset circuit is reset by the field pulse, and counts up by the synchronizing clock. A timing adjustment circuit for inputting a sub-screen display position indicating a display position and the field pulse, and adjusting the timing of the sub-screen display position by the field pulse; It may be constituted by a comparator that outputs an offset field pulse when the value of the received child screen display position matches.

A multi-screen control circuit of an MPEG decoder according to another embodiment of the present invention outputs a field pulse synchronized with the main screen and a field discrimination signal indicating whether the main screen is the first field or the second field. A synchronization separation circuit, a first field memory and a second field memory provided corresponding to the first field and the second field of the sub-screen, and input of the field pulse and a sub-screen display position supplied from outside. Delay means for outputting as an offset field pulse to which an offset amount corresponding to the timing at which the child screen in the parent screen is displayed; and decoding of the video signal based on the offset field pulse and decoding of the decoded child screen. Indicates whether the field is the first field or the second field An MPEG decoding unit for outputting a data discrimination signal; read memory selecting means for supplying a read address to a field memory provided for a field indicated by the field discrimination signal based on the field pulse; And write memory selection means for supplying a write address to a field memory provided for a field indicated by the data discrimination signal based on the data discrimination signal.

In this case, the delay means includes a delay circuit for giving a predetermined delay amount to the field pulse and outputting it as an offset field pulse, a child screen display position indicating the display position of the child screen supplied from the outside, and a field pulse. And a timing adjustment circuit that outputs a delay amount determined by the sub-screen display position at the timing indicated by the field pulse, and a timing adjustment circuit output, and obtains the delay amount obtained from the timing adjustment circuit output. And a delay amount control circuit for controlling the delay circuit.

A multi-screen control circuit of an MPEG decoder according to still another embodiment of the present invention includes a vertical line count value synchronized with a main screen and a field discrimination signal indicating whether the main screen is the first field or the second field. , A first field memory and a second field memory provided corresponding to the first field and the second field of the child screen, and the vertical line count value and a child supplied from the outside. A subtraction circuit for inputting a screen display position, outputting as an offset vertical line count value to which an offset amount corresponding to a timing at which a child screen in the parent screen is displayed, and a video signal based on the offset vertical line count value. Decoding and decoding the decoded sub-picture are the first field and the second field An MPEG decoding unit for outputting a data discrimination signal indicating which one is used, and a read memory selection for supplying a read address to a field memory provided for a field indicated by the field discrimination signal based on the vertical line count value And write memory selection means for supplying a write address to a field memory provided for a field indicated by the data discrimination signal based on the offset vertical line count value.

In this case, the subtraction circuit inputs the small screen display position indicating the display position of the small screen and the vertical line count value supplied from the outside, and subtracts the subtraction amount determined by the small screen display position from the vertical line count. A timing adjustment circuit that outputs at the timing indicated by the value, and a subtractor that generates an offset vertical line count value by subtracting the subtraction amount sent from the timing adjustment circuit from the vertical line count value. Good.

According to still another aspect of the present invention, there is provided a multi-screen control circuit for an MPEG decoder, comprising: a field pulse synchronized with a main screen;
A main screen sync separation circuit for outputting a field discrimination signal indicating which one of the fields, a first field memory of a small screen size provided corresponding to the first field and the second field of the small screen, and a second field memory A field memory and an offset circuit for inputting the field pulse and a sub-screen display position supplied from the outside, and outputting as an offset field pulse to which an offset amount corresponding to a timing at which the sub-screen in the main screen is displayed is provided. A sub-picture MPEG decoding unit that decodes the video signal of the sub-picture based on the offset field pulse and outputs a data discrimination signal indicating whether the decoded sub-picture is the first field or the second field; Based on the field pulse and the sub-screen display period supplied from outside, There are a read memory selection means for supplying a read address to the field memory provided for the field indicated by the field determination signal,
Write memory selection means for supplying a write address to a field memory provided for a field indicated by the data discrimination signal based on the offset field pulse.

According to still another aspect of the present invention, there is provided a multi-screen control circuit for an MPEG decoder, comprising: a field pulse synchronizing with a main screen, a synchronizing clock, and a field discrimination indicating whether the main screen is the first field or the second field. A main screen sync separation circuit for outputting a signal; a first field memory and a second field memory of a small screen size provided corresponding to the first and second fields of the small screen; An offset circuit for inputting a sub-screen display position supplied from the sub-screen and outputting as an offset field pulse to which an offset amount corresponding to a timing at which the sub-screen in the main screen is displayed, and a sub-screen based on the offset field pulse Of the video signal of the A sub-screen MPEG decoding section for outputting a data discrimination signal indicating whether the field is a field or a second field and a sub-screen synchronization clock synchronized with the sub-screen; Read-out memory selection means for providing read-out enable to a field memory provided for a field indicated by the field discrimination signal, based on the first field memory and the second field memory. The write address is reset to the initial value 0 by the offset field pulse input to the pointer reset, and the read address pointer is reset to the initial value 0 by the field pulse input to the address read pointer reset.
And when the data discrimination signal input as a write enable signal is active and a sub-screen synchronization clock is input, the write address pointer is incremented and input as a read enable signal. The read address pointer is incremented when a synchronous clock is input while the output is active.

[Operation] In the present invention, in order to improve the image quality at the time of multi-screen output in the multi-screen control circuit of the MPEG decoder, the timing at which the sub-screen of the main screen is displayed in the field memory write control portion is improved. Since the corresponding offset amount is given and the field memory write is performed after the child screen start position, the addresses of the field memory write and the field memory read do not match, and the overtaking phenomenon does not occur. Further, the image data for the first field is changed to the second image data at the time of the first field scanning by the field discrimination signal.
The field image data is reliably output during the second field scan.

[0027]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a multi-screen control circuit according to the present invention.

In this embodiment, the field memories 101, 1
02, a write address generation circuit 103 and a read address generation circuit 10 for respectively generating a write address and a read address for each field memory
4. It comprises a sync separation circuit 105, an MPEG decoding unit 106, an offset circuit 107 and a switch 108.

The synchronization separation circuit 105 has a synchronization clock 105 having the same frequency as the sampling frequency synchronized with the screen.
c, a field discrimination signal 105b indicating whether the screen is the first field or the second field, and a field pulse 105 synchronized with the synchronization clock 105c.
is output. The offset circuit 107 receives the field pulse 105a, the synchronous clock 105c, and the small-screen display position 100a supplied from the outside, and outputs an offset field pulse 107a.

The MPEG decoding unit 106 receives the offset field pulse 107a, and the first field or the second field is a compressed video signal 106a obtained by compressing a video signal as a small screen and a screen in which writing is performed in synchronization with the compressed video signal 106a. It outputs a data discrimination signal 106b and a sub-screen synchronization clock 106c indicating whether or not this is the case.

The write address generating circuit 103 receives the offset field pulse 107a, the sub-screen display position and the sub-screen synchronization clock 106c, and generates and outputs a memory write address (WADR) 103a and a write enable (WE) 103b. I do.

The write enable 103b receives the write enable 103b and the data discrimination signal 106b as inputs, is constituted by two AND circuits and one inverter, and is constituted by a logic circuit constituting write memory selection means together with the write address generation circuit 103. WE1 and WE2 for selecting one of the field memories 101 and 102 are generated, and the respective field memories 1 and 102 are generated.
01 and 102.

The read address generation circuit 104 receives the field pulse 105a and the synchronous clock 105c, and inputs a memory read address (RADR) 104a.
And a read enable (RE) 104b are generated and output.

From the read enable 104b, the read enable 104b and the field determination signal 105b
RE1 which is constituted by two AND circuits and one inverter, and selects one of the field memories 101 and 102 alternatively by a logic circuit constituting read memory selection means together with the read address generation circuit 104 , RE2 are generated and output to the respective field memories 101 and 102. Field discrimination signal 1
05b is also given to the switch 108, whereby the read-out field memory is selected and output to the outside as a video data signal output.

The compressed video signal 106a is supplied to the field memories 101 and 102,
Out of 01 and 102, the compressed video signal 106a is written to the memory write address 103a to which WE1 and WE2 are input.

On the other hand, reading from the field memory is performed from the read address 104a of the memory to which the above RE1 and RE2 are input, and output from the switch 108, and display based on the output is performed.

FIG. 2 is a diagram showing the configuration of the offset circuit 107, which comprises a counter 111, a timing adjustment circuit 109, and a comparator 110 as shown. The counter 111 is reset by the field pulse 105a and counts up by the synchronous clock 105c. The timing adjustment circuit 109 inputs the small screen display position 100a and the field pulse 105a, and adjusts the timing of the small screen display position 100a by the field pulse 105a. Comparator 11
0 is the output of the counter 111 and the timing adjustment circuit 10
In step 9, when the value of the child screen display position 100a whose timing has been adjusted by the field pulse 105a matches, that is, when the same amount of offset as the child screen display position 100a is inserted, the offset field pulse 107a is output. I do.

The MPEG decoding unit 106, the sync separation circuit 105, the write address generation circuit 103, the read address generation circuit 104 and the field memory 10 in FIG.
Reference numerals 1 and 102 are well known to those skilled in the art, and are not directly related to the present invention.

Next, the operation of this embodiment will be described.
FIG. 3 is a timing chart showing the operation of the present embodiment, which will be described below with reference to FIG.

The data corresponding to the first field of the data discrimination signal 106b is Top, and the data corresponding to the second field is Bo.
tttom, each field memory 101, 102
Is read from the field determination signal 105b.
Indicates the first field, the processing is performed from the field memory 101, and the field determination signal 105b
Indicates the second field, the processing is performed from the field memory 102.

On the other hand, data is written by the data discrimination signal 10 synchronized with the offset field pulse 107a.
When 6b indicates the first field, it is performed for the field memory 101, and the data discrimination signal 106b is
When indicating a field, it is performed for the field memory 102. As described above, the offset field pulse 107a is smaller than the field pulse 105a.
This is output with an offset of the same amount as the difference between the display start position and the small screen display position.

Next, the relationship between reading and writing of each of the field memories 101 and 102 in this embodiment will be described with reference to FIG. In FIG. 4, the vertical axis indicates the address value of the field memory, and the horizontal axis indicates the display time.

In FIG. 4, V is the time required for reading and writing for one field, and the relationship between the memory read address and the read time is represented by READ.
The relationship between memory write address and write time is WRIT
It is represented by E. The field memory address value corresponding to the small screen display start position is A1, and the field memory address value corresponding to the small screen display end position is A2.
Then, in READ, all the field memory values are read out over V time. When READ reaches A1, that is, when the time corresponding to the small screen display start position has elapsed, WRITE is started, and A2 is read. Is written during the time V until the data reaches.

In this embodiment configured as described above, since the writing timing to the field memory has an offset corresponding to the display of the small screen, the phenomenon that the field memory reading overtakes the field memory writing occurs. I will not do it. Further, the image data for the first field is output at the time of the first field scan and the image data for the second field is output at the time of the second field scan by the field discrimination signal, so that the image quality is always kept good.

Next, a second embodiment of the present invention will be described.

This embodiment has a basic configuration similar to that of the first embodiment, and uses a delay means 507 as shown in FIG.

The delay means 507 comprises a timing adjustment circuit 5
09, a delay amount control circuit 510 and a delay circuit 511. The timing adjustment circuit inputs the small-screen display position and the field pulse, and adjusts the timing of the small-screen display position by the field pulse. In the delay amount control circuit 510, the timing adjustment circuit 509 calculates the delay amount from the value of the sub-screen display position whose timing has been adjusted by the field pulse.
By this, an offset field pulse in which the above-described delay amount is added to the field pulse input to the delay circuit 511 is output, and the same write and read operations as in the first embodiment are performed for each field memory. Done.

Next, a third embodiment of the present invention will be described.

FIG. 6 is a circuit block diagram showing the configuration of this embodiment. In the present embodiment, the offset circuit 107 in the first embodiment shown in FIG. 1 is replaced by a subtraction circuit 607, and the sync separation circuit 105 which outputs the field pulse 105a.
Is a sync separation circuit 605 that outputs a vertical line count value 605a. Other field memories 601, 602, a write address generation circuit 603, a read address generation circuit 604, and an MPEG decoding unit 6
06 are the field memories 10 shown in FIG.
1, 102, a write address generator 103, a read address generator 104, and an MPEG decoder 106
Since these are the same including the signals output therefrom, the description is omitted.

The subtraction circuit 607 has a subtractor 710 and a timing adjustment circuit 709 therein as shown in FIG. 7, and the timing adjustment circuit 709 calculates the subtraction amount determined by the sub-screen display position by the vertical line count value. 60
Output to the subtractor 710 at the timing shown in 5a. The subtractor 710 subtracts the subtraction amount sent from the timing adjustment circuit 709 from the vertical line count value 605a generated by the sync separation circuit 605, generates an offset vertical line count value, and outputs the offset vertical line count value.
6 is given.

In each of the embodiments described above, a system for reducing the entire screen to a small screen size has been described. However, a video signal after MPEG decoding, such as a jacket picture used in MPEG, is already used. Even when the size of the sub-screen does not need to be reduced, that is, when the frequency of the synchronization clock and the frequency of the sub-screen synchronization clock are equal and the overtaking phenomenon does not occur, the configuration of each embodiment has an element that hinders the display operation. There is no. For this reason, it is not necessary to switch the circuit operation even when, for example, switching from reduced display to equal-size display.

In the case where the sub-screen synchronization clock has a higher frequency, and it is desired to perform writing after reading, the sub-screen synchronization clock frequency and the master screen synchronization clock are calculated according to the ratio of the sub-screen display size to the full-screen display size. By multiplying the frequency ratio and subtracting the value subtracted from the sub-screen display end position as the offset amount, the same effect as in the above-described embodiments can be obtained.

Each of the above embodiments is an example of application to a multi-picture system requiring a field memory for the entire picture or a jacket picture system. Two types of video signal input signals conventionally used in TVs and the like are used. Picture-in-Picture (PinP), which fits one video (child screen) into a part of the other video (parent screen)
A case where the present invention is applied to a decoder will be described as a fourth embodiment with reference to FIG.

The screen control circuit shown in FIG. 8 includes small screen field memories 801 and 802, a small screen write address generation circuit 803, and a small screen read address generation circuit 80.
4. Parent screen synchronization separation circuit 805, MPEG decoder for child screen 806, offset circuit 807, and switch 80
8,809.

The parent screen synchronization separation circuit 805 outputs a synchronization clock 805c having the same frequency as the sampling frequency synchronized with the screen, a field pulse 805a synchronized with the synchronization clock 805c, and a field discrimination signal 805b.

The offset circuit 807 has a synchronous clock 8
05c, a field pulse 805a, and a small-screen display position 800a given from the outside, an offset field pulse 807a is output.

Receiving the offset field pulse 807a, the sub-screen MPEG decoding section 806 outputs a compressed video signal 806a obtained by compressing the video signal as a sub-screen, a data discrimination signal 806b synchronized with the compressed video signal 806a, and a sub-screen synchronization clock 806c. .

Sub-picture write address generation circuit 803
Receives an offset field pulse 807a and a small screen synchronization clock 806c, and inputs a memory write address (WADR) 803a and a write enable (WE).
803b is generated and output.

A write enable 803b and a data discrimination signal 806b are input from the write enable 803b, and each of the field memories 801 and 801b is formed by a logic circuit composed of two AND circuits and one inverter.
WE1 and WE2 for selectively selecting one of the 802s are generated and output to the field memories 801 and 802.

The read address generation circuit 804 receives the field pulse 805a and the synchronous clock 805c, and inputs a memory read address (RADR) 804a.
And a read enable (RE) 804b are generated and output.

The read enable 804b receives the read enable 804b, a small screen display period 800b which is a signal indicating a small screen display period supplied from the outside, and a field discrimination signal 805b, and receives two AND circuits and one inverter. Are generated, and RE1 and RE2 for selectively selecting one of the field memories 801 and 802 are generated and output to the field memories 801 and 802. The field discrimination signal 805b is also supplied to a switch 808 for selecting a readout output of each field memory, whereby the readout field memory is selected and output as a small-screen video signal 800d.

The compressed video signal 806a is supplied to the field memories 801 and 802,
01 and 802, the compressed video signal 806a is written to the memory write address 803a to which WE1 and WE2 are input.

On the other hand, the field memory is read from the read address 804a of the memory to which RE1 and RE2 have been input, output from the switch 808, and output to the switch 809 as a small-screen video signal 800d. The switch 809 has a small screen video signal 80
0d and a main screen video signal 800c supplied from outside
Are selected, and one of them is selected according to the small-screen display period 800b and output to the outside as a video signal 800e.

To summarize the above-mentioned circuit configuration, the compressed video signal 806a is obtained by writing the memory write address (WA) output from the write address generation circuit 803 based on the offset field pulse 807a and the small-screen display position 800a.
DR) 803a, write enable (WE) 803b
And a data discrimination signal 806b from the MPEG decoding unit 806
Field memory 801 having a memory for one field of the child screen, or the field memory 8
02 is written.

On the other hand, reading from the field memories 801 and 802 is performed by reading the read address (RAD) output from the small-screen read address generating circuit 804 in response to the field pulse 805a from the main screen synchronization separating circuit 805.
R) 804a and read enable (RE) 804b
This is performed according to the conditions of the sub-screen display period 800b and the field determination signal 805b from the parent screen synchronization separation circuit 805 and the display.

The operation of the present embodiment configured as described above will be described with reference to a timing chart shown in FIG.

FIG. 9 is a diagram showing timings when the full screen display time and the sub-screen field memory writing time are V, the sub-screen display start time is B1, and the end time is B2. Reading of the small-screen field memory is started when the display time reaches B1, and ends at time B2.

On the other hand, writing to the small-screen field memory starts when the offset time corresponding to the small-screen display position, that is, when the display time reaches B1, and ends after the lapse of V time.

In the method of this embodiment, as can be seen from FIG.
READ and WRITE do not cross. Therefore, the reading does not overtake the writing, and the relationship among the data discrimination signal 806b, the feed discrimination signal 805b, the compressed video signal 806a, and the small-screen video signal 800d is the same as in FIG. 3, and the image quality does not deteriorate. The object of the invention is achieved.

Next, a description will be given of a fifth embodiment of the present invention, in which the same effects as those of the fourth embodiment shown in FIG. 8 are obtained, with reference to FIG.

In this embodiment, the small-screen field memory 10 is used.
01, 1002, parent screen sync separation circuit 1005, sub-screen MPEG decoding section 1006, offset circuit 1007,
It is composed of switches 1008 and 1009.

The parent screen sync separation circuit 1005 outputs the field pulse 1005a to each child screen field memory 100.
1, 1002 and the offset circuit 1007,
Synchronous clock 1005c is stored in each sub-screen field memory 1
001, 1002, an offset circuit 1007, and a small picture MPEG decoding unit 1006, and a field discrimination signal 1005b.

The offset circuit 1007 includes, in addition to the field pulse 1005a and the synchronous clock 1005c,
Input the sub-screen display position 100a supplied from the outside,
An offset field pulse 1007a is generated and output to each of the small picture field memories 1001 and 1002, the offset circuit 1007, and the small picture MPEG decoding unit 1006. The same amount of offset as the small picture display position 1000a is added to the field pulse 1005a. And outputs it as an offset field pulse 1007a.

The small-screen MPEG decoding section 1006 outputs a compressed video signal 1006a obtained by compressing a video signal as a small screen, a data discrimination signal 1006b synchronized with the compressed video signal 1006b, and a small-screen synchronization clock 1006c based on the offset field pulse 1007a. .

Child screen field memories 1001, 100
2 is address write pointer reset (RSTW)
, The write address is reset to the initial value 0, and the address read pointer reset (RSTR)
, The read address pointer is reset to the initial value 0, and the write enable signals (WE1, WE
When the sub-screen synchronization clock is input when 2) is active, the write address pointer is incremented. When the synchronization clock 1005c is input when the read enable signals (RE1, RE2) are active, the read address is read. The pointer is incremented.

[0077] Child screen field memories 1001, 100
2, an offset field pulse 1007a is input to reset the address write pointer, and the data enable signal (WE1, WE2) is the data discrimination signal 10
06b is selectively input by way of one through an inverter. A field pulse 1005a is input to the read address pointer, and a field determination signal 1005b and a small screen display period 100b are input to the read enable signals (RE1, RE2).
Each sub-screen field memory 1001, 10 is constituted by a logic circuit composed of one AND circuit and one inverter.
WE1 and WE2 for selecting either one of 02 are generated and output to the field memories 1001 and 1002. The field discrimination signal 1005b is supplied to the switch 10 for selecting the read output of each sub-screen field memory.
08, the read-out field memory is selected and output to the switch 1009 as a small-screen video signal 1000d. Switch 1009
, A parent screen video signal 1000c supplied from the outside in addition to the child screen video signal 1000d, and one of these is selected during the child screen display period 1000b and output to the outside as the video signal 1000e. .

FIG. 11 is a diagram showing the operation timing of this embodiment. As shown in FIG.
5a resets the read memory address,
Except that the write memory address is reset by the offset field pulse 1007a, the operation is the same as that of the fourth embodiment shown in FIG. 8, and the same effect is obtained. Moreover, in this embodiment, the auto
The use of the increment type memory also has the effect of reducing the number of address generation circuits and address lines.

[0079]

Since the present invention is configured as described above, it has the following effects.

Since the writing timing to the field memory has an offset corresponding to the display of the small screen, the phenomenon that the field memory reading overtakes the field memory writing does not occur. Since the field image data is output during the first field scan and the second field image data is output during the second field scan, the overtaking phenomenon can be prevented without deteriorating the image quality, and the image can be faithfully reproduced. There is an effect that can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a multi-screen control circuit according to the present invention.

FIG. 2 is a diagram showing a configuration of an offset circuit 107 in FIG.

FIG. 3 is a timing chart showing an operation of the embodiment shown in FIG. 1;

FIG. 4 is a diagram showing a relationship between reading and writing of each of the field memories 101 and 102 in the embodiment shown in FIG.

FIG. 5 is a diagram showing a main configuration of a second embodiment of the present invention.

FIG. 6 is a circuit block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of a subtraction circuit 607 in FIG. 6;

FIG. 8 is a circuit block diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 9 is a timing chart showing an operation of the embodiment shown in FIG. 8;

FIG. 10 is a circuit block diagram showing a configuration of a fifth example of the present invention.

11 is a timing chart showing the operation of the embodiment shown in FIG.

FIG. 12 is a block diagram showing a configuration of a conventional example.

FIG. 13 is a block diagram showing a configuration of a conventional example.

14A and 14B are diagrams showing operation timings of the circuit shown in FIG. 12, and FIG. 14A is a timing chart in a normal operation;
(B) is a timing chart when image quality deteriorates.

FIG. 15 is a diagram for explaining an overtaking phenomenon.

FIG. 16 is a diagram for explaining an overtaking phenomenon.

[Explanation of symbols]

100a, 600a, 800a Small screen display positions 101, 102, 601, 602 Field memories 103, 603 Write address generation circuits 103a, 603a, 803a WADR 103b, 603b, 803b WE 104, 604 Read address generation circuits 104a, 604a, 804a RADR REs 104, 604b, 804b REs 105, 605 Synchronization separation circuits 105a, 807a, 1007a Field pulses 105b, 605b, 805b, 1005b Field discrimination signals 105c, 605c, 805c, 1005c Synchronous clocks 106, 606 MPEG decoders 106a, 606a, 806a, 1006a Compressed video signal 106b, 606b, 806b, 1006b Data discrimination signal 106c, 606c, 806c, 006c child screen synchronized clock 107,807,1007 offset circuit 107a, 807a, 1007a offset field pulse 108,608,808,809,1008,1009
Switch 109, 509, 709 Timing adjustment circuit 110 Comparator 111 Counter 507 Delay means 510 Delay amount control circuit 511 Delay circuit 605a Vertical line count value 607 Subtraction circuit 607a Offset vertical line count value 710 Subtractor 800b, 100b Child screen display period 800c , 100c Main screen video signal 800d, 100d Small screen video signal 800e, 1000e Video signal data output 803 Small screen write address generation circuit 805, 1005 Main screen sync separation circuit 806, 1006 MPEG decoding unit for small screen 801, 802, 1001, 1002 inset screen field memory

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-10-4526 (JP, A) JP-A-8-146942 (JP, A) JP-A-5-122603 (JP, A) JP-A 64-64 46375 (JP, A) JP-A-6-90414 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/45 H04N 5/262-5/265

Claims (8)

(57) [Claims] 1. A sync separation circuit for outputting a field pulse synchronized with a main screen and a field discrimination signal indicating whether the main screen is a first field or a second field, and a first field and a second field of a sub-screen. A first field memory and a second field memory provided corresponding to a field; inputting the field pulse and a sub-screen display position supplied from the outside; An offset circuit for outputting as an offset field pulse to which a corresponding offset amount has been added, and decoding of a video signal based on the offset field pulse, and indicating whether the decoded child picture is a first field or a second field. An MPEG decoding unit for outputting a data discrimination signal; Readout memory selecting means for supplying a readout address to a field memory provided for the field indicated by the field discrimination signal based on the offset pulse, and for the field indicated by the data discrimination signal based on the offset field pulse. And a write memory selecting means for supplying a write address to a field memory provided. 2. The multi-screen control circuit of an MPEG decoder according to claim 1, wherein the synchronization separation circuit outputs a synchronization clock synchronized with the main screen, the offset circuit is reset by a field pulse, and counts up by the synchronization clock. A counter for inputting a sub-screen display position indicating the display position of a sub-screen supplied from the outside and the field pulse, and adjusting the timing of the sub-screen display position by the field pulse; and the counter A multi-screen control circuit of an MPEG decoder comprising a comparator which outputs an offset field pulse when the output of the sub-screen and the value of the sub-screen display position subjected to the timing adjustment by the field pulse in the timing adjustment circuit match. 3. A sync separation circuit for outputting a field pulse synchronized with the main screen and a field discrimination signal indicating whether the main screen is the first field or the second field; and a first field and a second field of the sub-screen. A first field memory and a second field memory provided corresponding to a field; inputting the field pulse and a sub-screen display position supplied from the outside; Delay means for outputting as an offset field pulse to which a corresponding offset amount is added, decoding of a video signal based on the offset field pulse, and indicating whether the decoded child picture is the first field or the second field. An MPEG decoding unit for outputting a data discrimination signal; Readout memory selecting means for supplying a readout address to a field memory provided for a field indicated by the field discrimination signal based on the offset field pulse; And a write memory selecting means for supplying a write address to a field memory provided. 4. The multi-picture control circuit of an MPEG decoder according to claim 3, wherein the delay means gives a predetermined amount of delay to the field pulse and outputs it as an offset field pulse; A timing adjustment circuit for inputting a sub-screen display position indicating the display position of the sub-screen and a field pulse value, and outputting a delay amount determined by the sub-screen display position at a timing indicated by the field pulse; and A delay amount control circuit for controlling the delay circuit so as to obtain the delay amount obtained at the output of the timing adjustment circuit.
Multi-screen control circuit for PEG decoder. 5. A sync separation circuit for outputting a vertical line count value synchronized with the main screen and a field discrimination signal indicating whether the main screen is the first field or the second field; A first field memory and a second field memory provided corresponding to a second field; inputting the vertical line count value and a sub-screen display position supplied from the outside; A subtraction circuit for outputting as an offset vertical line count value to which an offset amount corresponding to the timing to be added is provided, and a video signal is decoded based on the offset vertical line count value, and the decoded child screen is composed of a first field and a second field. An MPEG decoding unit that outputs a data discrimination signal indicating which of the fields Read memory selecting means for supplying a read address to a field memory provided for a field indicated by the field discrimination signal based on the vertical line count value; and the data discrimination signal based on the offset vertical line count value. And a write memory selecting means for supplying a write address to a field memory provided for the field indicated by.
Multi-screen control circuit for decoder. 6. The multi-screen control circuit of an MPEG decoder according to claim 5, wherein the subtraction circuit inputs a sub-screen display position indicating a display position of the sub-screen and a vertical line count value supplied from the outside. A timing adjustment circuit for outputting the subtraction amount determined by the screen display position at the timing indicated by the vertical line count value; and an offset vertical line count by subtracting the subtraction amount sent from the timing adjustment circuit from the vertical line count value. A multi-screen control circuit of an MPEG decoder comprising a subtractor for generating a value. 7. A main screen sync separation circuit for outputting a field pulse synchronized with the main screen and a field discrimination signal indicating whether the main screen is the first field or the second field; A first field memory and a second field memory provided corresponding to the second field, and the field pulse and a sub-screen display position supplied from outside are input, and a sub-screen in the main screen is displayed. An offset circuit for outputting an offset field pulse to which an offset amount corresponding to a timing is added; a decoding of a video signal of the child screen based on the offset field pulse; and a decoding of the decoded child screen in either the first field or the second field. Output a data discrimination signal indicating whether the Readout memory selecting means for supplying a readout address to a field memory provided for a field indicated by the field discrimination signal, based on the field pulse and a sub-screen display period supplied from the outside, A multi-screen control circuit for an MPEG decoder, comprising: write memory selection means for supplying a write address to a field memory provided for a field indicated by the data discrimination signal based on a field pulse. 8. A main screen synchronization separation circuit for outputting a field pulse and a synchronization clock synchronized with the main screen and a field discrimination signal indicating whether the main screen is the first field or the second field; A first field memory and a second field memory provided corresponding to the first field and the second field, and the field pulse and a sub-screen display position supplied from outside are input. An offset circuit for outputting as an offset field pulse to which an offset amount corresponding to a displayed timing is provided, and a video signal of a child screen is decoded based on the offset field pulse, and the decoded child screen is in the first field or the second field. Data discrimination signal and sub-screen indicating which of the fields A sub-screen MPEG decoding unit that outputs a sub-screen synchronization clock synchronized with the field pulse, and a field memory provided for a field indicated by the field discrimination signal based on the field pulse and a sub-screen display period supplied from outside. Read memory selection means for supplying a read enable, wherein the first field memory and the second field memory reset the write address to an initial value 0 by the offset field pulse input to the address write pointer reset. The read address pointer is reset to an initial value 0 by the field pulse input to the address read pointer reset,
When the sub-screen synchronization clock is input while the data determination signal input as the write enable signal is active, the write address pointer is incremented, and the output of the read memory selection means input as the read enable signal becomes active. A multi-screen control circuit for an MPEG decoder, wherein a read address pointer is incremented when a synchronous clock is input.