JP3423327B2 - Video signal input / output device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal input / output device for converting a video signal into an input video signal and outputting the converted video signal.

[0002]

2. Description of the Related Art When an image is embedded in another image and synthesized, for example, as shown in FIG.
NTSC and HD, such as when embedded in the image of
Since the frame frequency of TV is different (NTSC: 29.
(97 Hz, HDTV: 30.0 Hz) In the NTSC input / HDTV output frame synchronizer 1 configured with one frame memory, the NTSC image is temporarily stored in the frame memory by the writing control means 2 synchronized with the NTSC sync signal. On the other hand, it is necessary to read from the frame memory by the read controller 3 synchronized with the HDTV sync signal.

At this time, the access operation of the frame memory is synchronized with the output image signal for reading, and is synchronized with the input image signal for writing, and the reading and writing operations are completely independent operations. When the difference in frame frequency is used as the repetition frequency, overtaking occurs at the read and write addresses of the frame memory. When this overtaking occurs, the old frame and the new frame are displayed at the same time in the one-frame reading screen, and when the moving image signal is input, the boundary between the old frame image and the new frame image is displayed in the output screen. It occurred, and it became an unnatural screen like the NTSC composite screen in FIG.

FIG. 9 illustrates this phenomenon by using arrows to indicate the read and write addresses of the frame memory, which change over time. The old frame and the new frame of the input image signal will be read. A method for avoiding this overtaking phenomenon is disclosed in Japanese Patent Laid-Open No. 64-36174, in which "198 is a method for removing this overtaking phenomenon.
As shown in Proposal 7-7 of the 6th National Congress of the Television Society of Japan, a method of using an image memory for four fields has been proposed. In this method, the video signal 1 is sequentially written into a memory in units of four fields, and read from a field memory in which no writing is performed. Is disclosed.

[0005]

However, the above method has a problem that the cost is high because a large amount of memory is required.

The present invention has been made in view of the above points. It requires a small amount of image memory, and it can be converted into a video signal of a different cycle without being overtaken and output. An object is to provide an output device.

[0007]

[Means and Actions for Solving the Problem] Claims of the present invention
The video signal input / output device according to item 1 ,
More first video signal that can be displayed is input, a first and a first memory means for storing the video signal, the first of the said video signal input to the memory means first being the input
A write control means for writing control to the first memory means based on the synchronization signal, low video signal input
Second memory means for storing at least one frame, and the first video signal stored in the first memory means under the write control by the write control means ,
Transfer means in synchronization with the serial first synchronization signal written is transferred to the second memory means, said first video signal stored in said second memory means, said first synchronizing signal and Is a display hand that displays with a second synchronization signal with a different frequency
The second synchronization signal for displaying as an image on the column.
And read control means for reading the screen period is different second video signal by said first synchronizing signal based on the time difference between said second synchronizing signal, the first synchronizing signal and the second synchronization signal Overtaking with the transfer by the transfer means
An overtaking detection unit that detects a frame that occurs in advance, and a frame in which the overtaking occurs based on the detection of the occurrence of an overtaking by the overtaking detection unit .
The transfer timing of the transfer means is set to the
For the first synchronization signal so that the transfer timing comes
And a transfer control means for controlling so that the transfer timing is delayed by a predetermined time. When the occurrence of overtaking is detected due to the time difference between the synchronization signals, the transfer timing is delay controlled. In addition, claim 2 of the present invention
Video signal output device can be displayed by the first synchronization signal
First video signal is input, and the input first video is input.
First memory means for storing a signal, and said first memory
The video signal input to the means to the first synchronization signal
Writing control for writing to the first memory means based on
Embedded control means and at least one video signal input.
Second memory means for storing an amount of memory, and the write control means
Storing in the first memory means by write control by
The first synchronized video signal is read, and the first synchronization is performed.
Transfer to the second memory means and write in synchronization with the signal
Transfer means, and the storage means stored in the second memory means.
The first video signal has a frequency higher than that of the first synchronization signal.
As an image on the display means for displaying the number of second synchronization signals.
Screen is displayed by the second synchronization signal in order to display
Read control means for reading as a second video signal having a different period
And the time between the first synchronization signal and the second synchronization signal
The first synchronization signal of the second synchronization signal based on the difference.
Overtaking for an issue occurs during transfer by the transfer means
Overtaking detection means for detecting the frame to be detected in advance,
Based on detection of occurrence of overtaking by the overtaking detection means
Then, the transfer in the frame in which the overtaking occurs
The transfer timing of the means is set with respect to the first synchronization signal.
By delaying for a fixed time, the second memory means
The stored frame before the overtaking occurs
The read control means controls the video signal to be read.
And a transfer control means.
Therefore, the occurrence of overtaking is detected due to the time difference between the sync signals.
The transfer timing is delayed and controlled. Furthermore, this
The video signal output device according to claim 3 is the input device.
First video signal that can be displayed by the first synchronization signal
Is a video signal of the resolution of NTSC system,
The second video signal read by the control means is HDT
It is characterized in that the video signal has a V-system resolution.

[0008]

Embodiments of the present invention will be specifically described below with reference to the drawings. 1 to 6 relate to a first embodiment of the present invention, FIG. 1 is a schematic configuration diagram of a video display device including a frame synchronizer as a video input / output device of the first embodiment, and FIG. 2 is a block of the frame synchronizer. Diagram,
FIG. 3 is an operation explanatory diagram, FIG. 4 is a specific configuration diagram of the frame synchronizer, and FIGS. 5 and 6 are operation explanatory diagrams of FIG.

As shown in FIG. 1, the video display device 11 having the first embodiment has a frame frequency of 29.97H, for example.
a first video signal processing device 12 that outputs an NTSC video signal of z, and an HD with a frame frequency of 30.0 Hz, for example.
A second video signal processing device 13 that performs signal processing for displaying a (HDTV) screen on a TV video signal, and is interposed between these two video signal processing devices 12 and 13.
The frame synchronizer 14 as the video signal input / output device of the first embodiment converts the NTSC video signal into an HDTV video signal and outputs it to the second video signal processing device 13.

The first video signal processing device 12 outputs a digital video signal having a frame frequency of 29.97 Hz from its output end to the video input end of the frame synchronizer 14. The first synchronizing signal input terminal of the frame synchronizer 14 is connected to the NTS from the first video signal processing device 12.
The C sync signal Vsyn 1 is input.

The video output end of the frame synchronizer 14 is connected to the video input end of the second video signal processing device 13, and the second synchronizing signal input end is connected to the HDTV from the second video signal processing device 13. The synchronization signal Vsyn 2 is input. An HDTV video signal having a frame frequency of 30.0 Hz is output from the video output terminal of the frame synchronizer 14, that is, the input video signal having a frame frequency of 29.97 Hz is converted into a video signal having a frame frequency of 30.0 Hz. Output.

FIG. 2 is a block diagram showing the structure of the frame synchronizer 14 of the first embodiment. First image signal output from the video signal processing device 1 2 (video signal)
Is input to the first memory means 21 as an input image signal to the frame synchronizer 14. The writing of the image signal input to the first memory means 21 is controlled by the first memory means write controller 22 in the first memory means 21. The writing control by the first memory means write controller 22 is performed in synchronization with the synchronizing signal Vsyn 1 of the image signal.

The image signal written in the first memory means 21 is read by the memory transfer controller 23,
It is written in the second memory means 24. The image signal written in the second memory means 24 is read by the second memory means read controller 25, and the second synchronization signal Vsyn is read.
The image signal synchronized with 2 is the frame synchronizer 1
4 becomes the output image signal, and the second video signal processing device 13
Entered in.

The two synchronizing signals Vsyn 1 and Vsyn 2 are input to the input / output synchronizing signal time difference detecting means (abbreviated as time difference detecting means) 26, and the two synchronizing signals Vsyn 1 and Vsy.
The time difference between n 2 is detected and it is determined whether or not it is a time difference in which overtaking occurs, and a time difference determination signal (time difference detection signal) corresponding to the presence or absence of overtaking is output to the memory transfer controller 23. Further, the synchronization signal Vsyn 1 is input to the first memory means write controller 22 and the memory transfer controller 23 and used for timing control of write control and read control of the first memory means 21.

The synchronization signal Vsyn 2 is also input to the second memory means read controller 25, and the second memory means 2 is read.
4 is used for timing control of read control. The first memory means write controller 22 synchronizes the input image signal with the first image signal in synchronization with the input synchronization signal Vsyn 1.
Write in the memory means 21. The second memory means read controller 25 also reads the image signal written in the second memory means in synchronization with the input synchronizing signal Vsyn2.

The memory transfer controller 23 changes the timing of transferring the image data from the first memory means 21 to the second memory means 24 according to the time difference determination signal detected by the time difference detecting means 26. That is, usually the first
At the same cycle as the vertical synchronization signal Vsyn1 to which the data transfer start from the memory means 21 to the second memory means 24 is also input,
Do it regularly. Then, the time difference between the synchronizing signal Vsyn 2 associated with the image signal output from the second memory means 24 and the vertical synchronizing signal Vsyn 1 associated with the input image signal exceeds the read and write addresses for the second memory means 24 (both addresses For a frame in which an (intersection) occurs, the transfer start timing is delayed so that overtaking does not occur.

FIG. 3 shows an explanatory diagram of the above operation, and FIG.
(A) and FIG. 3 (c) show synchronization signals Vsyn 1 and Vsy, respectively.
n 2 (indicated by negative logic) and two synchronization signals V
When the time difference between the timings syn1 and Vsyn2 does not cause overtaking, the image data transfer to the second memory means 24 is performed with the synchronization signal Vsyn1 of the input image signal as shown by the solid line in FIG. 3 (b). Do it synchronously. In FIG. 3B, the dotted line shows the state of reading from the second memory means 24, and image data corresponding to the image from the upper left point α to the lower right point β of the input screen shown in FIG. 3D. The second memory 24
The time change of the address when reading from is shown.
The reading from the second memory means 24 is always performed with the synchronization signal V
Synchronized with syn 2.

On the other hand, two synchronization signals Vsyn 1 and Vsyn 2
When the time difference between the timings is small and the time difference signal is determined to be overtaking, the memory transfer controller 23 delays the transfer start timing so that overtaking of the read address and the write address does not occur (Fig. 3, the transfer timing is delayed in the nth frame).

In other words, in the present embodiment, the start of transfer of a new frame is delayed compared to the usual case in comparison with a frame in which overtaking has occurred in the past, so that only the old frame of the input image signal is read out and the old and new frames are transferred to one frame. It is possible to prevent one frame from being partially displayed.

The capacity of the second memory means 24 is required for one frame of the input image signal, and the capacity of the first memory means 21 is enough to store the input image signal data written during the maximum delay time of the transfer start. Is required at the minimum, and since all the frames of the input image signal must be sequentially transferred to the second memory means 24 due to the nature of the frame synchronizer 14, it can be seen that a maximum of one frame is required.

The minimum transfer start delay time required to avoid overtaking is that the arrows indicating the read and write operations of the second memory means 24 in FIG. 3 should not intersect. This is the difference between the read time and the write time of the second memory means 24. FIG. 4 shows a specific configuration of the first embodiment. In this case, the input image signal is non-interlaced and the output image signal is also non-interlaced.

An analog input image signal is A / D converted by an A / D converter 31 and then applied to an input end of a FIFO memory (first-in first-out memory) 32, which is controlled by the FIFO controller 33.
It is written in the IFO memory 32. This writing is FIF
This is performed in synchronization with the horizontal and vertical synchronization signals Hsyn 1 and Vsyn 1 input to the O controller 33.

The image data written in the FIFO memory 32 is transferred to the dual port D-RAM frame memory 35 under the control of the D-RAM controller 34. The image data transferred to the frame memory 35 is read by a serial clock synchronized with the synchronizing signal Vsyn 2, converted into an analog image signal by the D / A converter 36, and output.

The vertical synchronizing signal Vsyn 1 is input to the timing generator 37 to generate two kinds of pulses, that is, a normal pulse H and a delay pulse I, which are applied to the two input / output terminals of the selector 38. One of these two types of pulses H and I is selected by the select signal J to the selector 38 and becomes the transfer start signal L, which is applied to the D-RAM controller 34.

The D-RAM controller 34 transfers the image data by the transfer start signal L, and when the transfer of the image data for one frame is completed, the transfer end signal K is applied to the clock input terminal of the flip-flop 39. . With this signal K, the flip-flop 39 outputs the select signal J according to the state of the time difference detection signal M of the time difference detection circuit 40 applied to the input terminal D.

The synchronization signal Vsyn 1 is input to the pulse generator 41 which constitutes the time difference detection circuit 40, and outputs the pulse N to the input terminal D of the flip-flop 42 at the same cycle as the synchronization signal Vsyn 1. This flip-flop 4
The synchronization signal Vsyn 2 is applied to the clock input terminal of 2,
The pulse N is latched at the rising edge of the synchronization signal Vsyn 2 and the time difference detection signal (time difference determination signal) M of “H” or “L” is output to the flip-flop 39.

This signal M is sent from the FIFO memory 32 to the frame memory 35 formed by the dual port D-RAM.
When the data transfer to the frame memory 35 is started by the normal pulse H which is not delayed, there is a time difference such that the read and write addresses of the frame memory 35 are overtaken and the "H" is generated.
For example, the timing and pulse width of the pulse N are set so that The D-RAM controller 34 is also applied with horizontal and vertical synchronization signals Hsyn 2 and Vsyn 2.

Next, this operation will be described below with reference to FIG. 5A and 5B show two synchronization signals Vsyn 1 and Vsyn 2 as in FIG. A / D converter 31
The image data converted by the above is input horizontal and vertical synchronizing signals Hsyn 1, Vsy under the control of the FIFO controller 33.
The data is sequentially written in the FIFO memory 32 in synchronization with n 1.
The vertical synchronizing signal Vsyn 1 is applied to the timing generator 37, and the normal pulse H synchronized with the rising edge of the synchronizing signal Vsyn 1 and the delayed pulse I delayed are shown in FIG.
It is output as shown in (e).

The pulse N of the pulse generator 42 is output as shown in FIG. 5 (j) at the same cycle as the synchronizing signal Vsyn 1, and this pulse N is applied to the clock input terminal of the flip-flop 42. By being latched at the rising edge of the signal Vsyn 2, the "L" or "H" time difference detection signal M is generated as shown in FIG. 5 (i). When this signal M is "L", it means that there is a time difference that does not cause overtaking during the next transfer operation, and when it is "H", it passes during the next transfer operation. Corresponds to a time difference that occurs. This signal M is input to the flip-flop 39, is latched by the transfer end signal K shown in FIG. 5 (g), becomes the select signal J shown in FIG. 5 (f), and is input to the selector 38.

When the time difference detection signal M is "L",
That is, when a time difference that does not cause overtaking is detected, the select signal J becomes "L", and the selector 38 sets the normal pulse H to D as the transfer start signal L shown in FIG.
-Output to the RAM controller 34. In synchronization with this transfer start signal L, the D-RAM controller 34 operates as shown in FIG.
When the transfer is started and transferred to the final address as shown by the solid line in (b), the transfer end signal K is output to the flip-flop 39, and the select signal J of the selector 38 is careless until the signal K is output. To be switched to.

When the time difference between the two synchronization signals Vsyn 1 and Vsyn 2 approaches and a time difference occurs in which an overtaking occurs during the image transfer of the next one frame, the time difference detection signal M becomes "H", and after this timing. By the transfer end signal K,
When this state is detected, the select signal J becomes "H" as shown in FIG. 5 (f), and the delay pulse I is transferred to the transfer start signal L.
To the D-RAM controller 34.

Therefore, the D-RAM controller 34
In synchronism with the delay pulse I, the transfer is started at a timing delayed as compared with the normal case as shown by the solid line in FIG. 5B, and an overtaking occurs during the transfer without delay. Prevent from happening. If the time difference detection signal M is "L" at the timing when the transfer in synchronization with the delay pulse I is completed, the select signal J becomes "L" again and the normal pulse H is output to the D-RAM controller 34 as the transfer start signal L. It will be.

Each horizontal synchronizing signal Hs shown in FIG.
As shown in FIG. 6A, the D-RAM is synchronized with yn2.
Memory processing is performed by the controller 34. D-R
AM refresh, D-RAM shift register transfer, F
Processing such as transfer from the IFO memory 32 to the dual port D-RAM frame memory 35 is performed by the horizontal synchronization signal Hsy.
It is performed in synchronization with n2. That is, these memory processes are performed in one horizontal synchronization section.

For example, in D-RAM refresh, CAS (column address strobe) which becomes "L" in synchronization with the horizontal synchronizing signal Hsyn2 as shown in FIG. 6 (d).
After that, the RAS (row address strobe) shown in FIG. 6D is set to "L", and the refresh method of CAS before RAS is performed. Note that FIG.
(E) shows a serial clock.

As a result of the above operation, in the case of data transfer timing without delay from the FIFO memory 32 to the dual port D-RAM frame memory 35, there is overtaking between the read and write addresses of the dual port D-RAM frame memory 35. Time-difference detection circuit 4 that indicates that something happens
From the time difference detection signal M from 0, the data transfer start timing from the FIFO memory 32 to the dual port D-RAM frame memory 35 is determined for each vertical synchronization (blanking) signal of the output image signal. As a result, the reading of the dual port D-RAM frame memory 35 and the passing of the write address are always avoided.

According to the frame synchronizer 14 of the first embodiment, it is possible to perform the frame synchronizing operation of the non-interlaced input image signal / non-interlaced output image signal. Regarding the memory, the FIFO memory 32 has a maximum capacity of one frame of the input image signal, and the dual port D-RAM frame memory 35 has a capacity of one frame.

Further, since the first memory means is added in the preceding stage of the second memory means, it is not necessary to make the rate of the input image signal and the writing rate of the second memory means the same, and the degree of design freedom is increased. Can be large. Figure 7
Shows a second embodiment of the present invention, which shows a frame synchronizer 51 for interlaced input / output image signals.

In this embodiment, the field signal F1 constitutes the first flip-flop 53 which constitutes the time difference detection circuit 52.
Input to the first flip-flop 53 and the second flip-flop 53
The pulse of the pulse generator 41 is applied to the flip-flop 54. The outputs of the two flip-flops 53 and 54 are input to the AND gate 56 via the EX-NOR circuit 55 together with the output of the pulse generator 41. The output of the AND gate 56 is input to the flip-flop 42.

The field signal F1 is input to the flip-flop 57, the output of the flip-flop 57 is input to the next-stage flip-flop 58, and the output of the flip-flop 58 is the D-RAM controller 3.
4 is input. Also, the second field signal F2 is D
It is input to the RAM controller 34 and also to the second flip-flop 54 forming the time difference detection circuit 52. The other structure is the same as that of the first embodiment shown in FIG. 4, and the same components are designated by the same reference numerals and the description thereof will be omitted.

The operation of the second embodiment is not much different from that of the first embodiment, and will be briefly described.
Since data is stored in the IFO memory 32 on a field-by-field basis, the flip-flop 57 is used as a logic for confirming the match / mismatch of the field surface signal of the data stored in the FIFO memory 32 and the field surface of the output image signal. 58 or flip-flops 53, 54
In the case of the second embodiment, the condition for delaying the transfer timing of the frame memory more than usual is that the time (phase) of the input / output vertical synchronization signal is the same as in the first embodiment. In addition to the difference, this is the case when the field surface of the display screen matches the field surface to be transferred. As a result, reading of the frame memory and overtaking of the write address are always avoided.

The frame synchronizer 51 according to the second embodiment can perform a frame synchronizing operation for interlaced input image / interlaced output image signals. Regarding the memory, the FIFO memory 32 has a maximum capacity of one field of the input image signal and the dual port D-RAM frame memory 35 has a capacity of one frame.

Further, as in the first embodiment, by providing the two memory means, the image signals written in the first memory means can be transferred at the same rate to the second memory means. Is unnecessary, and the degree of freedom in design can be increased.
Further, the transfer delay time width required for overtaking prevention is also changed by changing the transfer rate by the memory interleaving of the first memory means and the second memory means to bring the read rate and the transfer rate of the second memory means close to each other. The present system can be configured even with the first memory means having a smaller size and a smaller capacity.

In addition to these embodiments, the frame synchronizer for interlaced input image signal / non-interlaced output image signal and non-interlaced input image signal / interlaced output image signal can be similarly implemented. NTS
It is of course possible to handle not only the C or HDTV image signal or image signal but also other image (image) signals. Furthermore, this time, an example of a frame synchronizer was given, but the input image signal is used as it is, thinned out, or data obtained by distributing one identical data to a plurality as a child screen signal and an output image synchronization signal as a parent screen synchronization signal. Of course, it does not matter if the picture-in-picture is used without overtaking.

[0044] Incidentally, in the above embodiment, the time difference or phase difference between the two synchronization signals, with respect to the frame or field overtaking occurs by changing the writing rate (speed) to the second memory means ( for example reading speed is greater than the writing speed, etc. to writing speed twice) may be additionally have over does not occur.

[0045]

As described above, according to the present invention, in addition to the second memory means, the first memory means is provided in the front stage, and the first memory means is provided.
Since the transfer start timing from the memory means of the second memory means to the second memory means is changed according to the phase difference or the time difference of the two synchronization signals, the read and write addresses in the second memory means can be overtaken. It is possible to obtain a natural image that is avoided and always has no boundaries.

Further, by providing the two memory means, it is possible to increase the degree of freedom in designing the video signal input / output device in which overtaking does not occur.

[Brief description of drawings]

FIG. 1 is a schematic view showing an entire apparatus including a synchronizer of the present invention.

FIG. 2 is a block diagram showing a configuration of a frame synchronizer of the first embodiment.

FIG. 3 is an operation explanatory diagram of FIG. 2;

FIG. 4 is a specific configuration diagram of the frame synchronizer of the first embodiment.

5 is a timing chart for explaining the operation of FIG.

FIG. 6 is an operation explanatory diagram of FIG. 4;

FIG. 7 is a specific configuration diagram of a frame synchronizer according to a second embodiment of the present invention.

FIG. 8 is a schematic configuration diagram of a conventional example.

FIG. 9 is an operation explanatory diagram of a conventional example.

[Explanation of symbols]

11 ... Video display device 12 ... First video signal processing device 13 ... Second video signal processing device 14 ... Frame synchronizer 21 ... First memory means 22 ... First memory means write controller 23 ... Memory transfer controller 24 ... Second memory means 25 ... Second memory means read controller 26. Input / output synchronization signal time difference detection means

Claims (3)

(57) [Claims] 1. A first displayable by a first synchronization signal.
Is input video signal, a first memory means for storing the first video signal the input, the video signal inputted to said first memory means and said
The writing control means for controlling writing to the first memory means based on the first synchronization signal, the second memory means for storing the input video signal for at least one frame, and the writing control means Transfer means for reading the first video signal stored in the first memory means under write control, transferring to the second memory means for writing in synchronization with the first synchronization signal, and the second The first video signal stored in the memory means is displayed as an image on the display means for displaying the second video signal having a frequency different from that of the first video signal .
Therefore, a second cycle having a different screen cycle depending on the second synchronization signal
Read control means for reading out as the video signal, and the transfer means is overtaking the first sync signal and the second sync signal based on the time difference between the first sync signal and the second sync signal. Due to the
And overtaking detecting means for beforehand detecting the over arm, based on the detection of overtaking occurs by the overtaking detecting means, said transfer of a frame in which the overtaking occurs
Set the transfer timing of the means to the transfer
A video signal input / output device comprising: a transfer control unit that controls the first synchronization signal so that the first synchronization signal is delayed by a predetermined time. 2. A first displayable by a first synchronization signal.
A video signal is input, and the input first video signal is recorded.
A first memory means for storing, The video signal input to the first memory means is
Writing to the first memory means based on a first synchronization signal
Writing control means for controlling the writing, Store the input video signal for at least one frame
Second memory means, By the write control by the write control means, the first
Read out the first video signal stored in the memory means
The second memory hand in synchronization with the first synchronization signal.
Transfer means for transferring and writing to the stage, The first video signal stored in the second memory means
To a second synchronization signal having a frequency higher than the first synchronization signal.
It is displayed as an image on the display means that is displayed by a signal.
Therefore, a second cycle having a different screen cycle depending on the second synchronization signal
Read control means for reading out as a video signal of The time difference between the first synchronization signal and the second synchronization signal
Based on the first sync signal of the second sync signal
Overtaking for this occurs during transfer by the transfer means
Overtaking detection means for detecting the frame in advance, Based on detection of occurrence of overtaking by the overtaking detection means
Then, the transfer in the frame in which the overtaking occurs
The transfer timing of the means is set with respect to the first synchronization signal.
By delaying for a fixed time, the second memory means
The stored frame before the overtaking occurs
The read control means controls the video signal to be read.
Transfer control means, A video signal input / output device comprising: 3. A table represented by the first sync signal input.
The first video signal that can be displayed is an NTSC resolution image.
Image signal, Second video signal read by the read control means
Is an HDTV system resolution video signal
The video signal output device according to claim 1 or 2.