JPH07114504B2 - Frequency conversion circuit and frequency conversion method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a frequency conversion circuit and a frequency conversion method suitable for use in, for example, image processing in a video tape recorder, a television receiver, or the like.

[Outline of Invention]

The present invention compares a first address signal and a second address signal in a frequency conversion circuit that performs frequency conversion by writing and reading information in a memory with asynchronous first and second address signals, and responds to the comparison. When the first and second address signals are overtaken, the order of the address signals to the memory is switched and a continuous output signal is taken out from the memory, so that an image is obtained by overtaking the first and second address signals. It is intended to prevent the occurrence of abnormalities.

[Conventional technology]

As a conventional frequency conversion circuit (frame synchronizer) for performing frequency conversion, for example, the one shown in FIG. 6 has been proposed. That is, in FIG. 6, a plurality of frame memories (or field memories ... The same applies hereinafter).
(1) and (2) are provided, and an 8-bit composite color video signal is supplied to the frame memories (1) and (2) separated into upper 4 bits and lower bits, respectively. . That is, the frame memories (1) and (2) use the supplied 4-bit data as the write clock signal CK.
Clock signal CKR for writing and reading sequentially based on W
Read based on. At this time, the clock signals CKW and CKR are asynchronous. Therefore, the frame memory (1),
At the output side of (2), a frequency different from the frequency of the input signal, that is, a frequency-converted output signal is obtained.

Then, as will be described later, the frame memory (1),
When an overtaking occurs between the write address signal and the read address signal used in (2), this is detected by the overtaking detection circuit (3), and the chroma is detected according to the detection result of the overtaking detection circuit (3). Inverter (4)
At, the phase of the sub-carrier is shifted by 180 ° so that normal color reproduction is performed and the result is taken out to the output terminal (5).

As the frame memories (1) and (2), for example, those shown in FIG. 7 are used. In Figure 7, (10)
Is an input terminal to which a video signal is supplied, and the video signal from this input terminal (10) is sequentially input to a serial access memory (hereinafter referred to as SAM) (11) in units of lines based on a write clock signal CKW. Written. This SAM
The data written in (11) is a line-by-line dynamic random access memory (hereinafter referred to as DRAM).
(12) is transferred to the counter, clock signal CLK
Is written in a predetermined position of the DRAM (12) specified by the address signal from the write address circuit (13).

The data written in a predetermined position of the DRAM (12) is read line by line by using a counter, designated by an address signal from a read address circuit (14) to which a clock signal CLK is supplied, and read by a SAM (15 ) Is written to. The information transferred to the SAM (15) is shifted by one bit each time the read clock signal CKR is supplied and taken out to the output terminal (16). Note that SAM (1
1) and (15) are equal capacity and clock signals CKW and CKR
Is asynchronous.

[Problems to be solved by the invention]

By the way, in the structure shown in FIG. 6, since the input and output of the frame memories (1) and (2) are asynchronous, the write address signal from the address circuit (13) and the read address signal from the address circuit (14). Occurs somewhere, and at the time of passing, the data is replaced from the current field to the previous field. That is, in FIG. 8, the solid line represents the temporal transition of the write address signal, the broken line represents the temporal transition of the read address signal, and the read address signal is higher than the frequency of the write address signal (cycle). Is short).
Then, when overtaking does not occur between both address signals, the nth field information is read out at the time t _{1 to} t ₂ ,
Time t ₂ in ~t ₄ n + 1 th field information is read, the time t ₄ in ~t ₅ n + 2 th field information is read out, should the time t ₅ ~t ₆ in the n + 3 th field information is read although, when results overtaking read address signal at time t ₃ is caught up with the write address signal, the time t ₂ ~t ₃ in (n + 1) -th field information or the time t ₃ the current field information is read
~t n th field information or previous field information as shown in FIG. 8 at ₄ is to be read out,
After it will be similarly time t ₄ ~t ₅ in (n + 1) -th field information, the time t ₅ ~t ₆ in (n + 2) -th field information and one field before the field information is read.

Such an overtaking phenomenon is good in the case where the frame memory (1) for upper 4 bits and the frame memory (2) for lower 4 bits are used simultaneously as shown in FIG. This is a problem when the passing times do not always match between the memories due to variations or the like. That is, at this time, the upper 4 bits and the lower 4
There is a drawback in that the current field and the previous field are mixed as the contents of data depending on the bit, and as a result, the screen is seriously affected.

The present invention has been made in view of the above circumstances, and provides a frequency conversion circuit and a frequency conversion method capable of eliminating the occurrence of overtaking and preventing an adverse effect on the screen.

[Means for solving problems]

For example, as shown in FIG. 1, the frequency conversion circuit of the present invention writes an input signal to a predetermined address of the memory (12) with a first address signal for sequentially specifying an address on a line-by-line basis. In a frequency conversion circuit for reading the information written in the line by a second address signal that sequentially specifies an address to obtain an output signal whose frequency is converted, a delay means (26) for delaying the output signal, and Means for switching the delay amount of the output signal (2
5) and the first and second address signals are compared with each other, and comparing means (20) for setting a flag when one of these address signals indicates a state of overtaking the other, and this comparing means (20). Correction circuit supplied with the output of (28)
In response to this flag, the address correction circuit (28) shifts the order of the address signals to the memory (12) by a predetermined order, and the means (25) for switching the delay amount after a predetermined period elapses. A continuous output signal is taken out from the memory (12) by switching the delay amount of the output signal.

Further, according to the frequency conversion method of the present invention, the input signal is written to a predetermined address of the memory (12) by the first address signal for sequentially specifying the address on a line-by-line basis, and this memory (12) is written.
In the frequency conversion method for obtaining the output signal with the frequency converted by reading the information written in the predetermined address with the second address signal that sequentially specifies the address in line units, the first and second address signals are In comparison, a flag is set when one of these address signals indicates a state in which it is likely to overtake the other, and in response to this flag, the address correction circuit (28) determines the order of the address signals for this memory (12). The output signals are sequentially shifted, and after a lapse of a predetermined period, the delay amount of the output signal is switched and output, so that a continuous output signal is taken out from the memory (12).

[Action]

A comparator (20) compares the first address signal, that is, the write address signal with the second address signal, that is, the read address signal, and sets a flag when an overtaking is about to occur between the two address signals. Set the circuits (21) and (22). Then, the output of the frame memory is switched from the normal route according to the logical result of the flip-flop circuits (21) and (22), and the address circuits (13) and (14) are controlled by the address correction circuit (28) to control the DRAM ( Switch the order of address signals for 12). This effectively prevents the phenomenon of overtaking,
A continuous output signal can be taken out from AM (12).

[Embodiment] An embodiment of the present invention will be described below in detail with reference to FIGS. 1 to 5.

FIG. 1 shows the circuit configuration of this embodiment, and the frame memory as shown in FIG. 7 is also used in this embodiment. Therefore, in FIG. 1, parts corresponding to those in FIG. 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, a comparator (20) is provided, and the address signal from the write address circuit (13) is compared with the address signal from the read address circuit (14), and one address signal is the other address signal. Generates a flag when you are about to pass. The flag from the comparator (20) is a pair of D-type flip-flop circuits (21) and (22).
Is supplied to the input terminal D of. Further, the clock signal CLK applied to the read address circuit (14) is supplied to the clock terminal of the flip-flop circuit (21) and the flip-flop circuit (2) via the inverter (23).
It is supplied to the clock terminal of 2). The output of the flip-flop circuit (21) becomes "1" when the read-ahead address is about to change from the write-ahead to the read-ahead, that is, when the read address signal is about to overtake the write-address signal. Becomes "0". In addition, when the read ahead is likely to change to the read ahead, that is, when the write address signal is about to overtake the read address signal, the output of the flip-flop circuit (21) becomes “1”, and the flip-flop circuit (22) Output becomes "0".

The output of the flip-flop circuit (21) is supplied to the set terminal SET2 of the switch control circuit (24), and the output of the flip-flop circuit (22) is supplied to the set terminal SET1 of the switch control circuit (24). The switch control circuit (24) connects the switch (25) to the contact b in the vertical blanking interval during reading.
Preset to the side. And set terminals SET1 and SET2
When a signal of "1" is supplied to either of the above, the switch (25) is switched to the contact a side with a delay of a predetermined time, for example, 2H from the time of the supply. The contact b of the switch (25) is connected to the output side of the SAM (15) via the 2H delay circuit (26), and the contact a is directly connected to the output side of the SAM (15). Then, the common terminal c of the switch (25) is connected to the output terminal (27).

The outputs of the flip-flop circuits (21) and (22) are supplied to the address correction circuit (28), and the address correction circuit (28) writes according to the output results of the flip-flop circuits (21) and (22). For controlling the read address circuit (13) or the read address circuit (14). That is, when the output of the flip-flop circuit (22) is "1" and the output of the flip-flop circuit (21) is "0", the address correction circuit (28) controls the read address circuit (14) to control the address. When the order of signals is -2, the output of the flip-flop circuit (21) is "1", and the output of the flip-flop circuit (22) is "0", the write address circuit (13) is controlled to output the address signal. The order of is +2.

Next, the operation of FIG. 1 will be described with reference to FIGS. FIG. 2 shows a state in which a flag is generated on the output side of the comparator (20). The clock signal CLK as shown in FIG. 2A is supplied to the read address circuit (14) and the flip-flop circuit. It is supplied to the clock terminal of (21) and further supplied to the clock terminal of the flip-flop circuit (22) via the inverter (23). here,
If the frequency of the read address signal from the address circuit (14) shown in FIG. 2B is higher than the frequency of the write address signal from the address circuit (13) shown in FIG. 2C, the second As can be seen from Figures B and C,
The read address signal comes to overtake the write address signal, and when the read address signal partially matches the write address signal, that is, the read address signal seems to overtake the write address signal. The output of the comparator (20), the second
A flag as shown in FIG. D is generated. For example, in FIGS. 2B to 2D, the flag is generated at the time when a part of each of the n−1th, nth and n + 1th read and write address signals match.

Assuming that the frequency of the write address signal is higher than the frequency of the read address signal, the write address signal will overtake the read address signal, as can be seen from FIGS. 2B and 2E. When part of the address signal matches part of the read address signal, that is, when the write address signal is about to overtake the read address signal, the output of the comparator (20) is shown in FIG. The flag shown is generated. For example, in FIGS. 2B, 2E and 2F, a flag is generated at the time when a part of each of the n-2th, n-1st and nth read and write address signals match.

The flag obtained at the output side of the comparator (20) is supplied to the input terminals D of the flip-flop circuits (21) and (22),
When the clock signal CLK supplied to the read address circuit (14) is applied to the clock terminal, it is output to the output terminals Q of the flip-flop circuits (21) and (22).
That is, when the read address signal (FIG. 2B) tries to overtake the write address signal (FIG. 2C), the read address signal (FIG. 2B) is changed to the FIG. 2D at the trailing edge of the clock signal CLK shown in FIG. 2A. The flag shown is generated on the output side of the flip-flop circuit (22) and becomes "1" (the output of the flip-flop circuit (21) is "0" at this time), and the write address signal (Fig. 2E) is for reading. Address signal (Fig. 2B)
The clock signal shown in FIG. 2A when attempting to overtake
The flag shown in FIG. 2F is generated at the output side of the flip-flop circuit (21) at the rising edge of CLK and becomes "1" (at this time, the output of the flip-flop circuit (22) is "0").

In the normal mode where overtaking does not occur, the switch (25) is connected to the contact b side, and the output of the frame memory, that is,
The output of SAM (15) is n-2, n-1 ,, as shown in FIG. 3A.
The video signals corresponding to the address signals of n, n + 1, ..., N + 5 are sequentially output, and the output terminal (27) receives the third signal.
As shown in Fig. C, the output of SAM (15) is delayed by 2H, n-4, n
Video signals corresponding to −3, n−2, n−1, n, ..., N + 3 and each address signal are sequentially output.

However, as described above, for example, when the read address signal is about to overtake the write address signal, the output of the flip-flop circuit (22) becomes "1", the output of the flip-flop circuit (21) becomes "0", and the address correction circuit (2
8) controls the read address circuit (14) and shifts the nth address by -2 as shown in FIG.
For the DRAM (12), similarly, the n + 1th is the n-1th, the n + 2 is the nth, and the n + 3 is the nth.
The order of the address signals is reduced by -2, such as +1, ... Then, the switch control circuit (24) switches the switch (2) 2H after the time when the output of the flip-flop circuit (22) becomes "1" and the output of the flip-flop circuit (21) becomes "0" when it is about to pass.
Switch 5) to the contact a side.

Then, until now, the output terminal (27) has a 2H delay circuit (26).
Although the video signal corresponding to each address signal of n-4, n-3, n-2, n-1 on the C side in FIG. 3 was output via the switch (25), the switch (25) After switching to, the video signals corresponding to the respective address signals of n, n + 1, n + 2, n + 3 ... On the lower side of FIG. 3A are output. That is, the video signal corresponding to each address signal is continuously output to the output terminal (27) in the order shown by hatching in FIG.

When the write address signal is about to pass the read address signal, a flip-flop circuit (21)
Is "1", the output of the flip-flop circuit (22) is "0", and the address correction circuit (28) controls the write address circuit (13) at a point when it is likely to pass, for example, n.
The second address signal is shifted by +2 as shown in FIG. 4A and generated as the n + 2th address signal in the DRAM (12), and the predetermined position of the DRAM (12) corresponding to the n + 2th address signal is generated. Then, the video signal to be written is written corresponding to the nth address signal. That is, in the normal mode in which no overtaking occurs, as shown in FIG. 5, the video signals V ₁ , V ₂ , V ₃ ... Vn are sequentially written and read corresponding to the addresses ₁ , ₂ , ₃ ... N. However, when the write address signal is about to overtake the read address signal, no video signal is written at the position corresponding to the address signal to be overtaken and the next address signal, and after jumping two. The data is sequentially written from the position corresponding to the address signal.
Therefore, the fourth nothing video signal is not written to the position of the next (n + 1) th address signals to the n-th address signals in FIG At A overtaking likely time the video signal V _n corresponding to the n-th address signals The video signal Vn _{+ 1} corresponding to the (n + 2) th address signal and the video signal Vn _{+ 1} corresponding to the ( _{n + 1)} th address signal are written to the position corresponding to the (n + 3) th address signal, and so on.

Then, 2 hours after the time when it is likely to pass, that is, when the output of the flip-flop circuit (21) becomes "1" and the output of the flip-flop circuit (22) becomes "0", the switch control circuit (2
4) switches the switch (25) to the contact a side. Then,
Until now, the video signal corresponding to each address signal of n-4, n-3, n-2, n-1 on the side of FIG. 5C is output to the output terminal (27) through the 2H delay circuit (26). V _n-4 , V _n-3 , V _n-2 , and V _n-1 were output, but after the switch (25) was switched to the contact a side, n + 2, n + 3, on the A side in FIG. The video signals V _n , V _{n + 1} , V _{n + 2} , V _{n + 3} corresponding to the respective address signals of n + 4, n + 5 ... Are output. That is, the video signal corresponding to each address signal is continuously output to the output terminal (27) in the order shown by hatching in FIG.

〔The invention's effect〕

As described above, according to the present invention, the first and second address signals are compared with each other, and when an overtaking is about to occur between them, the order of the address signals for the memory is switched so that continuous output signals are taken out from the memory. Therefore, it is possible to eliminate the overtaking of the address signal, and therefore there is no problem even when the input data is processed by being divided into the upper bits and the lower bits, and the serious adverse effect on the screen as in the conventional case is prevented. Further, according to the present invention, the overtaking of the address signal itself does not occur, so that the overtaking detection circuit and the chroma inverter, which have been used conventionally, are unnecessary, and the circuit configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 to 5 are diagrams for explaining the operation of the present invention, and FIG. 6 is a circuit diagram showing an example of a conventional circuit. FIG. 7 is a circuit configuration diagram showing a frame memory, and FIG. 8 is a diagram for explaining an overtaking operation. (11) and (15) are serial access memory (SAM), (1
2) is Dynamic Random Access Memory (DRAM), 1
3 is a write address circuit, (14) is a read address circuit, (20) is a comparator, (21) and (22) are D-type flip-flop circuits, (24) is a switch control circuit, and (25).
Is a switch, (26) is a 2H delay circuit, and (28) is an address correction circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04N 5/92 9/87 A H04N 5/92 B

Claims (2)

[Claims] 1. A first system for sequentially specifying addresses on a line-by-line basis
The input signal is written to a predetermined address of the memory by the address signal of, and the information written at the predetermined address of the memory is read out by a second address signal that sequentially specifies the address on a line-by-line basis and the frequency-converted output signal is read. In the frequency conversion circuit for obtaining the above, the delay means for delaying the output signal, the means for switching the delay amount of the output signal and the first and second address signals are compared, and one of these address signals overtakes the other. Comparing means for setting a flag when such a state is indicated, and an address correction circuit to which the output of the comparison means is supplied, and in response to the flag, the address correction circuit determines the order of the address signals to the memory. The delay amount of the output signal is switched by means of shifting by a predetermined order and switching the delay amount after a lapse of a predetermined period. Frequency converter, characterized in that they were taken out of the output signal which is continuous from the memory by. 2. A first for sequentially specifying addresses on a line-by-line basis
The input signal is written to a predetermined address of the memory by the address signal of, and the information written at the predetermined address of the memory is read out by a second address signal that sequentially specifies the address on a line-by-line basis and the frequency-converted output signal is read. In the frequency conversion method, the first and second address signals are compared, a flag is set when one of these address signals indicates a state in which it is likely to pass the other, and address correction is performed in response to the flag. A frequency is characterized in that the circuit shifts the order of the address signals to the memory by a predetermined order, and switches the delay amount of the output signal after a predetermined period of time to output it, thereby extracting a continuous output signal from the memory. How to convert.