JPH01190176A - Video signal processor - Google Patents

Abstract

PURPOSE:To attain various video image synthesis of a video signal processing unit without using any expensive time axis correction device by using the 1st and 2nd frame memory means and extracting a digital video signal subject to synchronizing coupling. CONSTITUTION:An analog signal from the 1st and 2nd VTRs 1, 2 is digitized by A/D conversion means 61c, 62c and stored in frame memories 61d, 62d at least in the unit of one frame picture element. Write timing means 61e, 62e and read timing means 63 deciding the write and read timing to the memories, the 1st and 2nd fast feed means overtake control switches 61g, 62g monitoring the phase and quickening the readout timing from the memory if the phases are approached closely in excess of a prescribed value and line buffers 61f, 62f being the 1st and 2nd delay means retarding the sending speed of the digital video signal read by the increased speed are provided to couple synchronously the video signals of the two systems given to a video special effect circuit 7 by means of an inexpensive and simple operation.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is a system which is connected to the front stage of a video special effects device and used to synchronize two systems of video signals input to the video special effects device. The present invention relates to a suitable video signal processing device.

[Conventional technology]

In recent years, reflecting the AV era, there has been remarkable development of various related equipment for video production and computer image processing equipment.

In particular, with respect to the first set of VTRs, in order to change the cut of the screen, change the image, etc., a method is used to create varying images using continuous video signals by combining video signals from multiple systems. Video compositing methods can be broadly divided into mix wipe and overlap. In other words, a mix wipe is, for example, as shown in Figure 4 (
Cut out a part of the video signal of the A screen shown in a), insert and synthesize the video signal of the screen as shown in the same figure (b), and create the C screen shown in the same figure (C). This is a method of obtaining Also, overlap means that the video signal of the A screen is
This is a method of superimposing and synthesizing the video signals of the screen to obtain a screen as shown in FIG. 2(d).

In order to perform such video synthesis, it is necessary that the video signal of the A screen and the video signal of the 8th screen are synchronized, that is, the vertical synchronization signal of the video signal of the A screen and the video signal of the 8th screen must be synchronized. The input timing of the signal and the vertical synchronization signal must match, and if they are not synchronized, a TBC (time base correction device) must be used to synchronously combine them.

That is, as shown in FIG. 5, when the video signal from the playback VTR 1 and the video signal from the playback VTR 2 are combined in the video special effects device 3, a TBC 4 is placed between the TRI and the video special effects device 3. , also connect TBC5 between VTR2 and video special effects device 3, and connect TBC4 and TBC5.
An external synchronization signal is applied to the BC 5 to synchronize the video signal of the VTR 1 and the video signal of the VTR 2 to be sent to the video special effects device 3.

[Problem to be solved by the invention]

However, according to such a conventional video compositing method, a TB inserted and connected between a VTR and a video special effects device cannot be used.
Since C is an expensive item costing 2 million to 2.5 million yen per unit, it is inevitable to buy a VTR for closed use broadcasting work.
ji collections have taken the lead, and it is expected that an inexpensive device that can be used for VTR editing at a consumer level will appear in place of the TBC.

[Means to solve the problem]

The present invention has been made in view of such problems, and includes first and second A/D conversion means for converting analog video signals from first and second source video devices into digital video signals; The first and second frames are capable of writing at least one frame of the digital video signal converted by the first and second A/D converting means pixel by pixel, and read out the input information pixel by pixel while writing the input information. memory means, and first and second write timing determination in which the writing timing of the digital video signal to the 91st and second frame memory means is set to a generation period of a vertical synchronization signal for each frame of the video signal; means and this first
and a read timing determining means whose write timing is determined by a second write timing determining means and whose read timing of the digital video signal written in the frame memory means is set as a predetermined reference cycle; and a read timing determined by the read timing determining means. Timing and the first
and first and second frame memory means for monitoring the phase with the write timing determined by the second write timing determining means and advancing the read timing to the first and second frame memory means when the phase exceeds a predetermined value and approaches the write timing. 2, and the transmission speed of the digital video signal read from the first and second frame memory means by the amount that the read timing is advanced by the first and second read timing quick change means. A video signal processing device is constituted by first and second speed delay means for delaying the speed.

[Effect]

Therefore, according to the present invention, it is possible to extract synchronously combined digital video signals from the first and second frame memory means.

〔Example〕

Hereinafter, the video signal processing device according to the present invention will be explained in detail.

FIG. 1 is a functional block diagram of a video synthesis unit including an embodiment of this video signal processing device, in which 6 is a video signal processing circuit corresponding to the video signal processing device of this embodiment, and 7 is a functional block diagram of a video signal processing unit that includes an embodiment of this video signal processing device. This is a video signal special effect circuit that synthesizes video signals processed and extracted by the signal processing circuit 6. The video signal processing circuit 6 receives the NTS from the playback VTR1.
A first signal processing circuit 61 that processes a C human input signal or a Y/C input signal, and a second signal processing circuit 62 that processes an NTSC input signal or a Y/C input signal from the playback VTR 2.
and a read timing generator 63. The video signal special effects circuit 7 also includes a mixer & selector 71, a D/A converter 72, an RGB decoder 73, and a Y/C
It is composed of a synthesizer 74.

In the video signal processing circuit 6, the signal processing circuit 61 includes:
A Y/C separator 61a separates the Y/C component of the NTSC input from the playback VTR 1, and the Y/C signal separated by this Y/C separator 61a or the Y/C signal from the VTR 1 is input and the Y/C signal is input to this Y/C separator 61a. RG that decodes /C signal into RGB signal
A B decoder 61b, an A/D converter 61c that converts an RGB signal as an analog quantity sent out by this RGB decoder 61b into an 8-bit digital value, a frame memory 61d, and a Y signal that is about to be input to the RGB decoder 61b. Write timing generation for branching and inputting the /C signal, generating a sampling clock and a write address having the same cycle as the vertical synchronization signal generation cycle for each frame, and sending the generated sampling clock and write address to the A/D converter 61C and frame memory 61d. 61e, a line buffer 61f, and an overtaking control switch 61g.

The frame memory 61d has a storage capacity capable of writing a small number of RGB signals input via the A/D converter 61c (one frame in pixel units, and the writing timing of the RGB signals is the write timing. It is defined by the write address manually inputted via the generator 61e.The readout of the RGB signal written in the frame memory 61d is performed according to the predetermined reference period TO of the read timing generator 63 (in this embodiment). In the example, this is performed using a read address that is sent every T O = 33 m5ec), and writing and reading of RGB signals in the frame memory 61d can be performed asynchronously. That is, In this embodiment, the frame memory 6
1d, a field memory (FIFO memory) is used in which the input information can be read out pixel by pixel while being written. And this frame memory 6
The RGB signals read from the signal input terminal 1d are input to the mixer and selector 71 in the video signal special effects circuit 7 via the overtaking control switch 61g. The overtaking control switch 61g is such that the connection mode of its movable contact piece 6191 is changed by the overtaking control signal via the read timing generator 63, and normally the movable contact piece 619. is a normally closed contact 619. It is connected to the side. That is, the read timing generator 63 monitors the phase of the read address to be sent to the frame memory 61d and the write address to be manually input to the frame memory 61d. The difference in input timing between the write address and the read address is monitored, and this phase is set to a predetermined value (in this example, approximately 30
When approaching beyond μ5ec), the frame memory 61
The sending timing of the lead address for d is advanced by about 1% of the lead address generation cycle, and the movable contact piece 61g of the overtaking control switch 61g is
+ is a normally open contact 619. A control signal is sent out to connect the terminal to the other side. Overtaking control signal - movable contact piece 619 at notch 61g
1 is connected to the normally open contact 6191 side, the RGB signal read from the frame memory 61d is input to the mixer & selector 71 via the line buffer 61f. It has a function of delaying the sending speed of the read RGB signal to the mixer & selector 71 by the amount that the read address is accelerated.

Note that in the video signal processing circuit 6, the signal processing circuit 6
Since the configuration of No. 2 is the same as the signal processing circuit 61,
A corresponding number is assigned to each component block, and the explanation thereof will be omitted.

Next, the operation of the video composition unit configured as described above will be explained. That is, in the video signal processing circuit 6, the write address generation cycle TI generated by the write timing generator 61e and the read timing generator 6
It is assumed that the generation cycle MTO of read addresses generated in No. 3 is different, and the generation cycle T1 of write addresses is longer than the generation cycle TO of read addresses. In this case, one frame of the RGB signal sent to the frame memory 61d via the A/D converter 61c is written to the frame memory 61d at a period of T1, as shown in FIG. 2fa). on the other hand,
The read timing generator 63 sends a read address to the frame memory 61d at a period of TO, and transmits the read address to the frame memory 61d at each input timing of this read address.
The RGB signals written in d are read out. That is, if a write address is input at time a shown in FIG. 2(a) and a read address is input at time b shown in FIG. The reading of the RGB signal starts at time b, and the writing of the RGB signal begins at the next time point C.
Reading of the B signal starts from time d.

Here, the difference between the input timings of the write address and the read address is reduced because the generation cycle T1 is longer than TO, and eventually the input timing of the read address becomes earlier than the input timing of the write address.

In other words, after a read address is input at time e shown in FIG. 1 (bl), a write address is input at time f shown in FIG. The RGB signal write3 is read out again, and thereafter the RGB signal write4 is read out at time g shown in FIG.

On the other hand, if the write address generation cycle T1 is shorter than the read address generation cycle TO, the input timing of the read address will be delayed with respect to the input timing of the write address. That is, Fig. 3 (al
In the same figure (
The read address that was input at time a' shown in b) is input at the corresponding write address input time C' at the next read address input time d'.
becomes delayed. In this case, the write starts at the write address input point b'.
The readout of the RGB signal ite2 is canceled, and at the read address input point d', the write
The RGB signal e3 is now read out. From then on, write4 RGB at time e shown in tb> of the same figure.
The signal is read out, and then Write5. write6・
. . . and read out while repeating the above-mentioned operation.

In this way, when the period of RG B (number 8) on the VTR 1 side is read from the frame memory 61d, it is adjusted to the generation period of the read address, and the mixer and selector 71 of the video signal special effects circuit 7 is adjusted via the overtaking control switch 61g. In other words, VT
Similarly to the above, the period of the RGB signal on the R2 side is adjusted to the generation period of the read address when reading from the frame memory 62d, and the overtaking control switch 62g is adjusted.
through the mixer and selector 7 of the video signal special effects circuit 7
1, the mixer and selector 71 inputs V
The RGB signals on the TR1 side and the RGB signals on the VTR2 side are synchronously combined, and signal synthesis such as minx swipe and overlap at the mixer and selector 71 can be reliably realized.

Normally, in this way, the frame memory 61d
The RGB signals on the VTR1° side and the RGB signals on the VTR2 side read from the line buffer 62d
The signal is directly input to the mixer and selector 71 without passing through f and 62f, and the signal is synthesized. However, if the input timings of the write address and read address are too close to each other in the frame memories 61d and 62d, the read address will be read out. The RGB signals are manually input to the mixer & selector 71 via the line bass sofas 6'lf and 62f.

For example, when the input timing of the write address to the frame memory 61d, that is, the phase of the write address and the read address are close to each other by more than about 30 μsec, the timing at which the read address is sent to the frame memory 61d changes. In the device 63, the read address generation cycle can be advanced by about 1%. That is, if the input timings of the write address and read address overlap in the frame memory 61d, there is a risk that the images of the previous and subsequent frames will be combined. Forcibly advance the sending timing of the address so that it does not overlap with the write address. After the read address transmission timing is advanced, the transmission speed of the RGB signal read from the frame memory 61d to the mixer & selector 71 is accelerated, so the connection mode of the overtaking control switch 61g is switched and the frame memory The RGB signals read from 61d are sent to the mixer &
The data is sent to the selector 71. In other words, the sending speed of the RGB signal in the line buffer 61f is delayed by the amount that the input timing of the read address is advanced, so that the cycle of the RGB signal input to the mixer & selector 71 is maintained at the generation cycle of the read address. , and the RGB signals on the VTR 2 side which are input to the mixer & selector 71 via the signal processing circuit 62 are synchronized. If the write address and read address to the frame memory 62d are close in phase, the frame memory 62d
The RGB signals read from 2d are sent to the line buffer 62.
Needless to say, the signal is inputted to the mixer & selector 71 via the signal processing circuit 61, and synchronously combined with the RGB signal on the VTRl side inputted via the signal processing circuit 61 in the same manner as described above.

In this embodiment, the source video equipment to be synchronously coupled in the video signal processing circuit 6 is connected to the playback VT.
Although R1-VTR2 is used, this combination is not necessarily required, and various combinations such as TV camera-TV camera, TV camera=VTR, etc. are possible. Also,
The functions of the video signal special effects circuit 7 include, in addition to mix-wipe and Oharatsubu, VTRI and 2-image switching, VTRI 2-image fade-in/fade-out (afterimage), VTR 1 and 2-image dual-sided display, TV,
, TV functions, etc. can also be added.

Furthermore, in this embodiment, synchronization between two types of source video devices is attempted, but by adding a signal processing circuit in the video signal processing circuit 6, it is possible to synchronize even more source video devices. Needless to say, it is possible to achieve a combination.

As explained above, the video signal processing circuit according to this embodiment can be applied to recent feed memories and A/Ds.

Thanks to the high performance and low cost of ICs such as D/A converters, devices that enable synchronous connection between source video devices are becoming popular.
It can be manufactured at a lower cost than a BC (can be manufactured at about half the price of a TBC), and unlike a TBC, it is not necessary to provide a synchronization signal from the outside, so its operation is extremely simple. Additionally, in the past, when the number of source video devices to be synchronously combined increases, TBC
However, according to the video signal processing circuit shown in this embodiment, this circuit can be constructed compactly as one device, and therefore its handling and setup work are extremely easy. In addition, video compositing/special effects, which were previously limited to professional use, can now be widely used for professional needs such as high-class enthusiasts, bridal photography, schools, and companies, and their utility value is extremely high. .

〔Effect of the invention〕

As explained above, according to the video signal processing device according to the present invention, the first and second A converting the analog video signals from the first and second source video devices into digital video signals.
A/D converting means, and a first A/D converting means capable of writing at least one frame of the digital video signal converted by the first and second A/D converting means in pixel units and reading out the input information in pixel units while writing the input information. first and second frame memory means, and first and second frame memory means in which the writing timing of the digital video signal to the first and second frame memory means is the generation cycle of a vertical synchronization signal for each frame of the video signal; a read timing in which the write timing is determined by the first and second write timing determining means and the read timing of the digital video signal written in the frame memory means is set as a predetermined reference cycle; a determining means, which monitors the phase between the read timing determined by the read timing determining means and the write timing determined by the first and second write timing determining means, and when these phases exceed a predetermined value and become close to each other, the first and first and second read timing quick changing means for advancing the read timing to the second frame memory means; a first frame memory means for delaying the transmission speed of the digital video signal read out from the first and second frame memory means;
Since the video signal processing device is configured with the first and second speed delay means, it is possible to extract the synchronously combined digital video signal from the first and second frame memory means, which eliminates the conventional method using TBC. It has many excellent effects, such as making it possible to synchronize and connect source video equipment at a lower cost than with a TBC, and making it extremely easy to operate since there is no need to provide a synchronization signal from an external source like with a TBC. play.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram of a video synthesis unit including an embodiment of the video signal processing device according to the present invention, and FIG. 2 is a functional block diagram of a video signal processing circuit in the video synthesis unit in which the write address generation cycle is shorter than the read address generation cycle. A timing chart explaining the operation when the generation cycle is longer,
FIG. 3 is a timing chart explaining the operation when the write address generation cycle is shorter than the read address generation cycle in this video signal processing circuit. FIG. 5, which is a diagram for explaining overlap, is a diagram showing a conventional video compositing method using TBC. 1.2...VTR16...Video signal processing circuit, 7.
...Video signal special effect circuit, 61.62...Signal processing circuit, 63...Read timing generator, 61c, 6
2c...A/D converter, 61d, 62d...Frame memory, 61e, 62e...Write timing generator, 61f, 62f...Line buffer, 61g
, 62g...passing control switch, 71.
...Mixer and selector. Patent applicant: Nippon Avionics Co., Ltd. Freedom Video Co., Ltd.

Claims (1)

[Claims] first and second A/D conversion means for converting analog video signals from first and second source video equipment into digital video signals; and digital signals for conversion by the first and second A/D conversion means. first and second frame memory means capable of writing at least one frame of a video signal pixel by pixel and reading out the input information pixel by pixel while writing the input information; first and second write timing determining means for setting the write timing of the digital video signal to a generation period of a vertical synchronization signal for each frame of the video signal;
and a read timing determining means whose write timing is determined by a second write timing determining means and whose read timing of the digital video signal written in the frame memory means is set as a predetermined reference cycle; and a read timing determined by the read timing determining means. Timing and the first
and first and second frame memory means for monitoring the phase with the write timing determined by the second write timing determining means and advancing the read timing to the first and second frame memory means when the phase exceeds a predetermined value and approaches the write timing. 2, and the transmission speed of the digital video signal read from the first and second frame memory means by the amount that the read timing is advanced by the first and second read timing quick change means. A video signal processing device comprising first and second speed delay means for delaying the speed.