JP2001086426A - Video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a synthetic image from being distorted even when a clock skew occurs. SOLUTION: A horizontal synchronizing signal HD1 provided from a TS signal is applied to a multiplication circuit 20 and a multiplied clock CK3 is provided. While using a clock CK2 based on an analog video signal, a memory 12 stores the analog video signal. The clock CK2 synchronized to the analog video signal and a horizontal synchronizing signal HD2 are stored on memories 21 and 22 at timing of the clock CK3 and a read control circuit 24 controls the read of the memory 12 corresponding to the outputs of the memories 21 and 22. The memory 12 uses a read clock RCK and the clock CK3, and a video signal maintaining the phase relation of the video signal and the clock is read out of the memory 12. Thus, the picture quality of an image synthesizing the TS signal and the analog video signal is prevented from being deteriorated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus for performing video processing on an input television signal using a clock that is asynchronous with the input television signal.

[0002]

2. Description of the Related Art Conventionally, in a television receiver or the like, in addition to a normal display mode in which one image is displayed over the entire display screen, two or more images are divided and displayed on the same display screen. Devices having a multi-screen display function have been developed. For example, those having a sub-screen display function of displaying a sub-screen or a two-screen display function of simultaneously displaying two screens of the same size on a part of an image based on a received television signal or an external video signal have been commercialized. Have been.

In order to realize such a multi-screen display function, one type of video signal is created by, for example, synthesizing signals obtained from two types of video signal sources. The synthesizing process needs to be performed while synchronizing the respective video signals with each other. That is, the synchronization signal of one video signal may be drawn into the synchronization signal of the other video signal. Such synchronization of video signals is called frame synchronization processing, and is used when two types of video signals are simultaneously displayed on a television receiver. In addition, regarding the frame synchronization processing,
It is described in detail in Japanese Patent Application No. 8-163400.

In a conventional video signal processing apparatus for performing such frame synchronization processing, one field or one field
A memory capable of storing video signals for frames is provided. Then, frame synchronization processing is performed by independently controlling writing and reading of digitized video signals to and from the memory.

[0005] Writing and reading control use a clock phase-synchronized with a horizontal synchronizing signal multiplexed with a television signal. Using a write control signal synchronized with one video signal and a read control signal generated from a reference synchronization signal that is not synchronized with this video signal, one video signal is written to a memory using a write control signal and stored in the memory. The read video signal is read using the read control signal. Thus, the video signal read from the memory is synchronized with the reference synchronization signal. If this reference synchronization signal is generated from another video signal that is displayed simultaneously with one video signal, it is possible to mix and display two independent video signals of one and the other.

[0006] By the way, non-standard signals such as reproduction signals of a home VTR (video tape recorder) have unstable horizontal synchronizing signals. Further, even when a standard signal is used, when a clock phase-synchronized with the horizontal synchronizing signal is generated, clock skew may occur due to the influence of noise or ghost. Even in such a case, when the read control signal is created from the video signal written in the memory, there is not much problem because the write and read sampling points match.

However, in the frame synchronization processing, since the write control signal and the read control signal are asynchronous, when the horizontal synchronizing signal of the video signal is unstable like a non-standard signal, the video signal and the read control signal are not synchronized. There is a delay difference from the horizontal sync signal, and the display shifts in the horizontal direction,
This may cause image quality degradation.

[0008]

As described above, in the conventional video signal processing apparatus described above, the horizontal display of the video is shifted during the frame synchronization processing due to the clock skew of the horizontal synchronization clock, and the image quality is degraded. There was a problem that it would occur.

According to the present invention, there is provided a video signal processing apparatus capable of preventing a horizontal display shift of a video in frame synchronization processing and suppressing image quality deterioration even when a clock skew of a horizontal synchronization clock occurs. The purpose is to provide.

[0010]

According to the present invention, there is provided a video signal processing apparatus comprising: first clock generating means for generating a first clock phase-synchronized with a horizontal synchronizing signal of an input television signal; First storage means for storing the input television signal using a clock, second clock generation means for fixedly oscillating a second clock having a predetermined frequency higher than the first clock, and Second storage means for storing the horizontal synchronization signal using a clock,
Third storage means for storing the first clock using the second clock; and the horizontal synchronization signal stored in the second storage means and the first storage means stored in the third storage means. Control means for controlling the readout phase of the first storage means based on a clock.

In the present invention, the first clock generating means generates a first clock phase-synchronized with the horizontal synchronizing signal of the input television signal, and the first storage means stores the input television signal using the first clock. Store the John signal. Second
Clock generating means oscillates fixedly a second clock having a higher frequency than the first clock. The second and third storage units store the horizontal synchronization signal or the first clock using the second clock, respectively. The control means includes the second and third
The read phase of the first storage unit is controlled based on the horizontal synchronization signal read from the storage unit and the first clock. Thus, the read timing from the first storage means is defined by the second clock.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a video signal processing device according to the present invention. The present embodiment is applied to an apparatus for displaying two images of a digital broadcast and a current analog broadcast on two screens.

In this embodiment, the write control signal and the read control signal are asynchronous by using a high-frequency read control signal for the write control signal synchronized with the horizontal synchronizing signal of the input television signal. And the horizontal synchronization signal and the write control signal are synchronized with the read control signal and used for reading the input television signal, so that the phase between the input television signal and the write control signal before the frame synchronization processing is reduced. The relationship is reproduced even after the frame synchronization processing, and the horizontal display shift when clock skew occurs is reduced.

A first or second image serving as a source of a composite image is input to input terminals 1 and 2, respectively. For example, input terminal 1
, A digital video signal such as a transport stream signal (TS signal) encoded by the MPEG standard is input as a first image, and a current analog video signal is input to an input terminal 2 as a second image.

FIG. 2 shows first and second images input to input terminals 1 and 2, respectively, and a composite image of these two images. FIG. 2A shows 2200 horizontal pixels and 1 vertical pixel.
FIG. 2 shows a digital interlaced image with 125 lines and effective pixels of 1920 pixels × 1080 lines.
(B) shows an interlaced image of a current analog broadcast having 910 horizontal pixels and 525 vertical lines and 800 pixels × 480 effective pixels. FIG. 2C shows an example in which a composite image of the two images shown in FIGS. 2A and 2B is displayed on a display screen having 1920 pixels × 1080 lines of effective pixels.

The TS signal and the analog video signal input to the input terminals 1 and 2 respectively are the MPEG decoder 3 or the N
It is supplied to the TSC decoder 4. The MPEG decoder 3 decodes the input TS signal and outputs a video signal VIDEO.
1 is output to the horizontal / vertical compression / expansion circuit 5. MPE
The G decoder 3 reproduces the horizontal synchronizing signal HD1 and the vertical synchronizing signal VD1 from the TS signal and generates a clock CK1 synchronized with them.

The clock CK1 has a frequency of, for example, 74.175 MHz, and has a horizontal synchronization signal HD1.
Is, for example, a frequency of 33.716 KHz, and 220
It is a signal of 0 clock and one cycle. The vertical synchronization signal VD1 has a field frequency of 59.94 Hz, for example, and has a period of 1125/2 lines.

The horizontal / vertical expansion / compression circuit 5 receives the clock CK
1, the digital video signal VIDEO1 is compressed and expanded in the horizontal direction based on the horizontal synchronization signal HD1, and is compressed and expanded in the vertical direction based on the vertical synchronization signal VD1. The horizontal / vertical expansion / compression circuit 5 obtains one of the two images to be synthesized based on the first image. The output of the horizontal / vertical compression / expansion circuit 5 is supplied to a synthesis processing circuit 6.

On the other hand, the NTSC decoder 4 decodes the input analog television signal of the current broadcast and outputs an analog video signal, a horizontal synchronizing signal HD2 and a vertical synchronizing signal VD2. The A / D converter 11 converts the input analog video signal into a digital signal and outputs the digital signal to the memory 12 as a digital video signal VIDEO2.

The frame synchronization process is performed by controlling the writing and reading of the memory 12. Video signal VI subjected to frame synchronization processing by memory 12
The DEO 2 is supplied to the horizontal / vertical compression / expansion circuit 13 to perform horizontal / vertical compression / expansion processing, and then outputs to the synthesizing processing circuit 6 as the other image based on the second image of the two images to be synthesized.

In the present embodiment, writing to the memory 12 is performed based on a clock CK2 synchronized with the video signal VIDEO2. That is, the clock generation circuit 1
Reference numeral 4 generates a clock CK2 in which the horizontal synchronizing signal HD2 from the NTSC decoder 4 is multiplied and phase-synchronized. This clock CK2 is used as a write control signal WCK for the memory 12. Note that the clock CK2
Has a frequency of 14.318 MHz, the horizontal synchronization signal HD2 has a frequency of 15.734 KHz, for example, and one cycle is 910 clocks. The vertical synchronization signal VD2 has a period of 525/2 lines at a field frequency of 59.94 Hz, for example.

The clock CK2 is supplied to the A / D converter 1
1, the write control circuit 15 and the flip-flop 16 are also supplied. The write control circuit 15 outputs the clock CK2
The control for writing the digital video signal VIDEO2 to the memory 12 is performed using the horizontal synchronization signal HD2 and the vertical synchronization signal VD2.

On the other hand, in the present embodiment, the memory 1
2 is read using the output of the multiplication circuit 20.
The multiplication circuit 20 receives the clock CK1 from the MPEG decoder 3.
The clock CK1 is multiplied to n times the frequency and a clock CK3 whose phase is synchronized is output. Memory 12
Uses the clock CK3 as the read clock RCK.

The reading of the memory 12 is controlled by a read control circuit 24. In the present embodiment, the read control circuit 24
When performing the read control of No. 2, the NTSC decoder 4
The clock CK2, the horizontal synchronization signal HD2, and the vertical synchronization signal VD2 based on the output are not used as they are. The clock CK2 and the horizontal synchronizing signal HD2 are supplied to the read control circuit 24 via the flip-flops 16 and 17 and the memories 21 and 22. The clock CK2 from the clock generation circuit 14 and the horizontal and vertical synchronizing signals HD2 and VD2 from the NTSC decoder 4 are supplied to flip-flops 16 to 18, respectively.
8 outputs the input signal at the output timing of the multiplying circuit 20.

That is, the clock CK2 is latched by the flip-flop 16 using the clock CK3, and is changed to the timing of the clock CK3. Similarly, the horizontal synchronizing signal HD2 and the vertical synchronizing signal VD2 are also latched by the clock CK3 and changed to the timing of the clock CK3.

Clock CK from flip-flop 16
2 is given to the memory 21. The memory 21 includes a multiplication circuit 20
And outputs the stored clock CK2 to the read control circuit 24 and the horizontal / vertical compression / expansion circuit 13 using the clock CK3 from the CPU as the read clock RCK. The horizontal synchronizing signal HD2 from the flip-flop 17 is supplied to the memory 22. The memory 22 stores the clock CK3 from the multiplication circuit 20.
As the read clock RCK, and outputs the stored horizontal synchronization signal HD2 to the read control circuit 24 and the horizontal / vertical compression / expansion circuit 13. Also, the flip-flop 18
The vertical synchronization signal VD2 is output to the control circuit 23 and the read control circuit 24 at the timing of the clock CK3 from the multiplication circuit 20.

The frame synchronization control circuit 19 has an MPE
The vertical synchronization signals VD1 and VD2 are supplied from the G decoder 3 and the NTSC decoder 4, and a two-input phase error is detected, and the control circuit 23 and the read control circuit 24 are controlled based on the detection result. .

The control circuit 23 supplies the clock C to the memory 21.
The clock CK2 changed at the timing of K3 is written, and the horizontal synchronization signal HD2 changed at the timing of the clock CK3 is written into the memory 22. The control circuit 23 receives a signal based on the phase difference between the vertical synchronization signals VD1 and VD2 of the two types of input video signals from the frame synchronization control circuit 19, and performs a second operation based on the vertical synchronization signal VD1 of the first image. Readout control for displaying an image is performed.

The clock CK2 and the horizontal synchronizing signal H read out by the control circuit 23 at the timing of the clock CK3.
D2 is given to the read control circuit 24. The read control circuit 24 operates based on the output of the clock CK3 from the multiplying circuit 20, and outputs the clock CK2 from the memories 21 and 22 and the horizontal synchronizing signal HD2 and the vertical synchronizing signal VD2 from the flip-flop 18 from the memory 12. Controls reading. As described above, the clock CK3 from the multiplying circuit 20 is used as the read clock RCK. By reading the memory 12 in synchronization with the outputs of the memories 21 and 22, the phase relationship between the digital video signal VIDEO2 and the clock CK2 before the frame synchronization processing can be reproduced even after the frame synchronization processing.

The output of the memory 12 is supplied to a horizontal / vertical compression / expansion circuit 13, and the horizontal / vertical compression / expansion circuit 13
The video signal VIDEO2 is compressed and decompressed in the horizontal and vertical directions by using the clock CK2 and the horizontal synchronizing signal HD2 from the CPU 22, and is used as the other image based on the second image of the synthesized images. 6 is output.

The clock CK1 from the MPEG decoder 3
The horizontal synchronizing signal HD1 and the clock CK2 from the memory 21 are also supplied to the selection circuit 25. Selection circuit 25
Selects the output of the synthesis processing circuit 6 according to the screen display and causes the D / A converter 7 to output it. The D / A converter 7 receives the output of the selection circuit 25, converts the output of the synthesis processing circuit 6 into an analog signal, and outputs the analog signal to the display monitor 8.

The horizontal and vertical synchronizing signals HD1 and VD1 based on the first image from the MPGE decoder 3 are also supplied to a horizontal / vertical deflection circuit 26. Horizontal / vertical deflection circuit 26
Controls the horizontal and vertical deflection of the display monitor 8 so that an image based on the output of the D / A converter 7 is displayed on the display monitor 8.

Next, the operation of the embodiment configured as described above will be described with reference to FIGS. FIG. 2 is an explanatory diagram for explaining screen display, FIG. 3 is a timing chart for explaining the operation of the embodiment, and FIG. 4 is a timing chart for explaining the operation of the embodiment. .

Now, it is assumed that a digital video signal as a source of a first image is input through an input terminal 1 and a current NTSC video signal as a source of a second image is input through an input terminal 2. . FIG. 2A shows the first input to the input terminal 1.
2 (b) shows an example of a second image input to the input terminal 2. FIG.

In digital broadcasting, extremely stable synchronous reproduction is performed using a free-run clock of an external crystal oscillator. In the present embodiment, frame synchronization processing is performed using a clock reproduced from the digital broadcast signal.

The MPEG decoder 3 decodes the input TS to obtain a video signal VIDEO1, and outputs the clock CK1, the horizontal synchronizing signal HD1 and the vertical synchronizing signal VD1 shown in FIGS. obtain. The clock CK1 is also output to the multiplying circuit 20. Multiplication circuit 20
Multiplies the clock CK1 and generates a clock CK3 (FIG. 3D) synchronized with the clock CK1.

On the other hand, the NTSC decoder 4 decodes the input NTSC signal and outputs a video signal VIDEO2, and outputs a horizontal synchronizing signal HD2 and a vertical synchronizing signal VD2 shown in FIGS. 3 (f) and 3 (g), respectively. I do. This horizontal synchronizing signal HD2 is applied to a clock generation circuit 14, which multiplies the horizontal synchronizing signal HD2 by
The clock CK2 shown in FIG.

The clock CK1 has a frequency of 74.175 MHz, and the horizontal synchronizing signal HD1 has a frequency of 33.716 MHz.
The vertical synchronization signal VD1 is a signal of 1200/2 lines at a field frequency of 59.94 Hz. The clock CK2 has a frequency of 14.318 MHz, and the horizontal synchronization signal HD2 has a frequency of 15.734 MHz.
It is assumed that the vertical synchronizing signal VD2 has a period of 525/2 lines at a field frequency of 59.94 Hz with a frequency of 910 clocks at a frequency of 910 clocks. In the present embodiment, for example, n = 4 and the clock CK3 is set to a clock having a frequency of 300 MHz.

As shown in FIG. 3, the clocks CK1, CK
2 are mutually asynchronous. However, the clock CK3 has a sufficiently higher frequency than the clock CK1, and the clock CK1 rises at a timing relatively close to the rising timing of any pulse of the clock CK3.

Video signal VID from NTSC decoder 4
The EO2 is sampled at the clock CK2 timing by the A / D converter 11 and converted into a digital signal, and then stored in the memory 12 using the clock CK2 as the write clock WCK. In this case, the write control circuit 15 controls the horizontal and vertical synchronization signals H of the second image.
Writing to the memory 12 is performed using D2 and VD2.

On the other hand, reading from the memory 12 is performed in the first
Is performed using the horizontal and vertical synchronizing signals of the second image with reference to the image of FIG. That is, in the present embodiment, the clock CK3 obtained by multiplying the clock CK1 based on the first image is used.
Is used as a read clock RCK, the horizontal and vertical synchronizing signals of the second image are synchronized with the clock CK3, and reading is performed based on the vertical synchronizing signal of the first image.

That is, the clock CK2, the horizontal synchronizing signal HD
2 and the vertical synchronizing signal VD2 are flip-flop 1
6 to 18 and the clock CK from the multiplication circuit 20
After latching at three timings, it is given to the memories 21 and 22. The memories 21 and 22 control writing and reading by the control circuit 23. The control circuit 23 is supplied with a detection result of a phase error between the vertical synchronization signal VD1 and the vertical synchronization signal VD2 from the frame synchronization control circuit 19. The control circuit 23 writes the clock CK2 to the memory 21 and writes the horizontal synchronization signal HD2 to the memory 22. Then, based on the output of the frame synchronization control circuit 19, the control circuit 23 synchronizes the clock CK2 from the memories 21 and 22 with the timing of the clock CK3 in synchronization with the vertical synchronization signal VD1.
And read out the horizontal synchronizing signal HD2. FIG. 3H shows the clock CK2 from the memory 21, and FIG. 3I shows the horizontal synchronization signal HD2 from the memory 22.

The output of the memory 21 is the read control circuit 2
4, applied to the horizontal / vertical compression processing circuit 14 and the selection circuit 25,
The output of the memory 22 is provided to the horizontal / vertical compression / expansion circuit 13. The read control circuit 24 controls the read operation of the memory 12 based on the clock CK2 from the memories 21 and 22 and the flip-flop 16, the horizontal and vertical synchronization signals HD2 and VD2, and the comparison result of the frame synchronization control circuit 19.

As shown in FIG. 3H, the read control circuit 24 reads the video signal VIDEO2 from the memory 21 at the rising phase of the clock CK2. As a result, the digital video signal VID before the frame synchronization processing is
The phase relationship between EO2 and clock CK2 is also reproduced in the output of the memory 12.

Here, referring to FIG. 4, clock CK2
Will be described when clock skew occurs. The horizontal axis in FIG. 4 corresponds to the position in the horizontal direction of the screen.
4 indicate the sampling phase of the clock CK2, and the triangle indicates the sampling phase of the clock CK3.

Now, in the n-th line, three pixels a, b, and c continuous in the horizontal direction are sampled by the clock CK2 shown in FIG. 4D (FIG. 4).
(A)). These pixels are stored in the memory 12. In the next (n + 1) th line, as shown in FIG.
Clock skew occurs in the clock CK2 and the clock C
It is assumed that the sampling phase using K2 is delayed from the n-th line. In this case, as shown in FIG. 4B, the pixels a ', b', and c 'whose positions in the horizontal direction of the screen are shifted are stored in the memory 12. In the next (n + 2) th line, a ", b", and c "in FIG. 4C are stored in the memory 12 by the clock CK2 shown in FIG.

In the conventional example, since reading is performed using a synchronization signal based on the first image, pixels a ', b', and n 'at different horizontal pixel positions are provided for the (n + 1) th line.
c ′ represents pixels a and a ″, pixels b and b ″, and pixels c and c ″, respectively.
Will be displayed in the same horizontal position. That is, distortion occurs in the image.

On the other hand, in the present embodiment, the clock CK2 and the horizontal synchronizing signal HD2 are stored in the memories 21 and
2 and the clock CK obtained by multiplying the clock CK1
At timing 3, the data is read out in synchronization with the vertical synchronization signal VD 1, and the read clock CK 2 and horizontal reading signal HD 2 are used for reading out the memory 12.

That is, for the pixels a, b, and c, FIG.
The pixel a ', b', and c 'are read out at the timing of the clock CK3 of (e), and the clock C of FIG.
The pixel a ", b", and c "are read at the timing of K3, and the pixels a", b ", and c" are read at the timing of the clock CK3 of FIG.
b ″ and c ″ are read out at the phases indicated by triangles in FIGS. 4 (a) to 4 (c).

The reading of the memory 12 is performed by using the clock CK3
Timing horizontal synchronization signal HD2 and vertical synchronization signal VD
2, the video signal read from the memory 12 maintains the relationship between the original video of the second image and the clock skew. Further, the clock CK3 is synchronized with the horizontal synchronization signal HD1 of the first image, and reading from the memory 12 is started at the timing of the vertical synchronization signal VD1 using the clock CK3.
And the second image are subjected to frame synchronization processing and read from the memory 12. Further, the clock CK3
Is slightly different from the write timing by the clock CK2,
3, the effect of the shift is very small.

The horizontal / vertical expansion / compression circuit 13 operates in response to a clock CK2 from the memory 21 to perform horizontal compression / expansion processing on the frame synchronized video signal using the horizontal synchronization signal HD2. VD
2 to perform compression / decompression processing in the vertical direction. Thus,
The horizontal / vertical compression / expansion circuit 13 outputs, for example, an image shown on the right screen in FIG.

The images from the horizontal / vertical compression / expansion circuits 5 and 13 are supplied to a synthesis processing circuit 6. The selection circuit 25 performs the operation shown in FIG. 2C based on the horizontal synchronization signal HD1 obtained from the first image.
And generates an area signal indicating the horizontal image period of the right screen of the right side of FIG. In addition, the selection circuit 25 is configured as shown in FIG.
In (c), the clock CK1 is selected during the display of the left screen, and the clock CK2 from the memory 21 is selected during the display of the right screen, and output to the synthesis processing circuit 6 and the D / A converter 7. I do.

The synthesizing circuit 6 operates using the clock selected by the selecting circuit 25 to select the outputs of the horizontal / vertical compression / expansion circuits 5 and 13 according to the area signal.
The image is synthesized with a single image and output to the D / A converter 7. D / A
The converter 7 converts the input digital video signal into an analog signal and outputs the analog signal to the display monitor 8. The horizontal / vertical deflection circuit 26 generates horizontal and vertical deflection signals for controlling the display monitor 8 based on the horizontal synchronization signal HD1 and the vertical synchronization signal VD1 corresponding to the first image.
A composite image output from the A converter 7 is displayed.

As described above, in the present embodiment, when writing and reading out the second image from the memory for the frame synchronization processing, the phase relationship between the video signal and the clock is maintained after the frame synchronization processing. In this way, the composite image can be prevented from being distorted. Since the clock CK2 and the clock CK3 have an asynchronous relationship in the horizontal synchronization unit, the phase positions of the clock CK2 and the clock CK3 are not aligned in the vertical direction, so that one clock jitter occurs at the rate of the clock CK3. The frequency is sufficiently higher than the frequency of the clock CK2 and the influence is small.

FIG. 5 is a block diagram showing another embodiment of the present invention. 5, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the embodiment of FIG. 1, the horizontal / vertical compression / expansion processing is performed after the frame synchronization processing.
In the present embodiment, horizontal compression / expansion processing is performed by controlling a memory that performs frame synchronization processing.

In this embodiment, the horizontal / vertical compression / expansion circuit 13 is used.
1 in that a vertical compression / expansion circuit 30 is provided in place of the above, and a rising differentiation circuit 31, a write control circuit 32, and a read control circuit 33 are added.

The vertical compression / expansion circuit 30 compresses / expands the video signal read from the memory 12 in the vertical direction and outputs it to the synthesis processing circuit 6. The rising differentiating circuit 31 differentiates the rising of the clock CK2 from the flip-flop 16 and outputs a differentiated signal to the memory 21. The write control circuit 32 performs the same write control as the write control of the control circuit 23 so as to receive the vertical synchronization signal VD2 from the flip-flop 18 and write the differential signal into the memory 21.

Based on the vertical synchronizing signal VD 2 from the flip-flop 18 and the output of the frame synchronizing control circuit 19, the read control circuit 33 uses the horizontal synchronizing signal HD 2 after the frame synchronizing process output from the memory 22 and The horizontal compression is performed by controlling the horizontal read start position of the memory 21 and counting the read addresses of the memory 21 separately, and the horizontal expansion is performed by designating the same address continuously plural times. The horizontally compressed or horizontally expanded clock CK2 from the memory 21 is supplied to the read control circuit 24.

In the embodiment thus configured, the clock C output at the clock CK3 timing is used.
K2 is differentiated by the rising differentiating circuit 31. This differential signal is written into the memory 21 by the write control circuit 32. The read control circuit 33 reads the clock CK <b> 2 compressed or expanded in the horizontal direction from the memory 21 by controlling the read address of the memory 21 and supplies the clock CK <b> 2 to the read control circuit 24. The read control circuit 24 controls the read operation of the memory 12 using the clock CK2 from the memory 21, so that the video signal from the memory 12 is compressed or expanded in the horizontal direction.

Other operations are the same as those of the embodiment shown in FIG.

As described above, also in this embodiment, FIG.
The same effect as that of the embodiment can be obtained.

FIG. 6 is a block diagram showing another embodiment of the present invention.

In each of the above embodiments, the multiplication circuit 20
As a result, a clock having a frequency sufficiently higher than the clock CK1 is generated. Generally, oscillating and generating an extremely high frequency clock with an external crystal oscillator or the like may have a bad effect on other LSIs or the like, and is not realistic. On the other hand, a video clock used in digital broadcasting uses a frequency generated by free running of a crystal oscillator, for example, 27 MHz.
In such a case, DLL (Delay Locke)
d Loop).
It can be suitable for LSI. This embodiment is an example in which this type of DLL is adopted.

In the present embodiment, an example will be described in which an image obtained by decoding a digital broadcast stream signal and a current analog capture image are used as first and second images and a composite image of these two images is displayed. .

The input terminal 40 receives a transport stream (TS) reproduced from a digital broadcast signal, and the input terminal 41 receives a video signal of the current broadcast. The TS input from the input terminal 40 is supplied to the MPEG2 decoder 44. Crystal generator (X'ta
l) 45 generates a very stable clock with a frequency of 27 MHz. The MPEG2 decoder 44 uses the clock from the crystal generator 45 to input the input TS
, A horizontal synchronizing signal HD and a vertical synchronizing signal VD. The horizontal compression circuit 46 compresses the input video signal in the horizontal direction in synchronization with the horizontal synchronization signal HD in order to display two screens, and then outputs the video signal to the selector 63.

On the other hand, a video signal which is an analog captured image is supplied to an analog / digital converter (ADC) 50 via an input terminal 41. Also, the input terminals 42 and 43
Are supplied with horizontal and vertical synchronizing signals HD and VD based on the analog video signal inputted to the input terminal 41, respectively. The HPLL 51 multiplies the horizontal synchronization signal HD from the terminal 42 to generate a clock CLK. ADC 50 is
Using the clock CLK, the input analog video signal is sampled and output to the memory 70. Writing and reading of the memory 70 are controlled by a memory control circuit 71 to be described later, and the ADC 50 is controlled by using a clock CLK.
The output of is stored.

The HPLL 51 converts the clock CLK into each FF of the clock phase flip-flop (FF) group 52.
To the FFs of the HREF phase FF group 53.
Has given to.

The DLL 48 locks the output clock of the crystal oscillator 45 and outputs n + 1 delayed clocks (CK0 to CKn) at predetermined intervals from delay taps in the DLL 48.

FIG. 7 is a circuit diagram showing a specific configuration of DLL 48 in FIG.

The clock fin is input to the input terminal 81. The clock fin is transmitted via cascaded delay elements 84-1 to 84-n. The clock fin is also provided to the phase comparator 82, and the phase comparator 82
The phase of in is compared with the phase of the clock from the final-stage delay element 84-n, and the comparison result is output. The comparison result of the phase comparator 82 is supplied to the delay elements 84-1 to 84-n after band limitation by the filter 83.

The delay elements 84-1 to 84-n sequentially delay the clock input from the preceding stage based on the comparison result of the phase comparator 82 and output the delayed clock to the subsequent stage. That is, the delay element 8
In 4-1 to 84-n, the amount of delay is controlled based on the phase difference between the input clock fin and the clock from the delay element 84-n in the last stage, and the clock fin is delayed by one cycle in all stages.

The outputs of the delay elements 84-1 to 84-n are supplied to logic circuits 85-1 to 85-n, respectively. The logic circuits 85-1 to 85-n shape the outputs of the delay elements 84-1 to 84-n into one-shot pulses, and output the clocks CK0 and CK.
, CKn. Clock CK0, CK
, CKn are clocks having delays at a fixed interval from each other.

Each delayed clock from DLL 48 is
It is supplied to each FF of the groups 52 and 53. The FF group 52 outputs the analog clock CLK at each delayed clock timing from the DLL 48, and the FF group 53 outputs the HREF to the DLL.
48 at each delayed clock timing.

The output of each FF of the FF group 52 is provided to a parallel-serial (PS) converter 54, and the output of each FF of the FF group 53 is provided to a parallel-serial (PS) converter 55.
The PS converter 54 rearranges the output of each FF of the FF group 52 for each cycle of the clock CK and outputs the rearranged output to the FF 57. In addition, the PS converter 55 rearranges the output of each FF of the FF group 53 for each cycle of the clock CK and outputs the rearranged output to the FF 58.

On the other hand, each delay clock of the DLL 48 is supplied to the OR circuit 56, and the OR circuit 56 outputs the OR of each delay clock to the FFs 57 and 58, the memory 70 and the memory control circuit 71. The FFs 57 and 58 output the outputs of the PS converters 54 and 55 to the memories 59 and 60 at the clock timing from the OR circuit 56, respectively.

The frame synchronizing circuit 47 receives the vertical synchronizing signal VD based on the first image and the vertical synchronizing signal VD based on the second image from the terminal 43, detects these phases, and outputs the detection result. Based on the signals based on the memories 59 and 6
0 and output to the selector 63. The memories 59 and 60
Based on the output of the frame synchronization processing circuit 47, the stored clock is read and output to the SP converters 61 and 62, respectively. Thus, the outputs of the memories 59 and 60 are
Synchronized to G2 decoder.

The SP converters 61 and 62 are respectively provided in the memory 5
The outputs 9 and 60 are rearranged into the original time-series data and output to the memory control circuit 71, the selector 64 and the horizontal compression circuit 72. The memory control circuit 71 outputs a read enable signal for the memory 70 from the synchronized clock and the HREF signal.

The analog video signal read from the memory 70 has the same clock rate as the clock generated by the OR circuit 56, but the signal phase actually read is substantially equal to the original CLK phase. ing. Memory 70
The output is supplied to a horizontal compression circuit 72,
Are the clocks CLK and H from the SP converters 61 and 62.
Using REF, the video signal from the memory 70 is subjected to horizontal compression processing and output to the selector 63.

The selector 63 includes a horizontal compression processing circuit 46,
The output of 72 is switched and selected based on the switching signal from the frame synchronization processing circuit 47 and output to a digital-to-analog converter (DAC) 75. Also, the selector 64
Switches between the clock CLK from the SP converter 61 and the clock CK from the crystal oscillator 45 based on the output of the frame synchronization processing circuit 47, and outputs the clock to the DAC 75. The DAC 75 converts the video signal from the selector 63 into an analog signal using the clock from the selector 64 and outputs the analog signal to the monitor 77.

The deflection pulse generation circuit 76 receives horizontal and vertical synchronization signals HD and VD from the MPEG2 decoder, and controls horizontal and vertical deflection of the monitor 77 based on these signals HD and VD. Thus, a composite image based on the video signal from the DAC 75 is displayed on the display screen of the monitor 77.

Next, the operation of the embodiment configured as described above will be described with reference to the timing chart of FIG.

The TS input to the input terminal 40 is MPEG
The video signal is obtained by decoding with two decoders. The analog video signal input to the input terminal 41 is
The data is sampled by C50 and supplied to the memory 70.

The DLL is the 27 from the crystal oscillator 45.
The clocks CK0, CK1,..., CKn (FIG. 8) delayed at substantially equal intervals from the MHz clock (see FIG.
(B) to (g)) are generated. The HPLL 51 has a clock C based on a horizontal synchronization signal obtained from an analog video signal.
LK (FIG. 8 (i)) is reproduced. This clock CLK is supplied to each FF of the FF group 52, and the delayed clock (CK
0, CK1,..., CKn).
Thus, the signals shown in FIGS. 8J to 8O are obtained from each FF of the FF group 52.

The PS converter 54 converts the output of each FF of the FF group 52 from parallel to serial, and supplies the output to the memory 59 at the timing of the output (FIG. 8 (h)) of the logic circuit 56 by the FF 57. The memory 59 holds the values shown in FIG. Reading of the memory 59 is performed based on the output of the frame synchronization processing circuit 47.

In this way, the memory 59 stores information holding the relationship between the video signal and the skew of the clock CLK. This information is read out at a timing corresponding to the frame synchronization processing and supplied to the memory control circuit 71, and is also supplied to the DAC 75 via the selector 64.
The DAC 75 reads the data from the memory 59 and converts it into an analog video signal using the serial-to-parallel converted CLK, so that the composite image is read in a state where the relationship between the video signal and the skew of the clock CLK is preserved.

As described above, also in this embodiment, FIG.
The same effect as that of the embodiment can be obtained.

FIG. 9 is a block diagram showing another embodiment of the present invention.

This embodiment is an example in which a digital signal processor for video signals (hereinafter referred to as a DSP) is used to synthesize and output video signals of two systems.

A first input video signal and a first synchronizing signal synchronized with the first input video signal are input to input terminals 92 and 93 of the DSP 91. In addition, a second input video signal and a second synchronization signal synchronized with the second input video signal are input to the input terminals 94 and 95. Further, an external clock (external oscillation output) that is asynchronous with the first and second video signals is input to the input terminal 96 from an external oscillator (not shown). This external clock is supplied to the I / F unit 99 and the synchronization generation unit 1
00 to the memory control unit 101 and the I / F unit 104.

The first video signal and the first synchronizing signal are taken into the DSP 91 via an interface (hereinafter referred to as an I / F) 98. Similarly, the second input video signal and the second synchronization signal input to the input terminals 94 and 95 are I / O
The data is taken into the DSP 91 via the F section 99. That is, the I / F section 98 samples the input first video signal and first synchronization signal using an external clock, outputs the sampled signal to the data bus 97, and synchronously generates the first synchronization signal. Part 1
Supply to 00. Similarly, the I / F unit 99 samples the input second video signal and the second synchronization signal using an external clock, outputs the sampled signal to the data bus 97, and synchronously generates the second synchronization signal. To the unit 100.

The synchronization signal of each input system is guided to the memory control unit 101 via the data bus 97. Memory control unit 101
Generates a control signal for controlling the memory unit 102. The memory control signal generated by the memory control unit 101 is guided to the memory unit 102 via the data bus 97. Based on this control signal, the memory unit 102 performs video signal processing such as horizontal and vertical compression / expansion processing.

That is, the memory unit 102 captures the video signals from the I / F units 98 and 99 via the data bus 97 and stores them based on the memory control signal. Arithmetic unit 103
Reads and writes the video signal stored in the memory unit 102 via the data bus 97, and performs a predetermined arithmetic processing on the video signal.

The video signal processed by the arithmetic processing unit 103 is led to the I / F unit 104 via the data bus 97. I
The / F unit 104 outputs the video signal to the output terminal 1 based on the synchronization signal generated by the synchronization generation unit 100 and the external clock.
Output to 05.

As described above, in the present embodiment, D
With the SP configuration, clock signals on the data bus can be unified. Also, the I / F unit 104 can output a video signal using a stable external clock. Therefore, even when the horizontal synchronizing signal of one input video signal is unstable due to a non-standard signal or the like, there is no delay difference between the video signal and the synchronizing signal. Similar to the embodiment, it is possible to realize good image display.

In the above embodiment, the DSP
An example has been shown in which the output of an external oscillator is used as a clock signal for transmission of a data bus and for outputting a video signal using the above. However, similarly to the embodiment of FIG. 1, a clock signal synchronized with any one of the plurality of input video signals may be used as a clock signal for data bus transmission and a video signal output. Good display images can be obtained.

[0097]

As described above, according to the present invention, even when a clock skew of the horizontal synchronizing clock occurs, a display shift in the horizontal direction of the video is prevented from occurring in the frame synchronization processing, thereby suppressing the image quality deterioration. It has the effect that it can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a video signal processing device according to the present invention.

FIG. 2 is an explanatory diagram illustrating an embodiment.

FIG. 3 is a timing chart illustrating operation of the embodiment.

FIG. 4 is a timing chart illustrating operation of the embodiment.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a block diagram showing another embodiment of the present invention.

FIG. 7 is a circuit diagram showing a specific configuration of a DLL 48 in FIG. 6;

FIG. 8 is a timing chart for explaining the operation of the embodiment in FIG. 6;

FIG. 9 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

3 ... MPEG decoder, 4 ... NTSC decoder, 5,1
3: horizontal / vertical compression / expansion circuit, 6: synthesis processing circuit, 7: D
/ A converters, 12, 21, 22 ... memories, 14 ... clock generation circuits, 15 ... write control circuits, 16-18 ... flip-flops, 19 ... frame synchronization control circuits, 2
0 ... multiplier circuit, 23 ... control circuit, 24 ... read control circuit, 25 ... selection circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Suzuki 3-3-9, Shimbashi, Minato-ku, Tokyo Toshiba Abu E Co., Ltd. F-term (reference) 5C020 AA13 BA07 BA11 5C023 AA14 AA38 BA11 CA03 DA04 EA16 5C025 BA27 BA28 CA06 DA01

Claims (7)

[Claims] 1. A first clock generating means for generating a first clock phase-synchronized with a horizontal synchronizing signal of an input television signal, and a first clock storing the input television signal using the first clock. Storage means; fixed clock oscillation of a second clock having a predetermined frequency higher than the first clock; and second storage means for storing the horizontal synchronization signal using the second clock. Storage means; third storage means for storing the first clock using the second clock; and the horizontal synchronization signal stored in the second storage means and the third storage means. Control means for controlling the readout phase of the first storage means based on the first clock. 2. A first clock generating means for generating a first clock phase-synchronized with a horizontal synchronizing signal of an input television signal, and a first storing the input television signal using the first clock. Storage means; fixed clock oscillation of a second clock having a predetermined frequency higher than the first clock; and second storage means for storing the horizontal synchronization signal using the second clock. Storage means; edge extraction means for extracting an edge of the first clock using the second clock and outputting an edge signal; memory for storing the edge signal using the second clock; The read start position of the memory is controlled using the horizontal synchronization signal stored in the second storage means, and the first write position is controlled based on the edge signal read from the memory. Means a video signal processing apparatus, wherein a has a control means for controlling reading of said input television signal stored. 3. The memory is capable of random access, and the control means controls a read address of the edge signal stored in the memory, thereby variably changing a cycle of an edge signal output from the memory. The video signal processing device according to claim 2, wherein 4. A digital-to-analog conversion means for converting the input television signal read by the control means into an analog signal using the first clock or an edge signal extracted from the first clock. The video signal processing device according to claim 1, wherein: 5. A delay clock generating means for generating a plurality of delay clocks in one period by delaying a fixed period of a reference clock with the same delay amount, and generating a first clock of a first video signal. A first flip-flop group that outputs at a plurality of delay clock timings, a second flip-flop group that outputs a horizontal synchronization signal of the first video signal at the plurality of delay clock timings, and the first video signal A first storage unit for storing the first clock and the horizontal synchronization signal from the second storage unit; a second storage unit for storing the outputs of the first and second flip-flop groups; Reading means for reading, and reading the first video signal from the first storage means using the first clock and horizontal synchronization signal read from the second storage means. A video signal processing device comprising: 6. A first compression unit for compressing the first video signal read from the first storage unit, and a second compression unit for compressing a second video signal different from the first video signal. 2 based on a horizontal synchronizing signal of the second video signal.
6. The video signal processing apparatus according to claim 5, further comprising a selection unit for switching and outputting between the output of the compression unit and the output of the second compression unit. 7. A clock selection for switching and outputting the first clock read from the second storage means and a second clock based on the second video signal in accordance with the selection of the selection means. 7. The video signal processing device according to claim 6, further comprising: a digital-to-analog converting unit configured to convert a video signal from the selecting unit into an analog signal using a clock from the clock selecting unit. .