JPH06197274A - Picture expansion processor - Google Patents

Abstract

PURPOSE:To obtain a picture expansion processor with less degradation in picture quality attended with the expansion processing of a picture. CONSTITUTION:Input video data are written in a field memory 9 having two pot outputs. A 1st read control circuit 14 reads data stored in the memory 9 through the 1st output port 40 of the memory 9 at a phase delayed by 1/2V+alpha from the phase of a synchronous signal of an input video signal. A 2nd read control circuit 16 reads data stored in the memory 9 through the 2nd output port 40 of the memory 9 at a phase delayed by 1/2V+alpha from the phase of the synchronous signal of the input video signal so as to obtain an expanded picture. Then a switching circuit 22 controlled by the output of a blanking signal generating circuit 24 replaces a synchronous signal equivalent portion in the video signal of an expanded picture read through the 2nd output port is replaced with the synchronous signal of the video signal read through the 1st output port. Thus, a write address does not outrace a read address and no lateral line is caused on a screen.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for enlarging an image used in a VTR integrated camera, a video effector and the like.

[0002]

2. Description of the Related Art In recent years, video effectors that can add special effects such as zoom, strobe, and mosaic to video signals by using digital signal processing technology are being commercialized at low prices. Since these products are produced at a low price, in many cases, a digital signal processing circuit is equipped with a field memory, and various special effects using the field memory can be performed.

(Conventional Example 1) A circuit of a conventional example 1 which performs a special effect of image enlargement (also referred to as electronic zoom) will be described. In FIG. 6, a sync separation circuit 4 separates a horizontal sync signal and a vertical sync signal from an input video signal, and a clock generation circuit 6 generates a system clock based on the separated sync signal. From the system clock, the write control circuit 10 generates a write address signal for writing the input video signal in the field memory 8 (hereinafter also referred to as a memory), and outputs the write address signal to the memory 8.

The input video signal is converted into a digital signal in the A / D converter 2 and then written in the memory 8 in accordance with the write address signal. In this way, the video signal for one field is stored in the memory 8.

The video signal stored in the memory 8 is read according to the read address signal of the read control circuit 12 which is set by the enlargement ratio of the image, is interpolated by the interpolation processing circuit 20, and is then switched by the switch 22. The portion corresponding to the sync signal of the video signal that has undergone the enlargement signal processing,
The D / A converter 26 is replaced by the sync signal of the input video signal.
Is converted into an analog signal and output.

Next, the read control when the central portion of the screen is doubled will be described. As shown in FIG. 7A, in order to enlarge the screen twice, the reading is started from the point A in the figure, the data in the memory 8 is read twice, and the 1/2 horizontal video signal section is read. Then, the same data is read again in the video signal section of the next horizontal scan.
By this operation, the image of the signal in the 1/2 horizontal video signal section of the original video signal is doubled in the horizontal direction and doubled in the vertical direction. By repeating such control, the central portion of the screen can be doubled. However, since the sync signal disappears as it is, the sync signal equivalent portion of the enlarged video signal is replaced with the sync signal portion of the input video signal before being output.

(Conventional Example 2) The circuit of Conventional Example 2 will be described with reference to FIG. The sync separation circuit 4 separates the horizontal sync signal and the vertical sync signal from the input video signal, and the clock generation circuit 6 generates a system clock based on the separated sync signal. The write control circuit 10 generates a write address signal for writing the input video signal in the field memory 8 and outputs it to the memory 8. The input video signal is converted into a digital signal in the A / D converter 2 and then written in the memory 8 in accordance with the write address signal.
In this way, the video signal for one field is stored in the memory 8.

The video signal stored in the memory 8 is read in accordance with the read address signal of the read control circuit 12 set by the enlargement ratio of the image, is interpolated by the interpolation processing circuit 20, and then is switched by the switch 22. The portion corresponding to the sync signal of the enlarged video signal is replaced with the sync signal of the input video signal, converted into an analog signal by the D / A converter 26, and output.

Next, the read control when the central portion of the screen is doubled by the image enlargement processing will be described.
As shown in FIG. 11B, when the image data is enlarged to double, the same video data, for example, a is read twice a and a from the memory 8 and a 1/2 horizontal video signal section is read.
The same data is read again in the video signal section of the next horizontal scan. By this operation, the image in the 1/2 horizontal video signal section of the original video signal is doubled in the horizontal direction and doubled in the vertical direction.
It has been doubled. By repeating such control, the central portion of the screen can be doubled.

When the image is enlarged four times, the same data is read from the memory 8 four times as shown in (c), and when the 1/4 horizontal image signal section is read out, the image of the next horizontal scanning is obtained. The same data is read from the signal section to the 3 horizontal scanning video signal section. By this operation, the image in the 1/4 horizontal video signal section of the original video signal is expanded four times in the horizontal direction and four times in the vertical direction. By repeating such control, the central portion of the screen can be enlarged four times.

(Conventional Example 3) Next, a circuit of Conventional Example 3 for performing image enlargement processing will be described. In FIG. 13, a sync separation circuit 4 separates a horizontal sync signal and a vertical sync signal from an input video signal, and a clock generation circuit 6 generates a system clock based on this separated sync signal. From the system clock, the write control circuit 10 generates a write address signal for writing the input video signal in the field memory 8 and outputs it to the memory 8.

The input video signal is converted into a digital signal in the A / D converter 2 and then written in the memory 8 in accordance with the write address signal. In this way, the video signal for one field is stored in the memory 8.

The video signal stored in the memory 8 is read in accordance with the read address signal of the read control circuit 12 set by the magnification of the image and is interpolated by the interpolation processing circuit 20, and then the image is displayed by the switch 22. The portion corresponding to the sync signal of the enlarged video signal is replaced with the sync signal of the input video signal, converted into an analog signal by the D / A converter 26, and output.

Next, the read control when the central portion of the screen is doubled by the image enlargement processing will be described.
In order to double the screen, the data in the memory 8 is read twice from the read point, and once the 1/2 horizontal video signal section is read, the same data is read again in the next horizontal scanning video signal section. . By this operation,
The signal in the 1/2 horizontal video signal section of the original video signal is doubled in the horizontal direction and doubled in the vertical direction. By repeating such control, the central portion of the screen can be doubled. However, if the enlargement ratio is increased as it is, a large block is formed with pixels of the same data, and a mosaic image is formed. Therefore, interpolation processing is performed by the interpolation processing circuit 20. Especially, the pixel interval in the vertical direction is wider than that in the horizontal direction, and the deterioration of image quality is conspicuous. Therefore, as shown in FIG. 14, an average value interpolation process for obtaining an average value with the pixels of the immediately preceding line is performed to obtain a smooth image.

(Prior Art Example 4) In consumer equipment, a large-capacity memory is expensive, so when the input video signal is digitized and stored in the memory, the data is compressed to reduce the information amount of the signal. The data is stored in the memory, the data is read from the memory, the data is expanded, and the original signal is restored to save the memory. A circuit of Conventional Example 4 that performs image enlargement processing while performing such signal processing will be described.

In FIG. 16, a sync separation circuit 4 separates a horizontal sync signal and a vertical sync signal from an input video signal, and a clock generation circuit 6 generates a system clock based on the separated sync signal. The write control circuit 10 generates a write address signal for writing the input video signal in the field memory 8 from the synchronization signal and the system clock, and outputs the write address signal to the memory 8. The input video signal is converted into a digital signal in the A / D converter 2 and is compressed to 1 / n in the compression circuit 218.
It is written in the memory 8 in accordance with the write address signal. In this way, the video signal for one field is stored in the memory 8.

The video signal stored in the memory 8 is read in accordance with the read address signal of the read control circuit 12 set by the magnification of the image, and the decompression circuit 22 is read.
At 0, it is expanded to n times, then is interpolated by the interpolation processing circuit 21, and the switch circuit 22 replaces the portion corresponding to the synchronizing signal of the image signal subjected to the image enlargement processing with the synchronizing signal of the input image signal. The converter 26 converts into an analog signal and outputs it.

[0018]

However, the conventional examples 1 to 4 have the following problems.

(Regarding Conventional Example 1) In the image enlargement processing by the circuit configuration of Conventional Example 1, as shown in FIG. 7C, when a moving image is present, an image with a time difference of 1 field is generated on the screen. It appears, and there is a problem that the boundary of it looks like a horizontal line.

This problem occurs because the write address signal overtakes the read address signal on the way. That is, as shown in FIG. 7B, since the write address signal moves from B to B'while the read address signal moves from A to A ', the write address overtakes the read address in the middle of the screen. . The video signal one field before is output until the write address overtakes the read address, but when the write address overtakes the read address, the video signal immediately after writing is output, and the write address overtakes the read address. The video signal read at the moment
Move back and forth in the field.

(Regarding Conventional Example 2) In the image enlargement processing by the circuit configuration of Conventional Example 2, as shown in FIGS. 11 (b) and 11 (c), if the enlargement magnification is increased, one same data is obtained. Since the pixel block becomes large, the image becomes a mosaic shape, and the luminance signal shift between the odd (Odd) field image and the even (Even) field image becomes large, which causes flicker at 30 Hz and flickers. There is a problem that the image becomes very difficult to see.

(Regarding Conventional Example 3) In Conventional Example 3, there is a problem in that, by performing the average value interpolation process, a sharp change in the signal becomes gradual and the edges of the image appear blurred.

(Regarding Conventional Example 4) In the circuit configuration of Conventional Example 4, since the compression process and the decompression process are performed, the image quality is deteriorated to some extent, and the deteriorated image is further controlled by the read control circuit 12. When a part of the image is enlarged by, the image quality of the enlarged image deteriorates greatly as the enlargement ratio increases.

For example, a high resolution television, VTR or V
Due to the higher resolution of TR integrated cameras, a sampling frequency of 14.3 MHz is often used when digitizing an input video signal in order to maintain image quality. Along with it 1
The amount of information of the video signal in the field is greatly increased and a large number of memories are required. Therefore, in order to save the memory capacity, a study has been made to compress the input video signal in half to reduce the memory, and as a compression method, a method of halving the sampling frequency to halve the information of the input video signal. In addition, the information of the signal is set to 1 by utilizing the correlation between adjacent pixels of the input video signal called DPCM (predictive coding).
Various proposals have been made such as a method of compressing to 1/2. However, the signal that is restored after being compressed is always a signal that is deteriorated compared to the original signal, depending on the compression method. If the sampling frequency is halved, the resolution is degraded to ½, and in the case of DPCM, a phenomenon called edge business may appear. When enlarging such a deteriorated image, there is a problem that the image quality is further deteriorated as the enlargement ratio is increased (see FIG. 17).

The present invention has been made under such circumstances, and it is an object of the present invention to provide an image enlarging processing apparatus in which the deterioration of the image quality due to the image enlarging processing is small.

[0026]

In order to achieve the above object, the present invention provides an image enlarging processing device as follows.
Configure as in (5).

(1) An image enlarging processing device for enlarging an image using an image memory, which is an image memory capable of asynchronously outputting data stored in two output ports, and an image memory From the write control means for controlling the writing of the input video signal and the first output port of the image memory, about 1/2 of the writing phase of the input video signal
First read control means for controlling to read data at a phase delayed by a field and a second output port of the image memory at a phase delayed by about 1/2 field from a write phase of an input video signal, And second read control means for controlling to read the enlarged image data, switching means for switching and outputting the data of the first output port and the data of the second output port, and the first The switching means is arranged so that the data of the first output port is output during the blanking period of the video signal of the output port, and the data of the second output port is output during the periods other than the blanking period. An image enlargement processing apparatus comprising a switching control means for switching.

(2) An image enlarging processing device for enlarging an image using an image memory, the image memory storing an input video signal, and a writing control for controlling writing of the input video signal to the image memory. Means, read control means for reading the expanded image data from the image memory at a phase delayed by about 1/2 field from the write phase of the input video signal, and about 1/2 of the input video signal. A signal generating means for generating a decoding synchronizing signal and a blanking signal delayed by a field, a switching means for switching and outputting the output data of the image memory and the output signal of the signal generating means, and the blanking signal for blanking. Output data of the image memory except the blanking period so that the output signal of the signal generating means is output during the period. Image enlarging processing apparatus that includes a switching control means for switching the switching means to output.

(3) An image enlarging processing device for writing an interlace type video signal which constitutes one screen with two fields into an image memory, and enlarging an image using the image memory. Image enlargement including a read control unit that reads the stored image data by shifting the timing by reading the odd field and the even field by the number of lines corresponding to the magnification of the image enlargement. Processing equipment.

(4) An image enlarging processing device for enlarging an image using an image memory, wherein the signal level difference between adjacent pixels in the vertical and / or horizontal direction of the enlarged video signal is An image enlarging processing device provided with an interpolating means that performs average value interpolation when the threshold value is smaller than a predetermined threshold value and performs pre-value interpolation when the threshold value is larger than the predetermined threshold value.

(5) An image enlarging processing device for enlarging an image using an image memory, the enlarging magnification being a predetermined value n.
And a second processing system that performs processing when the enlargement magnification is equal to or greater than the predetermined value n, the first processing system including the video signal data. The second processing system is a processing system that performs compression processing to 1 / n, stores it in the image memory, enlarges and reads it from the image memory according to an enlargement ratio, and performs expansion processing and outputs the image signal data. Is stored in the image memory without being subjected to compression processing, and is enlarged and read out from the image memory in accordance with the enlargement ratio, and is output.

[0032]

In the configurations (1) and (2), the write address does not overtake the read address. With the configuration of (3), the difference between the luminance signals of the odd field and the even field is reduced. With the configuration (4), the blurring of the edge of the image is reduced. In the configuration of (5), when the enlargement ratio of the image is equal to or larger than the predetermined value n, the compression / expansion process is not performed.

[0033]

EXAMPLES The present invention will be described in detail below with reference to examples.
Note that Examples 1 to 3 correspond to Conventional Example 1, Example 4 to Conventional Example 2, Examples 5 and 6 to Conventional Example 3, and Example 7.
Correspond to Conventional Example 4, respectively.

(Embodiment 1) FIG. 1 is a block diagram of an "image enlargement processing apparatus" which is Embodiment 1. In the figure, 2 is an A / D converter for converting an input video signal into a digital signal, 4 is a sync separation circuit for separating a horizontal sync signal and a vertical sync signal from the input video signal, and 6 is this separation It is a clock generation circuit that generates a system clock based on the generated synchronization signal. Reference numeral 9 is a memory (field memory) having two output ports for storing the above-mentioned input video digital signal, and 10 is writing for writing the input video signal in the memory 9 from the synchronization signal and the system clock. A write control circuit for generating an address signal, 14 is a first read control circuit for reading a video signal stored in the memory 9 in a phase delayed by 1 / 2.V (described later), and 16 is stored in the memory 9. The second read control circuit 16 reads out the read video signal at a phase delayed by 1/2 · V and magnifies the image to a set magnification, and 20 is read by the second read control circuit 16. It is an interpolation processing circuit for interpolating the video signal of the enlarged image. Reference numeral 22 is a switch circuit for replacing a portion corresponding to the sync signal of the video signal of the enlarged image subjected to the interpolation processing with the sync signal of the input video signal, and 24 is for controlling the switch circuit 22 by using the sync signal and the system. A blanking signal generation circuit that generates a blanking signal from a clock, and 26 is a D / A converter that converts the output video signal of the switch circuit 22 into an analog signal.

Next, the operation will be described.

Since the write operation is the same as that described in the first conventional example, the read operation will be described.
In the first read control circuit 14, as shown in FIG. 2B, the first read of the field memory 9 having the 2-port output is performed.
The first read address signal is generated from the output port 40 to read the data stored in the memory 9 in a phase delayed by 1 / 2.multidot.V + .alpha. From the synchronizing signal of the input video signal. Here, V is the time for scanning one field, which is about 63.5 μsec in the case of the NTSC signal. Further, α is an arbitrary time convenient for the circuit configuration.

In the second read control circuit 16,
As in the case of the first read address signal, as shown in FIG. 2C, the phase is delayed by ½ · V + α from the sync signal of the input video signal, and the second magnification is set by the image enlargement ratio. Generate a read address signal. This second
The control of the read address signal is the same as that described in the conventional example 1 when the central part of the screen is doubled. The memory 9 according to the second read address signal
The video signal of the enlarged image read out from the second output port 42 is mosaic-like and unsightly as it is, and therefore is interpolated by the interpolation processing circuit 20 to be smooth, and then input to the switch circuit 22. The video signal read from the first output port 40 of the memory 9 by the first read address signal is also input to the switch circuit 22, and the blanking signal 50 generated by the blanking generation circuit 24 causes the switch circuit to switch. 22 is switched, and the portion corresponding to the sync signal in the video signal of the enlarged image subjected to the interpolation processing is replaced with the sync signal of the input video signal. Then, the video signal of the enlarged image to which the synchronization signal is added is converted to an analog video signal by the D / A converter 26 and then output to the outside.

By controlling in this manner, the write address signal does not overtake the read address signal in the middle of the screen, and the image drooling is eliminated.

As described above, according to this embodiment,
A 2-port output field memory is used, and the read address signal is about 1/2 of the write address signal.
By delaying V time, even if the central portion of the screen is enlarged from 1 to 2 times or 4 times by the image enlargement processing,
Since the write address signal does not overtake the read address signal in the middle of the screen, images one field before and one field after the other are mixed in the screen, and development that looks like a horizontal line can be prevented from occurring.

(Embodiment 2) FIG. 3 shows the configuration of Embodiment 2. In FIG. 3, an A / D converter 2, a sync separation circuit 4,
The operations of the clock generation circuit 6, the write control circuit 10, and the first read control circuit 14 are the same as those in the first embodiment. Therefore, the first read address signal causes the first output port 40 of the field memory 9 having a two-port output to output 1 / th of the sync signal of the input video signal.
The data stored in the memory 9 is read out with a phase delayed by 2 · V + α. The second sync separation circuit 5 separates a horizontal sync signal and a vertical sync signal from the data read from the first output port 40 of the field memory 9, and the second read control circuit 17 generates a clock. A second read address signal is generated from the system clock generated by the circuit 6 and the horizontal synchronization signal and the vertical synchronization signal separated by the second synchronization separation circuit 5, and the memory 9 is generated.
Output to. The control of the second read address signal is the same as that described in the first embodiment. A blanking signal generating circuit 24 generates a blanking signal from the system clock generated by the clock generating circuit 6 and the horizontal synchronizing signal and the vertical synchronizing signal separated by the second synchronizing separating circuit 5, and a switch circuit. 22 is output. Even with such a configuration, the same effect as that of the first embodiment can be obtained.

(Embodiment 3) FIG. 4 shows the configuration of the present embodiment. In the figure, 2 is an A / D converter for converting an input video signal into a digital signal, 4 is a sync separation circuit for separating a horizontal sync signal and a vertical sync signal from the input video signal, and 6 is the separated signal. A clock generation circuit that generates a system clock based on a synchronization signal, 8 is a field memory that stores the above-mentioned input video digital signal, and 10 is based on the synchronization signal and the system clock.
A write control circuit for generating a write address signal for writing the input video signal in the memory 8, and 13 denotes the video signal stored in the memory 8 about 1 / th of the input video signal.
It is a control circuit that reads out an image at a phase delayed by 2.V and by enlarging the image to a set magnification. Reference numeral 56 is a signal generator for generating a blanking signal and a composite synchronizing signal having a phase delayed by about 1 / 2.V from the synchronizing signal of the input video signal.
Reference numeral 0 denotes an interpolation processing circuit for interpolating the video signal of the enlarged image read by the read control circuit 13, and 2
Reference numeral 2 is a switch circuit for replacing the portion corresponding to the synchronization signal of the video signal of the enlarged image subjected to the above-mentioned interpolation with the composite synchronization signal output from the signal generator 56, and 26 is the output of the switch circuit 22 for image enlargement. It is a D / A converter that converts the processed video signal into an analog signal.

Next, the operation will be described.

Since the write operation is the same as that described in the first conventional example, the read operation will be described.
In the read control circuit 13, as shown in FIG. 5D, the data stored in the memory 8 is set to the set magnification with a phase delayed by 1 / 2.V + α from the synchronizing signal of the input video signal. A read address signal is generated so as to be enlarged and read. The control of the read address signal is the same as that described in the conventional example 1 when the central portion of the screen is enlarged to double. The video signal of the enlarged image read from the memory 8 by the read address signal is mosaic-like and unsightly as it is, so the interpolation processing circuit 2
When the value is 0, the interpolation processing is performed so as to be smooth, and the result is output to the switch circuit 22. The switch circuit 22 uses the blanking signal generated by the signal generator 56 to convert a portion corresponding to the synchronization signal of the video signal of the above-described interpolated enlarged image into the composite synchronization signal generated by the signal generator 56. Replace. Then, the video signal of the enlarged image to which the synchronization signal is added is converted to an analog video signal by the D / A converter 26 and then output to the outside.

By controlling in this way, the write address signal does not overtake the read address signal in the middle of the screen, and the same effect as in the first embodiment can be obtained.

(Embodiment 4) FIG. 8 shows the configuration of the fourth embodiment. In FIG. 8, 2 is an A / D converter for converting an input video signal into a digital signal, 4 is a sync separation circuit for separating a horizontal sync signal and a vertical sync signal from the input video signal, and 6 is the above-mentioned A clock generation circuit that generates a system clock based on the separated synchronization signal. Reference numeral 8 denotes a memory for storing the input video digital signal, and 10 denotes the synchronization signal and the system clock.
A write control circuit for generating a write address signal for writing an input video signal in the memory 8 and a read control circuit 32 for reading out the video signal stored in the memory 8. Reference numeral 20 is an interpolation processing circuit for interpolating the video signal of the enlarged image read by the read control circuit 32, and 22 is a portion corresponding to the sync signal of the video signal of the enlarged image subjected to the above-mentioned interpolation, in synchronization with the input video signal A switch circuit which is replaced by a signal, and 24 is the switch circuit 2
Reference numeral 26 denotes a blanking signal generation circuit for generating a blanking signal from the synchronization signal and the system clock in order to control switching of the switch No. 2, and D / which converts an output video signal of the switch circuit 22 into an analog signal.
A converter.

Next, the operation will be described.

Since the write operation is the same as that described in the second conventional example, the read operation will be described for the case where the image is magnified four times. The image by the video signal in the 61 horizontal scanning period from the nth line to the (n + 60) th line of the input video signal is enlarged four times in the vertical direction of the screen, and is enlarged from the 18th line to the 260th line. At this time, in the case of an odd field, as shown in FIG. 9B, the data of the nth line stored in the memory 8 is read four times during the four horizontal scanning periods from the 18th line to the 21st line, Then, the read address control of reading the data of the (n + 1) th line four times during the four horizontal scanning periods from the 22nd line to the 25th line is repeated. Next, in the case of the even field, the data of the nth line stored in the memory 8 is transferred from the (18 + k) th line to the (21 + th) line.
The data of the (n + 1) th line is read four times during the four horizontal scanning periods of the (k) line, and then the data of the (n + 1) th line is read four times during the four horizontal scanning periods of the (22 + k) th line to the (25 + k) th line. The read address control is performed by shifting the read address control by k lines from the read timing in the odd field. When the image enlargement magnification is 4, the value of k is appropriately 2 as shown in the figure, and the image becomes easier to see if the value of k is increased as the image enlargement magnification increases.

As described above, according to this embodiment,
According to the magnification of the image enlargement, the timing of reading the signal stored in the memory means is shifted by k lines when reading the odd field and when reading the even field. The area where the odd-field luminance signal and the even-field luminance signal deviate from each other in the video signal becomes small, and the 30 Hz flicker becomes less noticeable.

(Embodiment 5) FIG. 12 is a block diagram of an interpolation circuit in this embodiment. The configuration is the same as that of FIG. 13 except for the interpolation circuit. The signal read from the memory 8 according to the magnification of the image enlargement is input to the interpolation circuit of FIG. 12, delayed by the 1-line delay circuit 122, and then added by the adder 1.
24 and the subtractor 126. The adder 124 adds the output signal of the 1-line delay circuit 122 and the signal read from the memory 8 and outputs the added signal to the sub-multiplier 128. The divider 128 calculates the input signal by half and outputs it to the switch circuit 130. On the other hand, the subtractor 126 obtains the difference between the output signal of the 1-line delay circuit 122 and the signal read from the memory 8, and outputs the absolute value to the discriminating circuit 132. In the discrimination circuit 132, the level of the input signal,
The threshold value set in advance is compared and the result is output to the switch circuit 130. That is, the determination circuit 13
Reference numeral 2 denotes an output signal of the divider 128 when the level difference between the input video signal and the video signal delayed by one line is smaller than the set threshold value, and when it is larger, the signal read from the memory 8. The switch circuit 130 is controlled so as to output as is.

By controlling in this manner, the signal levels of the pixel of the current line and the pixel of the preceding line are compared, and when the level difference is larger than the set threshold value, that is, at the image edge, the average value interpolation is performed. Then, pre-value interpolation (also referred to as pre-hold interpolation) is performed to prevent blurring of the edges of the image, and mean-value interpolation is performed at portions other than the edges to prevent the image from appearing like a mosaic.

(Sixth Embodiment) The fifth embodiment relates to the interpolation processing in the vertical direction of the screen, but the same method can be applied to the interpolation processing in the horizontal direction of the screen. That is, FIG.
In the above, the delay circuit 122 may be delayed by one pixel. If the interpolation circuit of the fifth embodiment and the interpolation circuit of the present embodiment are connected in series, the same effect can be obtained in both the vertical and horizontal directions of the screen.

(Embodiment 7) FIG. 15 shows the configuration of Embodiment 7. In the figure, 2 is an A / D converter for converting an input video signal into a digital signal, 4 is a sync separation circuit for separating a horizontal sync signal and a vertical sync signal from the input video signal, and 6 is separated. It is a clock generation circuit that generates a system clock based on the synchronized signal. Reference numeral 218 is a compression circuit for compressing the digitized input video signal to 1 / n, and reference numeral 32 is a pre-lowpass filter for removing folding noise generated when the enlargement ratio is increased. Reference numeral 228 is a first switch circuit for switching between the signal compressed by the compression circuit 218 and the output of the pre-low-pass filter 232 according to a switching signal controlled by a magnification. Reference numeral 8 is a memory for storing the input video digital signal switched by the switch circuit 228, and 10 is a write for generating a write address signal for writing the input video signal in the memory 8 from the synchronization signal and the system clock. Reference numeral 12 denotes a control circuit, which is a read control circuit for enlarging and reading the video signal stored in the memory 8 to a set magnification.
Reference numeral 220 denotes a decompression circuit that decompresses an input signal compressed to 1 / n to n times to restore the original signal, and 230 denotes a video signal decompressed by the decompression circuit 220 and a signal output from the memory 8. Is a second switch circuit for switching according to a switching signal controlled by the enlargement ratio.
Reference numeral 21 denotes an interpolation processing circuit for interpolating the video signal of the enlarged image which is the output of the second switch circuit 230,
Reference numeral 22 is a third switch circuit for replacing a portion corresponding to the sync signal in the video signal of the enlarged image subjected to the interpolation processing with the sync signal of the input video signal. Reference numeral 26 is a blanking signal generation circuit that generates a blanking signal from the synchronization signal and the system clock in order to control the third switch circuit 22, and 26 is an output video signal of the switch circuit 24 that is an analog signal. It is a D / A converter for conversion.

Next, the operation will be described.

When the expansion ratio of the input signal is smaller than the predetermined n times, the compression circuit 2 is operated similarly to the operation of the circuit of the conventional example 4.
It is compressed to 1 / n at 18 and then stored in the memory 8. 1 /
By compressing to n, the capacity of the memory 8 can be reduced to 1 / n. Next, when the magnification of the input signal becomes n times or more, the enlarged video signal is only 1 / n or less of the entire input video signal, so if the position of the signal to be enlarged is known in advance, only that video signal By controlling so as to be stored in the memory 8, the input video signal can be sufficiently stored in the memory 8 without being compressed.

As described above, in the present embodiment, when the magnification of the image of the input video signal is from 1 to a predetermined n times (horizontal direction √n times, vertical direction √n times), The input video signal is compressed to 1 / n by the compression circuit and stored in the memory to reduce the memory capacity. In this way, when the enlargement ratio is small, the amount of information of the original signal is large even if the compression circuit compresses it to 1 / n, so that the image quality deterioration due to the compression is not noticeable. On the other hand, when the enlargement ratio becomes n times or more, the required signal in the original input video signal becomes 1 / n or less of the entire input video signal, so the input video signal should be expanded without being compressed. By controlling so that only partial signals are written to the memory, it is possible to store the necessary signals without changing the memory capacity, and to prevent image quality deterioration of the video due to compression when the enlargement ratio is large. You can

By thus saving the capacity of the memory, it is possible to minimize the deterioration of the image quality while reducing the cost.

[0057]

As described above, according to the present invention,
It is possible to provide an image enlarging processing device in which image quality deterioration due to image enlarging processing is small.

More specifically, according to the first and second aspects of the present invention, images one field before and one field after are mixed on the screen, and development which looks like horizontal lines can be prevented. According to the invention described above, the flicker at 30 Hz becomes less noticeable, and according to the invention described in claim 4, it is possible to prevent the edges of the image from being blurred, and to prevent the image from appearing in a mosaic pattern at a place other than the edges. According to the invention of claim 5, the capacity of the memory can be saved, and the deterioration of the image quality can be suppressed to the minimum.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a timing chart of each signal in the first embodiment.

FIG. 3 is a block diagram of a second embodiment.

FIG. 4 is a block diagram of a third embodiment.

FIG. 5 is a timing chart of each signal in the third embodiment.

FIG. 6 is a block diagram of Conventional Example 1.

FIG. 7 is an operation explanatory diagram of Conventional Example 1.

FIG. 8 is a block diagram of a fourth embodiment.

FIG. 9 is an operation explanatory diagram of the fourth embodiment.

FIG. 10 is a block diagram of Conventional Example 2.

FIG. 11 is an operation explanatory diagram of Conventional Example 2.

FIG. 12 is a block diagram of an interpolation circuit in the fifth embodiment.

FIG. 13 is a block diagram of Conventional Example 3.

FIG. 14 is a block diagram of an average value interpolation processing circuit.

FIG. 15 is a block diagram of Example 7.

FIG. 16 is a block diagram of Conventional Example 4.

FIG. 17 is an operation explanatory diagram of Conventional Example 4.

[Explanation of symbols]

 9 2-port output field memory 10 Write control circuit 14 First read control circuit 16 Second read control circuit 22 Switch circuit 24 Blanking signal generation circuit

Claims (5)

[Claims] 1. An image enlarging processing device for enlarging an image using an image memory, the image memory being capable of asynchronously outputting data stored from two output ports,
The writing control means for controlling writing of the input video signal to the image memory and the first output port of the image memory read data at a phase delayed by about 1/2 field from the writing phase of the input video signal. From the first output control means for controlling the input video signal and the second output port of the image memory.
Second read control means for controlling to read the enlarged image data at a phase delayed by 1/2 field, and outputs by switching the data of the first output port and the data of the second output port. Switching means for
The data of the first output port is output during the blanking period of the video signal of the first output port, and the data of the second output port is output during the periods other than the blanking period. An image enlargement processing apparatus comprising: a switching control unit that switches the switching unit. 2. An image enlarging processing device for enlarging an image using an image memory, the image memory storing an input video signal, and a writing control means for controlling writing of the input video signal to the image memory. Read control means for reading the expanded image data from the image memory at a phase delayed by about 1/2 field from the write phase of the input video signal, and about 1/2 field from the input video signal. A signal generating means for generating a decoding synchronization signal and a blanking signal delayed by a delay, a switching means for switching and outputting the output data of the image memory and the output signal of the signal generating means, and a blanking period by the blanking signal. Outputs the output data of the image memory except during the blanking period so as to output the output signal of the signal generating means. An image enlargement processing device, comprising: a switching control unit for switching the switching unit. 3. An image enlarging processing device for writing an interlace type video signal, which constitutes one screen with two fields, to an image memory, and enlarging an image using the image memory, and storing the image in the image memory. A read control unit is provided for shifting the read timing of the image data being read by shifting the odd field and the even field by the number of lines corresponding to the magnification of the image enlargement. Image enlargement processing device. 4. An image enlarging processing device for enlarging an image by using an image memory, wherein a difference in signal level between adjacent pixels in the vertical direction and / or the horizontal direction of the enlarged video signal is An image enlargement processing apparatus comprising an interpolating means for performing an average value interpolation when it is smaller than a predetermined threshold value and performing a previous value interpolation when it is larger. 5. An image enlarging processing device for enlarging an image using an image memory, comprising: a first processing system for performing processing when the enlarging magnification is less than a predetermined value n; a second processing system for processing when n or more,
The first processing system is a processing system that compresses video signal data to 1 / n, stores it in the image memory, enlarges and reads it from the image memory according to an enlargement ratio, expands it, and outputs it. The second processing system is a processing system that stores video signal data in the image memory without compression processing, enlarges the image signal data according to an enlargement ratio, and outputs the enlarged image data. Image enlargement processing device.