JPH10336518A - Image magnification processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image magnification processing unit, by which deterioration in the image quality attended with magnification processing of an image is made less. SOLUTION: In the case that a magnification of an input signal is smaller than a prescribed multiple of (n), a compression circuit 218 compresses the signal to be a multiple of 1/n and stores the compressed signal to a memory 8. When the magnification of the input signal is more than the multiple (n), since the magnified video signal is not more than 1/n of the entire input video signal, since the positions of the signals desired to be magnified are known, only the video signals are controlled to be stored in the memory 8, then the video signals can be stored sufficient in the memory 8 without compression. As stated above, when the magnification is small, since the information amount of the original signals in high, even when the signals are compressed to be 1/n by the compression circuit 218, the deterioration in the image quality by the compression tends not to be remarkable. On the other hand, when the magnification is more than the multiple (n), not all the input video signals are compressed but only the signals desired to be magnified are written in the memory, then the deterioration, in the image quality of the video image due to compression when the magnification is high, is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an apparatus for performing image enlargement processing used in a VTR integrated camera, a video effector, and the like.

[0002]

2. Description of the Related Art In recent years, video effectors capable of adding special effects such as zoom, strobe, and mosaic to video signals using digital signal processing technology have been commercialized at low prices. Since these products are commercially available at low prices, digital signal processing circuits are often equipped with field memories so that various special effects using the field memories can be achieved.

(Conventional Example 1) A circuit of Conventional Example 1 for performing a special effect of image enlargement (also referred to as electronic zoom) will be described. In FIG. 6, a synchronization separation circuit 4 separates a horizontal synchronization signal and a vertical synchronization signal from an input video signal, and a clock generation circuit 6 generates a system clock based on the separated synchronization signal. The write control circuit 10 generates a write address signal for writing an input video signal to the field memory 8 (hereinafter also referred to as a memory) based on the system clock and the system clock, and outputs the write address signal to the memory 8.

The input video signal is converted into a digital signal by the A / D converter 2 and then written into the memory 8 in accordance with the write address signal. Thus, the video signal for one field is stored in the memory 8.

The video signal stored in the memory 8 is read out according to a read address signal of a read control circuit 12 which is set according to the magnification of the image, and is interpolated by an interpolation processing circuit 20. The part equivalent to the synchronization signal of the video signal that has been processed
The D / A converter 26 is switched by a synchronization signal of the input video signal.
To convert to analog signal and output.

Next, read control when the center of the screen is doubled will be described. As shown in FIG. 7A, in order to enlarge the screen twice, the reading is started from point A in the figure, the data in the memory 8 is read twice, and the half horizontal video signal section is read. Then, the same data is read again in the next horizontal scanning video signal section.
By this operation, the image based on the signal in the half horizontal video signal section of the original video signal is enlarged twice in the horizontal direction and twice in the vertical direction. By repeating such control, the center of the screen can be doubled. However, since the synchronizing signal is lost in this state, the portion corresponding to the synchronizing signal of the enlarged video signal is replaced with the synchronizing signal portion of the input video signal and then output.

(Conventional Example 2) A circuit of Conventional Example 2 will be described with reference to FIG. The synchronization separation circuit 4 separates the horizontal synchronization signal and the vertical synchronization signal from the input video signal, and the clock generation circuit 6 generates a system clock based on the separated synchronization signal. The write control circuit 10 generates a write address signal for writing an input video signal to the field memory 8 and outputs the write address signal to the memory 8. The input video signal is converted into a digital signal in the A / D converter 2 and then written into the memory 8 according to the write address signal.
Thus, the video signal for one field is stored in the memory 8.

The video signal stored in the memory 8 is read out according to a read address signal of a read control circuit 12 which is set according to the magnification of the image, and is interpolated by an interpolation processing circuit 20. A portion corresponding to the synchronizing signal of the enlarged video signal is replaced with a synchronizing signal of the input video signal, and is converted to an analog signal by the D / A converter 26 and output.

Next, a description will be given of readout control when the center of the screen is enlarged twice by image enlargement processing.
As shown in FIG. 11B, when the image data is enlarged by a factor of two, the same video data, for example, a, is read from the memory 8 twice a and a, and a half horizontal video signal section is read.
The same data is read again in the next horizontal scanning video signal section. By this operation, the image of the half horizontal video signal section of the original video signal is doubled in the horizontal direction and doubled in the vertical direction.
That is, it is doubled. By repeating such control, the center of the screen can be doubled.

When the image is enlarged four times, the same data is read from the memory 8 four times at a time, as shown in FIG. The same data is read from the signal section to the three horizontal scanning video signal sections. By this operation, the image in the 水平 horizontal video signal section of the original video signal is enlarged four times in the horizontal direction and four times in the vertical direction. By repeating such control, the center of the screen can be enlarged four times.

(Conventional Example 3) Next, a circuit of Conventional Example 3 for performing image enlargement processing will be described. In FIG. 13, a synchronization separation circuit 4 separates a horizontal synchronization signal and a vertical synchronization signal from an input video signal, and a clock generation circuit 6 generates a system clock based on the separated synchronization signal. The write control circuit 10 generates a write address signal for writing an input video signal to the field memory 8 from the system clock and the system clock, and outputs the write address signal to the memory 8.

The input video signal is converted into a digital signal by the A / D converter 2 and then written into the memory 8 in accordance with the write address signal. Thus, the video signal for one field is stored in the memory 8.

The video signal stored in the memory 8 is read out according to the read address signal of the read control circuit 12 set by the magnification of the image, and is interpolated by the interpolation processing circuit 20. The part corresponding to the synchronizing signal of the enlarged video signal is replaced with the synchronizing signal of the input video signal, and is converted to an analog signal by the D / A converter 26 and output.

Next, read control when the center of the screen is enlarged twice by image enlargement processing will be described.
In order to enlarge the screen twice, the data in the memory 8 is read twice from the read point, and once the 1/2 horizontal video signal section is read, the same data is read again in the next horizontal scanning video signal section. . By this operation,
This means that the signal in the half horizontal video signal section of the original video signal has been enlarged twice in the horizontal direction and twice in the vertical direction. By repeating such control, the center of the screen can be doubled. However, if the enlargement magnification is increased as it is, a large block is formed by the pixels of the same data, and a mosaic image is formed. In particular, the pixel interval in the vertical direction is wider than in the horizontal direction, and image quality is noticeably degraded. Therefore, as shown in FIG. 14, a smooth image is obtained by performing an average value interpolation process for obtaining an average value with the pixel of the previous line.

(Conventional Example 4) In a consumer device, since a large-capacity memory is expensive, when an input video signal is digitized and stored in the memory, the data is compressed to reduce the information amount of the signal. From the memory, read from the memory, expand the data, and restore the original signal to save the memory. A circuit of a fourth conventional example that performs image enlargement processing while performing such signal processing will be described.

In FIG. 16, a synchronization separation circuit 4 separates a horizontal synchronization signal and a vertical synchronization signal from an input video signal, and a clock generation circuit 6 generates a system clock based on the separated synchronization signal. From the synchronization signal and the system clock, the write control circuit 10 generates a write address signal for writing an input video signal to the field memory 8 and outputs the write address signal to the memory 8. The input video signal is converted into a digital signal in the A / D converter 2 and is compressed to 1 / n in the compression circuit 218.
The data is written to the memory 8 according to the write address signal. Thus, the video signal for one field is stored in the memory 8.

The video signal stored in the memory 8 is read out according to a read address signal of the read control circuit 12 set by the magnification of the image, and is read out by the expansion circuit 22.
After the image signal is expanded by n times at 0, interpolation processing is performed by an interpolation processing circuit 21, and a switch circuit 22 replaces a portion corresponding to a synchronization signal of a video signal subjected to image enlargement processing with a synchronization signal of an input video signal. The signal is converted into an analog signal by the converter 26 and output.

[0018]

However, Conventional Examples 1 to 4 have the following problems.

(Regarding Conventional Example 1) In the image enlarging process using the circuit configuration of Conventional Example 1, as shown in FIG. 7C, when there is a moving image, an image having a time difference of one field on the screen is displayed. The problem is that the boundaries appear as horizontal lines.

This problem occurs because the write address signal overtakes the read address signal halfway. That is, as shown in FIG. 7B, the write address signal moves from B to B 'while the read address signal moves from A to A', so that the write address overtakes the read address in the middle of the screen. . Until the write address overtakes the read address, the video signal one field before is output. However, if the write address overtakes the read address, the video signal immediately after writing is output, and the write address overtakes the read address. Video signal read at the moment
Move around the field.

(Regarding Conventional Example 2) In the image enlarging process using the circuit configuration of Conventional Example 2, as shown in FIGS. 11B and 11C, when the magnification of enlargement is increased, the same data is used. Since the block of pixels becomes large, the image becomes mosaic, and the difference between the luminance signal of the odd (Odd) field image and the luminance signal of the even (Even) field image becomes large, which causes flicker at 30 Hz and flickers. There is a problem that an image is very difficult to see.

(Regarding Conventional Example 3) In Conventional Example 3, there is a problem that the steep change of the signal becomes gentle by performing the average value interpolation processing, and the edge of the image appears blurred.

(Regarding Conventional Example 4) In the circuit configuration of Conventional Example 4, since the compression processing and the decompression processing are performed, the image quality deteriorates to a certain extent. When a part of the image is enlarged, the image quality of the enlarged image is greatly degraded as the magnification is increased.

For example, a high resolution television, VTR or V
A sampling frequency of 14.3 MHz is often used when digitizing an input video signal in order to maintain image quality due to an increase in resolution of a TR integrated camera. With it 1
The information amount of the video signal in the field has greatly increased, and a large number of memories are required. Therefore, in order to save memory capacity, studies have been made to reduce the memory by compressing the input video signal in half, and as a compression method, a method of reducing the information of the input video signal to half by halving the sampling frequency. Also, the information of the signal is calculated using DPCM (prediction coding), which is the correlation between adjacent pixels of the input video signal.
Various methods, such as a method of compressing to / 2, have been proposed. However, a signal restored after compression of a signal is always a signal degraded compared to the original signal, although it depends on the compression method. When the sampling frequency is reduced to 解像度, the resolution is reduced to １ ／, and in the case of DPCM, a phenomenon called edge business appears. When such a deteriorated image is enlarged, there is a problem that the image quality is further deteriorated as the enlargement magnification is increased (see FIG. 17).

The present invention has been made under such circumstances, and it is an object of the present invention to provide an image enlargement processing apparatus in which the image quality is hardly deteriorated due to the image enlargement processing.

[0026]

In order to achieve the above object, according to the present invention, an image enlargement processing device is provided by the following (1),
The configuration is as shown in (2).

(1) An image enlargement processing apparatus for performing image enlargement processing using an image memory, wherein an enlargement magnification is a predetermined value n
A first processing system that performs processing when the magnification ratio is less than and a second processing system that performs processing when the enlargement magnification is equal to or larger than the predetermined value n, wherein the first processing system converts video signal data into A processing system for compressing the image signal to 1 / n, storing the image data in the image memory, reading the image data from the image memory according to an enlargement magnification, expanding the image data, and outputting the image signal; Is stored in the image memory without compression processing, and is read out from the image memory in accordance with a magnification and output.

(2) An image enlargement processing apparatus for performing image enlargement processing using an image memory, wherein a difference in signal level between pixels adjacent to each other in a vertical direction and / or a horizontal direction of an enlarged image signal is determined. An image enlargement processing apparatus having an interpolation means for performing average value interpolation when the value is smaller than a predetermined threshold value and performing previous value interpolation when the value is larger than a predetermined threshold value.

[0029]

In the configuration (1), the compression and decompression processes are not performed when the magnification of the image is equal to or larger than the predetermined value n. In the configuration (2), the blur of the edge of the image is reduced.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to examples. Examples 1 to 3 correspond to Conventional Example 1.
Embodiment 4 corresponds to Conventional Example 2 and Embodiments 5 and 6
Corresponds to Conventional Example 3 and Embodiment 7 corresponds to Conventional Example 4, respectively.

[0031]

【Example】

(Embodiment 1) FIG. 1 is a block diagram of an "image enlargement processing apparatus" which is Embodiment 1. In the figure, reference numeral 2 denotes an A / D converter for converting an input video signal into a digital signal, reference numeral 4 denotes a synchronization separation circuit for separating a horizontal synchronization signal and a vertical synchronization signal from the input video signal, and reference numeral 6 denotes this separation. A clock generation circuit that generates a system clock based on the obtained synchronization signal. Reference numeral 9 denotes a memory (field memory) having two output ports for storing the input video digital signal described above, and 10 denotes a write for writing an input video signal to the memory 9 based on the synchronization signal and the system clock. A write control circuit 14 generates an address signal, and 14 converts the video signal stored in the memory 9 into 1 /
Reference numeral 16 denotes a first readout control circuit for reading out a video signal stored in the memory 9 at a phase delayed by 1 / 2V (at a later stage) and at a set magnification. And a second read control circuit for reading out
Is an interpolation processing circuit for interpolating the video signal of the enlarged image read by the second read control circuit 16. 22
Reference numeral 24 denotes a switch circuit for replacing a portion corresponding to the synchronization signal of the video signal of the interpolated enlarged image with the synchronization signal of the input video signal, and 24 controls the switch circuit 22 by controlling the synchronization signal and the system clock. A blanking signal generation circuit for generating a blanking signal is further provided. Reference numeral 26 denotes a D / A converter for converting the output video signal of the switch circuit 22 into an analog signal.

Next, the operation will be described.

Since the write operation is the same as that described in the conventional example 1, the read operation will be described.
In the first read control circuit 14, as shown in FIG.
From the output port 40, a first read address signal is generated so as to read data stored in the memory 9 with a phase delayed by 1/2 V + α from the synchronization signal of the input video signal. Here, V is a time for scanning one field, and is about 63.5 μsec in the case of an NTSC signal. Α is an arbitrary time convenient for the circuit configuration.

In the second read control circuit 16,
As shown in FIG. 2 (c), like the first read address signal, the phase is delayed by 1/2 V + α from the synchronization signal of the input video signal, and the second is set by the magnification of the image. Generate a read address signal. This second
The control of the read address signal is the same as that described in the first conventional example when the center of the screen is enlarged twice. The second read address signal causes the memory 9
The video signal of the enlarged image read out from the second output port 42 is mosaic-like and unsightly as it is, and is interpolated by the interpolation processing circuit 20 so as to be smooth. The video signal read from the first output port 40 of the memory 9 by the first read address signal is also input to the switch circuit 22, and the blanking signal 50 generated by the blanking generation circuit 24 generates 22 is switched, and the portion corresponding to the synchronization signal in the video signal of the enlarged image subjected to the interpolation processing is replaced with the synchronization signal of the input video signal. Then, the video signal of the enlarged image to which the synchronization signal is added is converted to an analog video signal by the D / A converter 26, and then output to the outside.

By controlling in this manner, the write address signal does not overtake the read address signal in the middle of the screen, and the image is not lost.

As described above, according to this embodiment,
A 2-port output field memory is used, and the read address signal is reduced from the write address signal to about 1/2.
By delaying the V time, even if the central portion of the screen is enlarged from 1 × to 2 × or 4 × by the image enlargement processing,
Since the write address signal does not overtake the read address signal in the middle of the screen, it is possible to prevent the occurrence of development that looks like a horizontal line because the image before and after one field is mixed in the screen.

(Embodiment 2) FIG. 3 shows the configuration of Embodiment 2. In FIG. 3, A / D converter 2, sync separation circuit 4,
The operations of the clock generation circuit 6, the write control circuit 10, and the first read control circuit 14 are the same as the operations in the first embodiment. Therefore, the first read address signal causes the first output port 40 of the field memory 9 having the two-port output to output 1/1/1 of the sync signal of the input video signal.
The data stored in the memory 9 is read out at a phase delayed by 2 · V + α. The second synchronization separation circuit 5 separates a horizontal synchronization signal and a vertical synchronization signal from data read from the first output port 40 of the field memory 9, and the second read control circuit 17 generates a clock signal. A second read address signal is generated from the system clock generated by the circuit 6 and the horizontal synchronizing signal and the vertical synchronizing signal separated by the second synchronizing separation circuit 5, and the memory 9
Output to The control of the second read address signal is the same as that described in the first embodiment. Further, a blanking signal is generated in a blanking signal generation circuit 24 from the system clock generated by the clock generation circuit 6 and the horizontal synchronization signal and the vertical synchronization signal separated by the second synchronization separation circuit 5. 22. Even with such a configuration, the same effect as in the first embodiment can be obtained.

(Embodiment 3) FIG. 4 shows the configuration of this embodiment. In the figure, reference numeral 2 denotes an A / D converter for converting an input video signal into a digital signal, reference numeral 4 denotes a synchronization separation circuit for separating a horizontal synchronization signal and a vertical synchronization signal from the input video signal, and reference numeral 6 denotes a separated signal. A clock generation circuit that generates a system clock based on a synchronization signal, 8 is a field memory that stores the input video digital signal described above, and 10 is based on the synchronization signal and the system clock.
A write control circuit 13 generates a write address signal for writing an input video signal to the memory 8, and 13 converts the video signal stored in the memory 8 to about 1 /
This is a control circuit that reads out an image with a phase delayed by 2 · V and at a set magnification. Reference numeral 56 denotes a signal generator for generating a composite synchronizing signal and a blanking signal having a phase delayed by about 1/2 V from the synchronizing signal of the input video signal.
Reference numeral 0 denotes an interpolation processing circuit for interpolating the video signal of the enlarged image read by the read control circuit 13.
Reference numeral 2 denotes a switch circuit for replacing a portion corresponding to the synchronization signal of the video signal of the enlarged image subjected to the interpolation processing with a composite synchronization signal output from the signal generator 56. Reference numeral 26 denotes an output of the switch circuit 22 for image enlargement. This is a D / A converter that converts the processed video signal into an analog signal.

Next, the operation will be described.

Since the write operation is the same as that described in the conventional example 1, the read operation will be described.
In the read control circuit 13, as shown in FIG. 5D, the data stored in the memory 8 has a phase delayed by 1 / 2.times.V + .alpha. A read address signal is generated so as to read in an enlarged manner. The control of the read address signal is the same as that described in the first conventional example when the center of the screen is enlarged twice. The video signal of the enlarged image read from the memory 8 by the read address signal is mosaic and unsightly as it is.
At 0, the signal is interpolated so as to be smooth and then output to the switch circuit 22. In the switch circuit 22, the blanking signal generated by the signal generator 56 converts a portion corresponding to the synchronization signal of the video signal of the enlarged image subjected to the interpolation processing into a composite synchronization signal generated by the signal generator 56. Replace. Then, the video signal of the enlarged image to which the synchronization signal is added is converted to an analog video signal by the D / A converter 26 and then output to the outside.

By performing such control, the write address signal does not overtake the read address signal in the middle of the screen, and the same effect as in the first embodiment can be obtained.

(Embodiment 4) FIG. 8 shows the configuration of Embodiment 4. 8, reference numeral 2 denotes an A / D converter for converting an input video signal into a digital signal, reference numeral 4 denotes a synchronization separation circuit for separating a horizontal synchronization signal and a vertical synchronization signal from the input video signal, and reference numeral 6 denotes a synchronization separation circuit. This is a clock generation circuit that generates a system clock based on the separated synchronization signal. Reference numeral 8 denotes a memory for storing the input video digital signal. Reference numeral 10 denotes a memory based on the synchronization signal and the system clock.
A write control circuit that generates a write address signal for writing an input video signal to the memory 8, and a read control circuit 32 that reads a video signal stored in the memory 8. Reference numeral 20 denotes an interpolation processing circuit that interpolates the video signal of the enlarged image read by the read control circuit 32. Reference numeral 22 denotes a portion corresponding to the synchronization signal of the video signal of the enlarged image subjected to the interpolation processing. 24 is a switch circuit which is replaced by a signal.
2 is a blanking signal generating circuit for generating a blanking signal from the synchronizing signal and the system clock in order to control the switching of the switch 2;
A converter.

Next, the operation will be described.

Since the writing operation is the same as that described in the conventional example 2, the reading operation will be described in the case where the image is enlarged four times. The image based on the video signal in the 61st horizontal scanning period from the nth line to the (n + 60) th line of the input video signal is enlarged four times in the vertical direction of the screen, and is enlarged from the 18th line to the 260th line. At this time, in the case of an odd field, as shown in FIG. 9B, the data of the n-th line stored in the memory 8 is read four times during the four horizontal scanning periods from the eighteenth line to the twenty-first line. Then, the read address control of reading the data of the (n + 1) th line four times during the four horizontal scanning periods from the 22nd line to the 25th line is repeated. Next, in the case of an even field, the data of the n-th line stored in the memory 8 is transferred from the (18 + k) -th line to the (21+
k) Four times during the four horizontal scanning periods of the line, and then the data of the (n + 1) th line is read four times during the four horizontal scanning periods of the (22 + k) th line to the (25 + k) th line. The read address control is performed with a shift of k lines from the read timing at the time of an odd field. When the magnification of the image is four times, the value of k is appropriately 2 as shown in the figure. If the value of k is increased as the magnification of the image is increased, the image becomes easy to see.

As described above, according to the present embodiment,
By shifting the timing for reading the signal stored in the memory means by k lines between reading the odd field and reading the even field in accordance with the magnification of the image, as shown in FIG. The area where the luminance signal of the odd field and the luminance signal of the even field in the video signal are shifted becomes small, and the flicker of 30 Hz becomes less noticeable.

(Embodiment 5) FIG. 12 is a block diagram of an interpolation circuit in this embodiment. The configuration other than the interpolation circuit is the same as that of FIG. The signal read from the memory 8 according to the magnification of the image enlargement is input to the interpolation circuit shown in FIG. 12 and is delayed by the one-line delay circuit 122.
24 and to a subtractor 126. The adder 124 adds the output signal of the one-line delay circuit 122 and the signal read from the memory 8 and outputs the result to the adder 128. The divider 128 calculates the input signal by １ ／ and outputs it to the switch circuit 130. On the other hand, the subtractor 126 obtains the difference between the output signal of the one-line delay circuit 122 and the signal read from the memory 8 and outputs the absolute value to the discrimination circuit 132. In the determination circuit 132, the level of the input signal and
The threshold value is compared with a preset threshold value, and the result is output to switch circuit 130. That is, the determination circuit 13
2 outputs the output signal of the divider 128 when the level difference between the input video signal and the video signal delayed by one line is smaller than the set threshold value, and outputs the signal read from the memory 8 when the level difference is larger. Is controlled as it is so as to output as it is.

By controlling in this way, the level of the signal of the pixel on the current line is compared with the level of the signal of the pixel one line before, and when the level difference is larger than the set threshold value, that is, when the edge is an image, the average value interpolation is performed. Then, pre-value interpolation (also referred to as pre-hold interpolation) is performed to prevent the edge of the image from being blurred, and average value interpolation is performed at an area other than the edge to prevent the image from looking like a mosaic.

(Embodiment 6) Embodiment 5 relates to interpolation processing in the vertical direction of the screen, but the same method can be applied to interpolation processing in the horizontal direction of the screen. That is, FIG.
, The delay circuit 122 may be delayed by one pixel. If the interpolation circuit of the fifth embodiment and the interpolation circuit of this embodiment are connected in series, the same effect can be obtained in both the vertical and horizontal directions of the screen.

(Embodiment 7) FIG. 15 shows the configuration of Embodiment 7. In the figure, reference numeral 2 denotes an A / D converter for converting an input video signal into a digital signal, reference numeral 4 denotes a synchronization separation circuit for separating a horizontal synchronization signal and a vertical synchronization signal from the input video signal, and reference numeral 6 denotes a separation circuit. And a clock generation circuit that generates a system clock based on the synchronization signal. Reference numeral 218 denotes a compression circuit for compressing the digitized input video signal to 1 / n. Reference numeral 232 denotes a pre-low-pass filter for removing aliasing noise generated when the magnification is increased. A first switch circuit 228 switches between the signal compressed by the compression circuit 218 and the output of the low-pass filter 232 in accordance with a switching signal controlled by a magnification. Reference numeral 8 denotes a memory for storing the input video digital signal switched by the switch circuit 228, and reference numeral 10 denotes a write for generating a write address signal for writing an input video signal to the memory 8 based on the synchronization signal and the system clock. A control circuit 12 is a read control circuit for reading out the video signal stored in the memory 8 by enlarging it to a set magnification. Reference numeral 220 denotes a decompression circuit that decompresses the input signal compressed to 1 / n by n times and restores the original signal, and 230 denotes a video signal decompressed by the decompression circuit 220 and the memory 8.
And a second switch circuit that switches a signal output from the switch according to a switching signal controlled by a magnification. Reference numeral 21 denotes an interpolation processing circuit that interpolates a video signal of an enlarged image output from the second switch circuit 230. Reference numeral 22 denotes a synchronization signal equivalent portion in the video signal of the interpolation-processed enlarged image. 3 is a third switch circuit which is replaced by the synchronization signal of FIG. 24 is a blanking signal generation circuit for generating a blanking signal from the synchronization signal and the system clock to control the third switch circuit 22;
4 is a D / A converter for converting the output video signal into an analog signal.

Next, the operation will be described.

When the magnification of the input signal is smaller than the predetermined n times, the compression circuit 2
At 18, the data is compressed to 1 / n and stored in the memory 8. 1 /
By compressing to n, the capacity of the memory 8 can be reduced to 1 / n. Next, when the magnification of the input signal becomes n times or more, the enlarged video signal is only 1 / n or less of the whole input video signal. Therefore, if the position of the signal to be enlarged is known in advance, only that video signal is used. Is stored in the memory 8 so that the input video signal can be sufficiently stored in the memory 8 without compression.

As described above, in this embodiment, when the magnification for enlarging the image of the input video signal is from 1 to a predetermined n times (√n times in the horizontal direction and √n times in the vertical direction), The input video signal is compressed to 1 / n by a compression circuit and stored in the memory to reduce the memory capacity. As described above, when the magnification is small, even if the data is compressed to 1 / n by the compression circuit, the information amount of the original signal is large, so that the image quality deterioration due to the compression is not conspicuous. On the other hand, if the magnification is n times or more, the required signal in the original input video signal becomes 1 / n or less of the entire input video signal, and therefore, it is desired to expand the input video signal without compressing the input video signal. By controlling only the partial signal to be written to the memory, the required signal can be stored without changing the memory capacity, and the image quality of the video is prevented from deteriorating due to compression when the magnification is large. Can be.

In this way, by reducing the capacity of the memory, it is possible to minimize the deterioration of the image quality while reducing the cost.

[0054]

As described above, according to the present invention,
It is possible to provide an image enlargement processing device in which the image quality is less deteriorated due to the image enlargement processing.

More specifically, according to the first aspect of the present invention,
According to the second aspect of the present invention, it is possible to save the memory capacity and to minimize the deterioration of the image quality. You can prevent it from being seen.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment;

FIG. 2 is a timing chart of each signal in the first embodiment.

FIG. 3 is a block diagram of a second embodiment;

FIG. 4 is a block diagram of a third embodiment;

FIG. 5 is a timing chart of each signal according to the third embodiment.

FIG. 6 is a block diagram of Conventional Example 1.

FIG. 7 is an explanatory diagram of the operation of Conventional Example 1.

FIG. 8 is a block diagram of a fourth embodiment.

FIG. 9 is an explanatory diagram of the operation of the fourth embodiment.

FIG. 10 is a block diagram of a second conventional example.

FIG. 11 is an explanatory diagram of the operation of Conventional Example 2.

FIG. 12 is a block diagram of an interpolation circuit according to a fifth embodiment.

FIG. 13 is a block diagram of a third conventional example.

FIG. 14 is a block diagram of an average value interpolation processing circuit;

FIG. 15 is a block diagram of a seventh embodiment.

FIG. 16 is a block diagram of Conventional Example 4.

FIG. 17 is a diagram illustrating the operation of Conventional Example 4.

[Explanation of symbols]

 9 Field memory with 2-port output 10 Write control circuit 14 First read control circuit 16 Second read control circuit 22 Switch circuit 24 Blanking signal generation circuit

Claims (2)

[Claims] An image enlargement processing apparatus for performing an image enlargement process using an image memory, comprising: a first processing system for performing processing when an enlargement magnification is less than a predetermined value n; and a second processing system that performs processing when n or more,
The first processing system is a processing system for compressing video signal data to 1 / n, storing the video signal data in the image memory, expanding the image signal data from the image memory in accordance with an enlargement magnification, expanding the image signal, and outputting the image data. The second processing system is a processing system that stores video signal data in the image memory without performing compression processing, and reads out and outputs the image signal data from the image memory according to a magnification. Image enlargement processing device. 2. An image enlargement processing apparatus for performing image enlargement processing using an image memory, wherein a difference in signal level between pixels adjacent in a vertical direction and / or a horizontal direction of an enlarged video signal is represented by: An image enlargement processing device comprising an interpolation means for performing average value interpolation when the value is smaller than a predetermined threshold value and performing previous value interpolation when the value is larger than a predetermined threshold value.