JP3529590B2 - Imaging system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image system having a function of obtaining a high quality image by performing a calculation process on a video signal in an image pickup device such as a video camera to generate a plurality of image signals. In this specification, the image pickup system is a broad concept including not only a so-called system but also an image pickup apparatus.

[0002]

2. Description of the Related Art A still image creating function in an image pickup apparatus such as a conventional video camera as an image pickup system will be described. FIG. 32 is a block diagram of an image pickup apparatus such as a video camera including a conventional still image generating function circuit. Figure 3
In FIG. 2, 1201 is an image pickup device having a photoelectric conversion function, 1202 is an image pickup device drive circuit for the image pickup device 1201, 1203 is an analog signal processing circuit for performing processing such as sampling and amplification on an output signal of the image pickup device 1201, 1
Reference numeral 204 denotes an analog-digital conversion circuit (hereinafter referred to as A / D conversion circuit) for the output signal of the analog signal processing circuit 1203, 1205 a field memory for recording / reproducing the A / D converted digital signal, and 1206 a field memory 1205. A memory control circuit for controlling 1207, a digital signal processing circuit for generating a luminance signal, a color signal, a color difference signal or the like from an output signal of the field memory 1205 or RGB signal processing, 1208 for an NTSC signal or the like from an output signal of the digital signal processing circuit 1207 1209 is a system control circuit for comprehensively controlling the memory control circuit 1206 and the digital signal processing circuit 1207.

The operation of an image pickup apparatus such as a video camera including the conventional still image forming function circuit configured as described above will be described below.

An analog output signal from the image pickup device 1201 becomes a digital signal through an analog signal processing circuit 1203 and an A / D conversion circuit 1204. This digital signal is stored in the field memory 1205 controlled by the memory control circuit 1206, and is read out after one field period and is read by the digital signal processing circuit 1207.
In, the luminance signal and the color signal are processed.

At this time, when the system control circuit 1209 gives an instruction to create a still image, the memory control circuit 1206
The storage of the new signal in the field memory 1205 is stopped, and the reading of the stored signal is continued. Then, the digital signal processing circuit 1207 performs interlace control on the output signal of one field of the field memory 1205, and outputs a still image suitable for the television signal.

As described above, in the still image creating function in the conventional image pickup apparatus such as a video camera, the field memory 1 is used.
A still image is created by reading the video signal of one field stored in 205.

Further, as a conventional image pickup device using a pseudo frame signal, there is "an image pickup device with a frame still image creating function" described in Japanese Patent Laid-Open No. 6-233316. The image pickup apparatus with the frame still image creating function will be described below.

FIG. 33 is a block diagram of an image pickup apparatus using a pseudo frame signal. In FIG. 33,
Reference numeral 1301 denotes an image pickup element portion having a photoelectric conversion function, 1302
Is an image sensor drive circuit for the image sensor unit 1301, 13
Reference numeral 03 is a drive control circuit for controlling the image sensor drive circuit 1302, 1304 is an analog signal processing circuit for performing processing such as sampling and amplification on the output signal of the image sensor unit 1301, 1
Reference numeral 305 denotes an analog-digital conversion circuit (hereinafter referred to as A / D conversion circuit) for the output signal of the analog signal processing circuit 1304, 1306 denotes a luminance signal, a color signal, a color difference signal or the like from the A / D converted digital signal, or RGB.
A digital signal processing circuit for performing signal processing, 1307 is a field memory circuit for storing the output signal of the digital signal processing circuit 1306, 1308 is a field memory control circuit for controlling the field memory circuit 1307, 130
Reference numeral 9 denotes a system control circuit that comprehensively controls the drive control circuit 1303 and the field memory control circuit 1308, and 131.
0 indicates N from the output signal of the digital signal processing circuit 1306.
An encoder circuit for obtaining a television signal such as a TSC signal, 1311 is an encoder circuit for obtaining a television signal such as an NTSC signal from the output signal of the field memory circuit 1307.

In the image pickup apparatus having the frame still image creating function configured as described above, the image pickup element section 1301
The plurality of R, G, and B output signals output from the digital signal are subjected to analog signal processing and A / D conversion processing to become digital signals. This digital signal is processed by the digital signal processing circuit 13
In 06, the luminance signal (Y1, Y2) and the color signal (C
1, C2) processed and input to the field memory circuit 1307. The signal input to the field memory circuit 1307 is output as a frame image by the field memory control circuit 1308.

The operations of the image pickup device section 1301 and the digital signal processing circuit 1306 in FIG. 33 will be briefly described. In the image pickup device unit 1301, when the image pickup device unit has a 3CCD structure as shown in FIG. 34, an image pickup device unit without a normal vertical pixel shift unit has G.
While the output signals of the R-B-CCD are spatially in the same phase with respect to the vertical direction, the output signal of the G-CCD as shown in FIG. 34 (b) in the image pickup device section having the vertical pixel shift section. On the other hand, the output signal of the RB CCD is spatially 1/2
It is output with the phase shifted by the line. As a result, in the case of no vertical pixel shift (a), the luminance signal (Y) and the color signal (C) are created at the same phase position as the output signal of the G, R, B-CCD, whereas the vertical pixel is not. In the case of the shift (b), the digital signal processing circuit 1306 has the same phase position as the output signal of the G-CCD and R · B−C.
A total of two systems of luminance signal (Y) and color signal (C) are created at the same phase position as the output signal of the CD.

After this, the digital signal processing circuit 1306
The output signal of is stored in the field memory circuit 1307 as an image at an arbitrary moment under the control of the field memory control circuit 1308, and the first field signal composed of the Y1 and C1 signals and the first field signal composed of the Y2 and C2 signals. The luminance signal Y3 and the color difference signal C3 are output in time series as a two-field signal, and further, the Y3 signal and the C3 signal are converted into a television signal (TV2) by the encoder circuit 1311 and output as a still image.

As described above, in the conventional still image creating function in the image pickup apparatus using the pseudo frame signal, the vertical pixel shift processing and the digital signal processing circuit 1306 and the field memory for creating the Y1, Y2 signals and the C1, C2 signals are provided. By including the circuit 1307 and the field memory control circuit 1308, a luminance signal and a color difference signal which are in a positional relationship of a frame signal are created, two field signals which form a frame signal at the same time are obtained, and a still image is created. There is.

[0013]

In these various image pickup apparatuses, a photographed image is output to a monitor as a still image or is output using a printer, and a plurality of screens are displayed using a personal computer or the like. It is required to deal with obtaining high quality images. However, in a photographing device such as a video camera, the resolution in the horizontal and vertical directions is limited by the number of pixels of the image pickup element, the driving frequency thereof, and the output sampling frequency rate, so that a high-resolution image cannot be obtained.

The present invention is to solve the above-mentioned problems, and it is possible to create a high resolution image even under the limitation of the resolution in the horizontal and vertical directions depending on the number of pixels of the image pickup device and its driving frequency and the output sampling frequency rate. An object is to provide an imaging system such as an imaging device.

[0015]

SUMMARY OF THE INVENTION According to the present invention, at least one of a horizontal direction and a vertical direction obtains a video signal at the same time having a higher density than the output sampling frequency rate, and further, the high density video signal is different. After dividing the image into multiple images, each divided image is output at the output sampling frequency rate, which makes it possible to obtain multiple images for high-quality image composition at the output sampling frequency rate. This solves the above-mentioned problems.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION The invention according to claim 1 of the present invention comprises means for obtaining a video signal having a density higher than the output sampling frequency rate in at least one of the horizontal direction and the vertical direction, and this high density video signal. It is provided with a dividing means for dividing the video signal into a plurality of different images and an image output means for outputting each of the divided images at an output sampling frequency rate. Has the effect of creating a plurality of images.

[0017]

[0018]

The invention described in claim 1 is a means for obtaining three different color signals C1, C2 and C3, and the color signal C1.
A horizontal phase shifter for shifting the horizontal phase of the color signals C2 and C3 by a constant pitch hp; and a color signal C horizontally phase-shifted with the color signal C1.
2, C3 in the horizontal direction, the color signals C1, C2
A horizontal pixel shift processing circuit that obtains a signal having a double density of C3, and 2: for the output signal of the horizontal pixel shift processing circuit :
Clock conversion processing circuit for performing clock conversion with a ratio of 1
And the horizontal direction from the clock conversion processing circuit.
Clock conversion to obtain two images for each pixel of a double-density signal
It is equipped with a control circuit, and the image is double-density in the horizontal direction.
Output from signal 2 screens with different sampling frequency rates
It has the function of creating an image .

According to a second aspect of the invention, means for obtaining three different color signals C1, C2 and C3, and the color signal C1.
A horizontal phase shifter for shifting the horizontal phase of the color signals C2 and C3 by a constant pitch hp; and a vertical phase shift of the color signal C2 for the color signal C1 in the vertical direction by a constant pitch vp. A vertical phase shifter, and a frame processing circuit for obtaining a pseudo frame signal having a positional relationship of two field signals forming a frame signal from the color signal C1 and the color signals C2 and C3 phase-shifted in the horizontal and vertical directions, a horizontal pixel shifting processing circuit for obtaining a double density signal in the density of the color signals C1, C2, C3 in the horizontal direction from the pseudo frame signal, the horizontal field
Vertically and horizontally double-densed signals that have been subjected to stagger processing
Clock conversion with a 2: 1 ratio clock conversion
Conversion processing circuit and the clock conversion processing circuit from the horizontal
Image for each pixel of the double-density signal in the direction
Equipped with a conversion control circuit for vertical and water
Output from a double-density video signal in the horizontal direction Sampling frequency
It has the effect of creating four images with different rates .

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an image pickup apparatus having a plural image creating function and an image pickup system including the same in a basic embodiment of the present invention. As shown in FIG. 1, the image pickup apparatus with a function of creating a plurality of images has a high-density video signal creating means 201, an image dividing means 202, and an image outputting means 20.
3 is included.

In the image pickup apparatus with a plurality of image creating functions in the basic embodiment configured as described above,
The video signal created by the high-density video signal creating means 201 is divided by the image dividing means 202 and output by the image output means 203. At this time, when the video signal created by the high-density video signal creating means 201 has a higher density than the video signal of the output sampling frequency rate of the image output means 203, a plurality of videos are divided and output at the output sampling frequency rate. High-quality images can be created by combining the signals.

Next, FIG. 2 and FIG. 3 are block diagrams showing a basic configuration example of the image pickup apparatus with a plurality of image forming functions in the basic embodiment shown in FIG.

The image pickup apparatus with a function of creating a plurality of images shown in FIG. 2 is a high-density device composed of an image pickup element 210 (driving frequency fck_ccd) and an analog-digital converter (hereinafter A / D) 211 (sampling frequency fck_A / D). An image dividing means 202 including a video signal creating means 201, a clock converting circuit 212 (pre-conversion frequency fck_d1, post-conversion frequency fck_d2), and an image output means 203.
(Output sampling frequency fck_out).

In the image pickup apparatus having a plurality of image forming functions in the basic embodiment configured as described above,
The video signal of the sampling frequency rate fck_d1 created by the high density video signal creating means 201 is converted into a video signal of the low sampling frequency rate fck_d2 by the clock conversion circuit 212 which is the image dividing means 202,
The image is divided and output by the image output unit 203. A high quality image can be created by synthesizing a plurality of image signals that are time-divided and output at the output sampling frequency rate.

Next, the image pickup apparatus with a plural image forming function shown in FIG. 3 has an image pickup element 210 (driving frequency fck_ccd).
And an analog-digital converter (hereinafter A / D) 211 (sampling frequency fck_A / D) and a horizontal pixel shift processing circuit 213 (frequency fck_d3 before pixel shift processing).
High-density video signal creating means 201 composed of pixel-shifted frequency fck_d4), image dividing means 202 composed of clock conversion circuits (pre-conversion frequency fck_d5, post-conversion frequency fck_d6), and image output means 203.
(Output sampling frequency fck_out).

In the image pickup apparatus having a plurality of image forming functions in the basic embodiment configured as described above,
The video signal of the sampling frequency rate fck_d4 created by the high-density video signal creating means 201 is the image sensor 2
10 output signals (driving frequency fck_ccd) are converted into a high-density video signal having a double sampling frequency rate by horizontal pixel shift processing. This high-density video signal is converted into a low sampling frequency rate fck_d by the clock conversion circuit 212 which is the image dividing means 202.
6 video signals are converted and divided, and output by the image output means 203. A high quality image can be created by synthesizing a plurality of image signals that are time-divided and output at the output sampling frequency rate.

As described above, in the image pickup apparatus with the plural image forming function of the first basic configuration example shown in FIG. 2, the output signal of the image pickup element driven at a sampling frequency higher than the output sampling frequency rate is divided. To obtain multiple video signals at the output sampling frequency rate.

In the image pickup apparatus with a plurality of images forming function of the second basic configuration example shown in FIG. 3, the output signal of the image pickup element is subjected to the horizontal pixel shift processing to thereby obtain a sampling frequency higher than the output sampling frequency rate. Output signal is generated and divided to obtain a plurality of video signals at the output sampling frequency rate.

Then, a high quality image can be created by synthesizing these plural image signals.

A specific description will be given below of the image pickup apparatus with a plural image forming function in the basic embodiment shown in FIG. 1 to FIG.

(First Embodiment) FIG. 4 shows a first embodiment of the present invention.
3 is a block diagram of an image pickup apparatus with a multiple image generation function in the embodiment. As shown in the figure, the image pickup apparatus with a function of creating a plurality of images has an image pickup device unit 101 having a photoelectric conversion function, a horizontal pixel shift unit 102 as a horizontal phase shift unit provided in the image pickup device unit 101, and an image pickup device unit 10.
1, the image pickup element drive circuit 103, the drive control circuit 104 that controls the image pickup element drive circuit 103, and the image pickup element unit 10
1. An analog signal processing circuit 105 for performing processing such as sampling and amplification on the output signal of No. 1, an analog signal processing circuit 105
Analog-to-digital conversion circuit (hereinafter referred to as A / D conversion circuit) 106 for the output signal of the above, and a digital signal processing circuit for generating a luminance signal, a color signal, a color difference signal or the like from an A / D-converted digital signal, or for processing an RGB signal. (1) 1
07, horizontal pixel shift processing circuit 108 and clock conversion processing circuit provided in the digital signal processing circuit (1) 107
(1) 109, clock conversion processing circuit (1) clock conversion control circuit 110 for controlling 109, digital signal processing circuit
(1) Encoder (a) 111 and encoder (b) for obtaining a television signal such as an NTSC signal from the output signal of 107
112, drive control circuit 104, clock conversion control circuit 1
It is configured to include a system control circuit 113 that comprehensively controls the 10.

In this structure, the A / D conversion circuit 106 and the horizontal pixel shift processing circuit 10 are arranged from the image pickup device section 101.
Reference numeral 8 corresponds to a means for obtaining a high-density video signal, and the clock conversion processing circuit (1) 109 and the clock conversion control circuit 110 correspond to a dividing means for dividing into a plurality of images.

An image pickup apparatus having a plurality of images creating function according to the first embodiment of the present invention configured as described above will be described.

A plurality of R, G, and B output signals output from the image sensor unit 101 via the horizontal pixel shift unit 102 are analog signal processing circuits 105 and A / D conversion circuits 10.
It becomes a digital signal through 6. In the digital signal processing circuit (1) 107, the digital signal is processed by the horizontal pixel shift processing circuit 108 and the clock conversion processing circuit (1) 1
The luminance signal processing and the color signal processing are performed via 09, and the luminance signals (Y1, Y2) and the color signals (C1, C2) of two systems are output.

The horizontal pixel shift unit 102 in the image pickup device unit 101, the horizontal pixel shift processing circuit 108 and the clock conversion processing circuit (1) 109 in the digital signal processing circuit (1) 107 will be described below.

First, the image pickup device section 101 having the horizontal pixel shifting section 102 will be described with reference to FIG. The image pickup device section 101 has a 3CCD configuration. 5A shows the case without horizontal pixel shift, and FIG. 5B shows the case with horizontal pixel shift. The curve curve of each subject is an image pickup signal of the subject, and the circles attached to the curve curve are sample points. GCCD, RC
The hatched □ in the CD and BCCD is the light receiving portion of each CCD. In this way, the image pickup device section 101 is a 3 CCD
In the case of the configuration, the image pickup device section without the horizontal pixel shift section 102 has the light receiving sections of the G, R, B-CCDs spatially horizontal with respect to the sample points of the subject as shown in FIG. 5A. 5B, the image pickup device section having the horizontal pixel shift section 102 is arranged at the same position with respect to the light receiving section of the G-CCD for the sample points of the subject as shown in FIG. 5B. The light receiving portions of the B-CCDs are spatially displaced by 1/2 pixel in the horizontal direction.
Thus, when the luminance signal is obtained, the G signal and the other signal are added in the same amount to remove the aliasing component and obtain a high resolution.

As another example of the configuration of the image pickup device portion having the horizontal pixel shift portion, the image pickup device portion has a 4CCD configuration (G1,
G2, R, B-CCD) etc., in this case G1-C
The CD and G2-CCD are spatially displaced by 1/2 pixel.

Another block in the case where the image pickup device section has a horizontal pixel shift section having a 3CCD structure will be described below.

First, the operation of the horizontal pixel shift processing circuit will be described with reference to FIG. FIG. 6A shows the case of the Y signal (luminance signal), and FIG. 6B shows the case of the C signal (color difference signal). In the system in which the image pickup device section 101 has a horizontal pixel shift of 3 CCD configuration, the driving frequency of the CCD is f
In the case of ck, the optical filter provided in the CCD is designed to drop the frequency above fck. Although high resolution can be obtained by this, when considering each of R, G, and B, folding (moire) occurs. However, due to the horizontal pixel shift, the R and B moire components are inverted in phase with respect to the G moire component. Therefore, by adding R, G, and B in the signal processing operation, the moire is substantially removed. (However, moire does not disappear completely and remains to some extent). However, each C of R, G, B
In many cases, the circuits that drive the CDs are the same, and in fact C
The time position of the signal extracted from the CD is R in FIG.
The timing is similar to that of the B and G signals. Therefore, in order to restore the spatial position of the G signal, the G signal is delayed by 1T (T: 2fck rate), and the G signal (1Tde

Lay), then R, B, G signals (1T
delay) and next

The Y signal is obtained by performing the Y matrix calculation shown in the following equation.

[0043]

[Equation 1]

Further, the C signal is subjected to frequency band limiting filter processing for suppressing the occurrence of false color, etc.

After performing the following,

It is created by the arithmetic processing shown in Equation 2.

[0046]

[Equation 2]

However, in FIG. 6B, the R signal and the B signal are multiplexed, and the multiplexed R and B signals are divided by ½.
Is performed, and the signal and G signal (1
The case where a signal of 4: 2: 2 in which the number of samplings of each color signal is 1/2 of the number of samplings of the Y signal from Tdelay) is created is shown. Creates a 4: 4: 4 signal in which the number of pixels of the Y signal is equal to the number of samplings of each color signal.
Next, the operation of the clock conversion processing circuit (1) 109 will be described below. First, the outline of the clock conversion process will be described.

The clock conversion processing here is to convert the frequency of the reference clock in the digital signal processing circuit 107, and in this case, in the digital signal processing circuit 107, the first half clock (fck in FIG. 2). d
1, fck in Figure 3 d5) and the latter half clock (f in FIG. 2)
ck d2, fck in FIG. d6) and their clock frequency ratios are generally set to integer ratios in many cases.

For example, in the DV format which is a digital recording system, the sampling frequency is 13.5 [MH
z], the reference frequency of the digital signal processing of the image pickup unit, which is determined by the driving frequency of the CCD in the DV format movie, is the reference frequency of the digital signal processing of the recording unit in the digital signal processing.
Conversion to 3.5 [MHz] is performed.

As a concrete example, when the 960HCCD is used, the reference frequency of the digital signal processing of the image pickup section is 18 [MHz], and the clock conversion is performed to 13.5 [MHz] with an integer ratio of 4: 3. Further, when a 590HCCD is used as a CCD in the horizontal pixel shift system of the image pickup device section of the 3CCD structure, the driving frequency of the CCD is 11.25 [MHz],
The digital reference clock after the horizontal pixel shift processing is doubled to 22.5 [MHz], and the clock conversion processing performs clock conversion with an integer ratio of 5: 3. In addition, the 3CCD
CCD in the horizontal pixel shift method of the image pickup device section of the configuration
When the 710HCCD is used as the above, the driving frequency of the CCD is 13.5 [MHz], the digital reference clock after the horizontal pixel shift processing is doubled to 27 [MHz], and the clock with the integer ratio of 2: 1 by the clock conversion processing. Do the conversion.

The operation of this clock conversion process will be described below with reference to FIG.

FIG. 7 is a block diagram showing a configuration example of the clock conversion processing circuit (1) 109. In FIG. 7, the input video signal includes an interpolation processing circuit 401, an interpolation control circuit 402, a RAM 403, and a RAM control circuit 404.

Next, the interpolation processing circuit 4 which is a constituent element
An outline of the basic operation of 01 will be described with reference to FIGS. 8 and 9. FIG. 8 is a configuration example showing an outline of the operation in the case of linear linear interpolation as a basic interpolation processing circuit.
2 is a video input terminal, 503 and 504 are multipliers A and B, and 505 is an adder. As shown in FIG. 8, in the interpolation processing circuit, w and (1-w) are applied to two input signals.
Interpolation processing is performed using the interpolation coefficient of. As an example of this interpolation processing operation, FIG. 9 shows a compressed interpolation signal (A, B, C in the figure) interpolated from the input signal (a, b, c in the figure) at a compression rate of 3/4. The outline of the interpolation processing operation for obtaining In FIG. 9, the interpolation signal B is interpolated using the input signals b and c, and the interpolation signal B is interpolated using the input signals c and d. Therefore, the input signal is continuously shifted by one pixel. An interpolation signal of 2 pixels will be obtained. On the other hand, when the interpolated signal D is obtained, the interpolated signal is obtained by interpolating the input signals c and d necessary for obtaining the interpolated signal C by shifting the input signals e and f by 2 pixels at the same time.

It means that. For example, if the function I indicates an interpolation of 2 pixels,

[Equation 3]

[0055]

[Equation 3]

In this way, when the interpolation pixel C and the interpolation pixel D are obtained, processing such as discontinuous control of input signal selection is performed.

Next, the clock conversion processing circuit shown in FIG.
The outline of the interpolation processing in (1) is shown in FIG. 10, FIG. 11 and FIG.
Will be described with reference to.

FIG. 10 shows a basic configuration example of the interpolation processing circuit 401, and FIGS. 11 and 12 show the outline of the operation of the interpolation processing. In the interpolation processing circuit 401 shown in FIG.
1 is a video input terminal, 702 is a delay circuit for obtaining a required delay (here, 1 pixel), and 703 and 704 are multipliers A.
And the multipliers B and 705 are adders.

In the interpolation processing circuit configured as described above, the input signal from the signal processing unit in the preceding stage is delayed and the multiplication coefficient w and (1-w) are added to the synchronized signals of two pixels. Interpolation processing using the interpolation coefficient is performed. In addition, in FIGS. 11 and 12, the compression ratio is 3/4 from the input signal (a, b, c ... In the figure).
The spatial position of the interpolation processing when obtaining the interpolated signals (A, B, C in the figure) interpolated in (4) is shown. The interpolation signal by the interpolation process becomes an interpolation between two consecutive pixels, and the interpolation signal (each pixel including D0 in the figure) is first created by the interpolation process.
Here, the interpolation signal D0 is an unnecessary signal as an interpolation signal compressed to 3/4. For example, in the case of compressing to 3/4, 3 pixels are created from 4 pixels, so that an unnecessary interpolation signal of 1 pixel is generated for every 4 pixels. Although the interpolation signal D0 is shown here as being created by interpolating the d pixel and e pixel of the input signal, the interpolation coefficient is not particularly limited, and for example, the interpolation signal C The interpolation coefficient and the interpolation coefficient necessary for interpolating the interpolation signal D are controlled, and are determined by a method that is easy to control.

FIG. 11 shows a case where the interpolation signal D0 is created by the interpolation coefficient necessary for interpolating the interpolation signal D. That is, after the interpolation signal D0 is interpolated, the interpolation signal D is created with the same interpolation coefficient, and the interpolation signal E is created with a new interpolation coefficient. Therefore, as shown in FIG. 11, the interpolation coefficient control becomes discontinuous between the interpolation signal D0 and the interpolation signal D.

.. When this is expressed by the function I,

It becomes like [Equation 4].

[0062]

[Equation 4]

Interpolation signals (A,
RAM control circuit 404 performs write control so that only valid signals (A, B, C, D, E, ...) Of B, C, D0, D, E ,. The output signal of the RAM 403 becomes a 3/4 compressed signal (A, B, C, D, E ...).

Alternatively, all the interpolation signals (A, B, C, D0, D ...) Created in this way are temporarily stored in the RAM 40.
Also, the output signal of the RAM 403 is 3/4 compressed signal (A, B, C) by performing read control so that only valid signals (A, B, C, D, E ...) Are read.
B, C, D, E ...).

Next, the interpolation coefficient and memory writing control will be described.

As shown in FIG. 7, the interpolation control circuit 402 uses the R
The AM control circuit 404 is subjected to writing / reading control and interpolation coefficient control in the interpolation processing circuit 401. An example of the control is shown in FIG. As shown in FIG. 12, the interpolation process for creating the interpolated signal, that is, the input signal shown in FIG. 10 and the multiplication coefficient of the multiplier A703 and the multiplier B704 are

From the spatial position of the interpolated signal after interpolation,

It becomes like [Equation 4]. If the interval between the input signals is 1, the interval between the interpolation signals is 4/3. In this way, the spatial position of the interpolation signal is determined by adding 4/3, which is the reciprocal of the clock conversion ratio, to the initial value of the interpolation coefficient, but the fractional part of the addition result corresponds to the signal that does not pass through the delay circuit 702. The interpolation coefficient is W, and since it is a first-order interpolation, (1−W) is an interpolation coefficient for the delayed signal. At this time, when the integer part of the addition result is "1", the decimal part is the interpolation coefficient as described above, but when the integer part is "2", the interpolation coefficient of the interpolation signal is the next interpolation coefficient. It is held for use as an interpolation factor for the signal. Further, in the RAM control, the above-mentioned integer part of the addition result stops writing the interpolation signal (D0) of "2", and the memory output address is incremented by "+1" every time the interpolation signal is written.

FIG. 13 shows a circuit configuration example for realizing this processing. In FIG. 13, reference numeral 1001 is an interpolation coefficient initial value input terminal, 1002 is a clock conversion ratio input terminal, and 1003.
Is an interpolation signal interval conversion circuit for converting the clock conversion ratio into pitch information corresponding to the signal interval of the interpolation signal, 1004 is a pitch addition calculation circuit for calculating (cumulative addition) interpolation coefficient initial value information and pitch information, and 1005 is a pitch This is an interpolation control conversion circuit that outputs a memory control signal and an interpolation ratio control signal necessary for interpolation processing from the calculation result of the addition calculation circuit 1004, and performs the calculation processing shown in FIG. 12 to create a necessary control signal.

Thus, in the interpolation control control circuit 402,
The interpolation coefficient control and the writing / reading control for the RAM control circuit are performed, and first, the interpolation signals (A, B, C, D0, D
.) Is created, and the memory output signal is 3/4 compressed by controlling the memory write so that only the valid signals (A, B, C, D ...) Are written in the memory. C ...)

Furthermore, the RAM read operation is performed at a clock frequency that is 3/4 times the clock frequency of the interpolation processing operation and the RAM write operation, so that the 3/4 compressed signals (A, B, C) are obtained. ..) is image data obtained by performing clock conversion processing of 4: 3 on the input signal.

The above operation will be summarized with reference to FIG. FIG. 14 is a block diagram in which a necessary reference clock is added to FIG. 7, and as shown in FIG. 14, the input video signal is W-
An interpolation processing circuit 401, an interpolation control circuit 402 and a RAM control circuit W405 which are CLK system operation circuits, a RAM control circuit R406 which is an R-CLK system operation circuit, and a Write.
The (write) clock and the Read (read) clock are configured to include the RAM 407 having an independent configuration.

Next, the case where the clock conversion ratio is 4: 3 has been described as the basic operation of the clock conversion circuit, but the digital signal processing circuit (1) 107 for performing the horizontal pixel shift processing in FIG. 4 is provided below. The operation of creating a plurality of images in the clock conversion processing circuit (1) 109 will be described with reference to FIGS. 15 to 18, focusing on the points different from the case of the clock conversion ratio of 4: 3.

FIG. 15 shows a configuration example of the clock conversion processing circuit (1) 109 when the clock conversion ratio is 2: 1.
FIG. 16 shows the spatial positional relationship of the output signals of the clock conversion processing circuit (1) 109. W-CLK is 2 fck, RC
LK is fck, and the same parts as in FIG. 14 are indicated by the same numbers. The clock conversion processing circuit (1) includes an interpolation processing circuit 401, which is a W-CLK system operation circuit, and a RAM control circuit W.
405, a RAM control circuit R406 which is an R-CLK system operation circuit, and a processing circuit (a) 409 including a RAM 407 in which the write clock and the read clock are independently configured.
It also has a processing circuit (b) 410 and an interpolation control circuit 408 for controlling the interpolation processing of these processing circuits (a) and (b).

Next, the processing circuit (a) 40 is shown in FIGS.
The signal flow in FIG. 15 will be described as an outline of the operation of the processing circuit 9 and the processing circuit (b) 410. 17 and 18, the input signal, the operation of the interpolation processing circuit 401, the RAM control circuit W40
5, the output signal of the RAM 407 is shown.

As shown in FIGS. 17 and 18, in the interpolation processing for creating the interpolation signal, the processing circuit (a) 409 and the processing circuit (b) 410 differ from the difference between the initial values of the interpolation coefficients of 0 and 1. 17 are as shown in FIGS. 17 and 18, respectively. At this time, if the interval between the input signals is 1, the interval between the interpolation signals is 2/1. As shown in the figure, the spatial position of the interpolation signal is determined by adding 2/1 which is the reciprocal of the clock conversion ratio to the initial value of the interpolation coefficient. The decimal part of the addition result is the position between pixels of the interpolated pixel, that is, the multiplication coefficient of the multiplier B 704 of the interpolation processing circuit 401 which is the basic configuration example shown in FIG. 10, that is, the interpolation coefficient for a signal that does not pass through the delay circuit 702. Since W is W, which is a first-order interpolation, (1−W) is an interpolation coefficient for the delayed signal. Also, the integer part of the addition result indicates the selection position of the pixel to be interpolated to create the interpolation pixel, and RA
This is the M write control information. For example, when the integer part is "1" or less, the decimal part becomes the interpolation coefficient and the interpolation signal is written to the RAM as described above, and the decimal part is the reciprocal of the clock conversion ratio for the next interpolation signal generation. Is added.

On the other hand, when the integer part is "2" or more, the writing is stopped, and the interpolation coefficient which is the decimal part at that time is held to be used as the interpolation coefficient of the next interpolation signal, Subtract one. By repeating this operation, the regular interpolation signal is written in the RAM. Also, the write address is incremented by 1 for each writing. This is the function

Expressed by I, FIGS. 17 and 18 respectively show

[Equation 5] and

It becomes like [Equation 6].

[0078]

[Equation 5]

[0079]

[Equation 6]

Thus, in the clock conversion processing circuit (1), as shown in FIGS. 15, 17, and 18, the generated interpolation signals (A, B0, B, C0, C, D0, D, ...) Of these, RAM only valid signals (A, B, C, D, ...)
The RAM control circuit W405 performs write control so that data is written in 407, and thus the output signal of the RAM 407 is clock-converted to a signal (A, B, C,
D, E ...). Further, by the initial value control of the interpolation processing of the interpolation control circuit 408, the clock-converted output signals from the processing circuits (a) and (b) are spatially horizontal at the clock rate of the input signal. This corresponds to a signal shifted by one pixel (see FIG. 16).

As described above, the two signals (Y1, C1) from the clock conversion processing circuit (1) 109 are output as the output signal of the digital signal processing circuit (1) 107 in FIG.
And (Y2, C2) are obtained, and the encoder (a) 11
1 and the encoder (b) 112 produce a TV signal.
The clock conversion ratio of these two systems of signals is 2: 1.
In the system (1), the signal is horizontally shifted by one sampling at the frequency before clock conversion, and is the signal shifted by one pixel of the double density pixel in the horizontal pixel shift processing.

In other words, the signals of the two systems are divided into two systems at the fck clock rate by dividing the odd-numbered signal and the even-numbered signal of the double-density signal of the 2fck clock rate created by the horizontal pixel shift processing. Will be output as a signal (see FIG. 16).

As described above, in the first embodiment, the horizontal pixel shift unit 102, the horizontal pixel shift processing circuit 108 and the clock conversion processing circuit (1) 109 are provided,
It is possible to obtain two screen images at the same time at the output clock frequency rate. Moreover, since the images of these two screens have not been subjected to interpolation processing or the like, there is no deterioration in image quality. By synthesizing the images of these two screens by shifting one sampling at a frequency twice the output clock frequency, a high image quality double density is obtained. It is possible to create the image of (see FIG. 16).

In the first embodiment, the case where the clock conversion ratio is 2: 1 for performing the horizontal pixel shift processing has been described, but the case where the clock conversion ratio is 2: 1 without the horizontal pixel shift processing ( For example, if the CCD has 1440 pixels and the drive frequency of 27 MHz is converted to 13.5 MHz)
In the same manner as described above, it is possible to obtain two screen images at the same time at the output clock frequency rate, and since these two screen images are not subjected to interpolation processing or the like, there is no deterioration in image quality. It is possible to create a high-quality double-density image by synthesizing images of two screens by shifting by one sampling at a frequency twice the output clock frequency. The clock conversion ratio of 4: 3 (for example, CCD is 960) explained as the basic operation of the clock conversion circuit in the case of other clock conversion ratios without horizontal pixel shift processing.
In the case of H), a horizontal 960-pixel video signal is once enlarged by zooming to 1440 pixels (corresponding to 1.5 times zoom) by interpolation processing, and then the clock conversion ratio of 2: 1 is performed, or By performing the interpolation processing of 0.75 times which is the product of the zoom magnification and the clock conversion ratio, it is possible to obtain two screen images at the same time at the output clock frequency rate. However, since the two screen images in this case are interpolated, the clock conversion ratio is 2:
Although the image quality is inferior to the case of 1, the output image at the output sampling frequency rate after clock conversion (one screen)
Therefore, it is possible to create a still image with less deterioration in image quality as compared with the case of creating a two-screen image by creating an interpolation screen portion (corresponding to 2 × zoom) by interpolation processing or the like.

Also, two systems of signals (Y1, which are output signals of the digital signal processing circuit (1) 107 in FIG.
When C1) and (Y2, C2) are connected to a display device such as a monitor or a recording device (neither is shown) in the next stage, the input terminal is often one system. FIG. 19 is a block diagram showing an example of a configuration having a one-system output function for this purpose. 19, the same parts as those in FIG. 4 are indicated by the same numbers, and different parts will be mainly described.

An image pickup apparatus with a plural image forming function having a one-system output function shown in FIG. 19 is a digital signal processing circuit.
(1) Total control of the entire system including the field memory circuit 114 for recording / reproducing the output signal of 107, the field memory control circuit 115 for controlling the field memory circuit 114, the clock conversion control circuit 110, and the field memory control circuit 115 The system control circuit 116 is included.

In this configuration, the A / D conversion circuit 106 and the horizontal pixel shift processing circuit 10 are arranged from the image pickup device section 101.
8, a means for obtaining a high-density video signal, a dividing means for dividing the clock conversion processing circuit (1) 109 and the clock conversion control circuit 110 into a plurality of images, a field memory circuit 114,
The field memory control circuit 115 corresponds to an image output means, and the system control circuit 116 corresponds to an image composition information creation means.

An image pickup apparatus having a multiple image generation function having a one-system output function configured as described above will be described.
In the digital signal processing circuit (1) 107, the horizontal pixel shift processing circuit 108 and the clock conversion processing circuit (1) 1
The luminance signal processing and the color signal processing are performed via 09, and two systems of signals (Y1, C1) and (Y2, C2) are output. This output signal is recorded in the field memory circuit 114 and then sequentially output as a luminance signal (Y3) and a color signal (C3) over a two-field period. Alternatively, one of the two signals (for example, (Y1, C1)) is output without passing through the field memory circuit, and the other signal (in this case (Y2, C2)) is output from the field memory circuit 1.
It is recorded in 14 and is output one field later.

As described above, in the first embodiment, the field memory circuit 114 and the field memory control circuit 115 for controlling the field memory circuit 114 are further provided, so that the output clock frequency rate is 2 times at the same time.
It is possible to obtain a screen image and sequentially output the two screen images under the control of the system control circuit 116 over a two-field period. Moreover, since the images of these two screens are not subjected to interpolation processing or the like, there is no deterioration in image quality, and the images of these two screens are linked to the field control in the system control circuit, and one sampling is performed at a frequency twice the output clock frequency. By shifting and synthesizing, it is possible to create a high-quality double-density image. (Second Embodiment) FIG. 20 is a block diagram of an image pickup apparatus having a plural image creating function according to a second embodiment of the present invention. 20, the same parts as those in FIG. 19 are denoted by the same reference numerals, and different parts will be mainly described.

The image pickup apparatus with a function of creating a plurality of images according to the present embodiment includes a digital signal processing circuit (2) 117 having a horizontal pixel shift processing circuit 108 and a clock conversion processing circuit (2) 118, a clock conversion processing circuit (2). ) 118, a clock conversion control circuit 119, a field memory circuit 120 that records and reproduces the output signal of the digital signal processing circuit (2) 117, a field memory control circuit 121 that controls the field memory circuit 120, and a clock conversion control circuit 119. System control circuit 122 for comprehensively controlling the entire system including field memory control circuit 121
It is configured to include.

In this structure, the A / D conversion circuit 106 and the horizontal pixel shift processing circuit 10 are arranged from the image pickup device section 101.
8, a means for obtaining a high-density video signal, a dividing means for dividing the clock conversion processing circuit (2) 118 and the clock conversion control circuit 119 into a plurality of images, a field memory circuit 120,
The field memory control circuit 121 corresponds to the image output means, and the system control circuit 122 corresponds to the image composition information creation means.

An image pickup apparatus having a plural image creating function according to the second embodiment having the above-mentioned structure will be described. Similar to FIG. 19, the plurality of R, G, and B output signals output from the horizontal pixel shift unit 102 in the image sensor unit 101 are analog signal processing circuits 105 and A / D conversion circuits 1.
It becomes a digital signal through 06. In the digital signal processing circuit (2) 117, the digital signal is processed by the horizontal pixel shift processing circuit 108 and the clock conversion processing circuit (2).
Through 118, luminance signal processing and color signal processing are performed, and a luminance signal (Y1) and a color signal (C1) are output. This output signal is output as a luminance signal (Y3) and a color signal (C3) after being written and read by the field memory circuit 120, and becomes a TV signal by the encoder (a) 111.

Next, the clock conversion processing circuit in FIG.
(2) The operation of 118 will be described with reference to FIG. FIG. 21 is a block diagram showing a configuration example of the clock conversion processing circuit (2) 118, in which the clock conversion ratio is 2: 1, that is, W-CLK is 2fck and R-CLK is fck.
Further, it corresponds to one system of the clock conversion processing circuit (1) shown in FIG. 12, and is shown by the same number as in FIG.

The clock conversion processing circuit (2) uses the W-CLK
An interpolation processing circuit 401 which is a system operation circuit, a RAM control circuit W405, an interpolation control circuit 408, a RAM control circuit R406 which is an R-CLK system operation circuit, and a RAM 407 in which a write clock and a read clock are independently configured. Have The clock conversion processing circuit shown in FIG.
In (2), the processing shown in FIG. 17 and FIG. 18 can be performed by the interpolation coefficient initial value control of the interpolation control circuit 408. For example, by switching the processing of FIG. 17 and FIG. It is possible to obtain the output signal of the processing circuit (1) and obtain the output signal of the processing circuit (2) in the even field.

Further, the digital signal processing circuit (2) 117
Output signal (Y1, C1) of the field memory circuit 1
In the next field, the output signal (Y1, C1) of the digital signal processing circuit (2) 117 and the output signal of the field memory circuit (Y
3, C3) two signals are obtained. These two-system signals are the two-system signals (Y1, C1); (Y
2, C2), in a system with a clock conversion ratio of 2: 1, the signal is shifted by one sampling at the pre-clock conversion frequency in the horizontal direction, and it corresponds to one double density pixel in the horizontal pixel shift processing. It is a shifted signal. Also,
The signals of the two systems are signals which are obtained by dividing the odd-numbered signal and the even-numbered signal of the double-density signal of 2fck clock rate created by the horizontal pixel shift processing into two systems at the fck clock rate.

As described above, in the second embodiment, the horizontal pixel shift unit 102, the horizontal pixel shift processing circuit 108, and the clock conversion processing circuit (2) 118 are provided.
Since no interpolation processing or the like is performed, it is possible to sequentially output two screen images at an output clock frequency rate without image quality deterioration as one system output signal over two field periods.

Further, by providing the field memory circuit 120, it is possible to obtain images of two screens at the same time, and when the field memory circuit 120 has a capacity of two fields (= 1 frame) or more, It is also possible to store the two systems of signals in the field memory circuit 120.

Moreover, since the images of the two screens are not subjected to the interpolation processing or the like, the image quality is not deteriorated, and the images of the two screens are linked with the field control in the system control circuit and the frequency of the output clock frequency is doubled. It is possible to create a high-quality double-density image by synthesizing after shifting by one sampling.

(Third Embodiment) FIG. 22 is a block diagram of an image pickup apparatus having a plurality of images creating function according to a third embodiment of the present invention. In FIG. 22, FIG.
Common parts are indicated by the same numbers, and different parts will be mainly described.

As shown in FIG. 22, the image pickup apparatus with a plural image forming function is provided with an image pickup element section 131 having a photoelectric conversion function.
The horizontal pixel shift unit 102 and the vertical pixel shift unit 132 included in the image sensor unit 131, the image sensor drive circuit 133 for the image sensor unit 131, the drive control circuit 134 that controls the image sensor drive circuit 103, and the output signal of the image sensor unit 131 An analog signal processing circuit 105 that performs processing such as sampling and amplification, an analog-digital conversion circuit (hereinafter referred to as A / D conversion circuit) 106 for the output signal of the analog signal processing circuit 105, and a luminance signal from the A / D converted digital signal. Signal processing circuit (3) 135 for generating a color signal, color difference signal, or RGB signal processing, a horizontal pixel shift processing circuit 108, a vertical pixel shift processing circuit 136, and a clock conversion provided in the digital signal processing circuit (3) 135 The clock circuit that controls the processing circuit (3) 137 and the clock conversion processing circuit (3) 137. Click conversion control circuit 138,
From the output signal of the digital signal processing circuit (3) 135 to NT
A system control circuit 140 that comprehensively controls an encoder (a) 111 that obtains an interlaced television signal such as an SC signal, a PS encoder 139 that obtains a progressive television signal, a drive control circuit 134, and a clock conversion control circuit 138. It is configured to include.

In this configuration, the A / D conversion circuit 106 and the horizontal pixel shift processing circuit 10 are arranged from the image pickup device section 131.
8 and the vertical pixel shift processing circuit 136 correspond to a means for obtaining a high-density video signal, and the clock conversion processing circuit (3) 137 and the clock conversion control circuit 138 correspond to a dividing means for dividing into a plurality of images.

An image pickup apparatus having a plural image forming function according to the third embodiment of the present invention having the above structure will be described.

The plurality of R, G, and B output signals output through the horizontal pixel shift unit 102 and the vertical pixel shift unit 132 in the image pickup device unit 131 are analog signal processing circuits 1.
It becomes a digital signal through 05 and the A / D conversion circuit 106. This digital signal is a digital signal processing circuit
(3) In 135, the horizontal pixel shift processing circuit 108,
The vertical pixel shift processing circuit 136 and the clock conversion processing circuit (3) 137 are used to perform luminance signal processing and color signal processing.
System luminance signals (Y1, Y2, Y3, Y4) and color signals (C1, C2, C3, C4) are output. Figure 19 below
A vertical pixel shift unit 132, a vertical pixel shift processing circuit 136, and a clock conversion processing circuit (3) 137 different from the above will be described.

First, the operations of the vertical pixel shift unit 132 and the vertical pixel shift processing circuit 136 provided in the image pickup device section will be described. As described in the conventional example, when the image pickup device unit has the 3CCD structure, the image pickup device unit without the vertical pixel shift unit has the G, R, B-type as shown in FIG.
While the output signal of the CCD is spatially in phase with the vertical direction, in the image pickup device section having the vertical pixel shift section, as shown in FIG. The output signal of the B-CCD is spatially shifted by 1/2 line and output. As a result, in the case of no vertical pixel shift (a), the luminance signal (Y) and the color signal (C) are created at the same phase position as the output signal of the G, R, B-CCD, whereas the vertical pixel is not. When the shift is present (b), the vertical pixel shift processing circuit 136 has a total of two systems of luminance signals (Y) at the same phase position as the G-CCD output signal and at the same phase position as the R / B-CCD output signal. And a color signal (C) can be created.

For the luminance signal and the color signal of these two systems,
Performs clock conversion processing. Next, the clock conversion processing circuit
The operation (3) will be described. FIG. 23 shows a configuration example of the clock conversion processing circuit (3) 137, and FIG. 24 shows a spatial positional relationship of output signals of the clock conversion processing circuit (3) 137.
The same parts as those of FIG. 15 shown in the first embodiment are indicated by the same numbers, and different parts will be mainly described. In the clock conversion processing circuit (3) shown in FIG. 22, the clock conversion processing is performed on each of the two output signals from the vertical pixel shift processing circuit 136 at the preceding stage. As a result, the four signals (Y1, C1) from the clock conversion processing circuit (3) are output as the output signals of the digital signal processing circuit (3) in FIG.
(Y2, C2), (Y3, C3), (Y4, C4) are obtained, and the interlace TV signal can be obtained by the encoder (a) 111 and the progressive TV signal can be obtained by the PS encoder 139.

Of the four systems of signals, the two systems of signals (Y1, C1) and (Y2, C2) and (Y3, C3) and (Y4, C4) have a clock conversion ratio of 2: 1. Is a signal that is shifted in the horizontal direction by one sampling at the frequency before clock conversion, that is, a signal that is shifted by one pixel of double density pixels in the horizontal direction in the horizontal pixel shift processing. Also, (Y1, C1) and (Y3, C3) and (Y
2, C2) and (Y4, C4), each of the two systems of signals are signals that are vertically displaced by one line in the frame line in the vertical pixel shift system (see FIG. 24).

As described above, in the third embodiment, the horizontal pixel shift unit 102, the horizontal pixel shift processing circuit 108, the vertical pixel shift unit 132, and the vertical pixel shift processing circuit 13 are used.
By including 6 and the clock conversion processing circuit (3) 137, it is possible to obtain a field image of 4 screens or a frame image of 2 screens at the same time at the output clock frequency rate. Moreover, the image of the four screens is a signal obtained by pixel shift processing, and the image of the four screens is horizontally shifted by one sampling at a frequency twice the output clock frequency and further vertically shifted by one line in the frame. By synthesizing, it is possible to create a high-quality quadruple-density image (see FIG. 24).

Further, four systems of signals (Y1, C1) which are output signals of the digital signal processing circuit (3) in FIG.
1), (Y2, C2), (Y3, C3) and (Y4, C4)
Is connected to a display device such as a monitor or a recording device (both not shown) in the next stage, the input terminal is often one system. A block diagram of a configuration example having a one-system output function for this purpose is shown in FIG. In FIG. 25, portions common to those in FIGS. 19 and 22 are indicated by the same numbers, and different portions will be mainly described.

An image pickup apparatus with a multiple image generation function having a one-system output function shown in FIG. 25 is a digital signal processing circuit.
(3) Total control of the entire system including the field memory circuit 141 that records and reproduces the output signal of 135, the field memory control circuit 142 that controls the field memory circuit 141, the clock conversion control circuit 138, and the field memory control circuit 142 The system control circuit 143 is included.

In this configuration, the A / D conversion circuit 106 and the horizontal pixel shift processing circuit 10 are arranged from the image pickup device section 131.
8 and the vertical pixel shift processing circuit 136 obtains a high-density video signal, the clock conversion processing circuit (3) 137 and the clock conversion control circuit 138 divide the image into a plurality of images, the field memory circuit 141 and the field memory control. The circuit 115 is an image output means and a system control circuit 143.
Corresponds to the image composition information creating means.

An image pickup apparatus having a multiple image generation function having a one-system output function configured as described above will be described.
In the digital signal processing circuit (3) 135, the horizontal pixel shift processing circuit 108 and the vertical pixel shift processing circuit 136
And the signals of four systems (Y1, C1) which have been subjected to luminance signal processing and color signal processing through the clock conversion processing circuit (3) 137,
(Y2, C2), (Y3, C3) and (Y4, C4) are output. This output signal is the field memory circuit 141.
After the recording, the luminance signal (Y5) and the color signal (C5) are sequentially output over a period of 4 fields. Or among the signals of the four systems (Y1, C1) and (Y3, C3)
And (Y2, C2) and (Y4, C4) are divided into two systems of signals and recorded in the field memory circuit 141 as two systems of progressive signals and output one field later.

As described above, in the present embodiment, the field memory circuit 141 and the field memory control circuit 142 for controlling the field memory circuit 141 are further provided to obtain four screen images at the same time at the output clock frequency rate. Images of four screens can be sequentially output over a period of two fields or four fields. Moreover, the image of the four screens is a signal obtained by pixel shift processing, and the image of the four screens is horizontally shifted by one sampling at a frequency double the output clock frequency in conjunction with the field control of the system control circuit. It is possible to create a high-quality quadruple-density image by shifting by one line in the frame in the vertical direction and combining.

(Fourth Embodiment) FIG. 26 is a block diagram of an image pickup apparatus having a plurality of images forming function according to a fourth embodiment of the present invention. 25 in FIG.
Common parts are indicated by the same numbers, and different parts will be mainly described.

The image pickup apparatus with a plurality of image forming functions according to the present embodiment has a horizontal pixel shift processing circuit 108, a vertical pixel shift processing circuit 136, and a clock conversion processing circuit (4) 1.
A digital signal processing circuit (4) 144 provided with 45, a clock conversion control circuit 146 for controlling the clock conversion processing circuit (4) 145, a field memory circuit 147 for recording and reproducing the output signal of the digital signal processing circuit (4) 144, A field memory control circuit 148 for controlling the field memory circuit 147, a system control circuit 149 for comprehensively controlling the entire system including the clock conversion control circuit 146 and the field memory control circuit 148 are included.

In this configuration, the A / D conversion circuit 106 and the horizontal pixel shift processing circuit 10 are arranged from the image pickup device section 131.
8 and the vertical pixel shift processing circuit 136 obtains a high density video signal, the clock conversion processing circuit (4) 145 and the clock conversion control circuit 146 divides the image into a plurality of images, the field memory circuit 147 and the field memory control. The circuit 148 is an image output means and a system control circuit 149.
Corresponds to the image composition information creating means.

An image pickup apparatus having a plural image forming function according to the fourth embodiment having the above-mentioned structure will be described. As in FIG. 25, the plurality of R, G, and B output signals output via the horizontal pixel shift unit 102 and the vertical pixel shift unit 132 in the image sensor unit 131 are analog signal processing circuits 1.
It becomes a digital signal through 05 and the A / D conversion circuit 106. This digital signal is a digital signal processing circuit
(4) In 144, the horizontal pixel shift processing circuit 108,
Luminance signal processing and color signal processing are performed through the vertical pixel shift processing circuit 138 and the clock conversion processing circuit (4) 145, and luminance signals (Y1, Y3) and color signals (C1, C3) are output. This output signal is output as a luminance signal (Y5 and Y6) and a color signal (C5 and C6) after writing and reading processing in the field memory circuit 147, and the encoder (a) 111 outputs the interlaced TV signal and the PS encoder 139. Thus, a progressive TV signal can be obtained.

Next, the clock conversion processing circuit in FIG.
(4) The operation of 145 will be described with reference to FIG. FIG. 27 is a block diagram showing a configuration example of the clock conversion processing circuit (4) 145, and the clock conversion ratio is 2: 1, that is, W-CLK is 2fck and R-CLK is fck.
Further, this corresponds to a case where the clock conversion processing circuit (2) shown in FIG. 21 has two systems, and is shown by the same number as in FIG.

The clock conversion processing circuit (4) uses the W-CLK
An interpolation processing circuit 401 which is a system operation circuit, a RAM control circuit W405, an interpolation control circuit 408, a RAM control circuit R406 which is an R-CLK system operation circuit, and a RAM 407 in which a write clock and a read clock are independently configured. Have The clock conversion processing circuit shown in FIG.
In (4), the processing shown in FIGS. 17 and 18 can be performed by the interpolation coefficient initial value control of the interpolation control circuit 408. For example, by switching the processing of FIGS. 17 and 18 for each field, The output signal of the processing circuit (a) can be obtained in the field (eg, odd field), and the output signal of the processing circuit (b) can be obtained in the next field (eg, even field).

Further, the digital signal processing circuit (4) 144
By storing the output signals (Y1, C1) and (Y3, C3) in the field memory circuit 147 during the first field, the output signals (Y1, C1) from the digital signal processing circuit (4) 144 during the next field. , (Y3, C
3) and field memory circuit output signals (Y5, C5) and (Y6, C6), a total of four systems of signals are simultaneously obtained. Of these four systems of signals, the two systems of signals (Y1, C1) and (Y5, C5) and (Y3, C3) and (Y6, C6) are in the horizontal direction in a system with a clock conversion ratio of 2: 1. Is a signal shifted by one sampling at the frequency before clock conversion, and the signals of each of the two systems (Y1, C1) and (Y5, C5) and (Y2, C2) and (Y6, C6) are shifted by vertical pixels. This is a signal that is shifted by one frame line in the vertical direction in the system (see FIG. 24).

As described above, in the present embodiment, the horizontal pixel shift unit 102, the horizontal pixel shift processing circuit 108, the vertical pixel shift unit 132, the vertical pixel shift processing circuit 136, and the clock conversion processing circuit (4) 145 are provided. , 4 screen field images at output clock frequency rate 2
It is possible to sequentially output over the field period.
Further, by including the field memory circuit 147, it is possible to sequentially output the frame images of two screens over the period of two fields.

Moreover, the images on the plurality of screens are signals obtained by the pixel shift processing, and the images on the four screens are linked to the field control of the system control circuit and horizontally 1 at the frequency double the output clock frequency. It is possible to create a high-quality quadruple-density image by shifting by sampling and shifting by one line in the vertical direction and combining (see FIG. 24).

(Fifth Embodiment) FIG. 28 is a block diagram of an image pickup apparatus having a plurality of images creating function according to a fifth embodiment of the present invention. In FIG. 28, FIG.
Common parts are indicated by the same numbers, and different parts will be mainly described.

The image pickup apparatus with a plurality of images forming function according to the present embodiment has a clock conversion unit (1) 151 having a clock conversion front FLT 152, a selector circuit 153, and a clock conversion processing circuit (2) 118, horizontal pixel shift processing. The digital signal processing circuit (5) 150 including the circuit 108 and the clock conversion unit (1) 151, the clock conversion control circuit 154 for controlling the clock conversion unit (1) 151, and the output signal of the digital signal processing circuit (5) 150 A system control circuit 156 that comprehensively controls the entire system including a field memory circuit 120 for recording / reproducing, a field memory control circuit 121 for controlling the field memory circuit 120, a clock conversion control circuit 154, a field memory control circuit 121, and a selection circuit 155. It is configured to include.

An image pickup apparatus having a plural image forming function of the fifth embodiment configured as described above will be described. As in FIG. 20, the plurality of R, G, and B output signals output from the horizontal pixel shift unit 102 in the image pickup device unit 101 include the analog signal processing circuit 105 and the A / D conversion circuit 1.
It becomes a digital signal through 06. In the digital signal processing circuit (5) 150, the digital signal is processed by the horizontal pixel shift processing circuit 108 and the clock conversion unit 151 (1).
Luminance signal processing and color signal processing through the luminance signal (Y
1) and the color signal (C1) are output. This output signal is input to the selection circuit 155 together with the Y1 and C1 after being written and read by the field memory circuit 120.

Next, the clock conversion unit (1) 1 in FIG.
The operation of 51 will be described. Clock converter (1) 15
In the case of 1, the selector circuit 1 is used to obtain image signals of two screens.
53 selects the through side of the clock conversion front FLT 152, and the clock conversion processing circuit (2) 118 shown in FIG.
Processing similar to that of the image pickup apparatus with a multiple image generation function according to the second embodiment indicated by 0 is performed.

On the other hand, in the case of normal moving image shooting, it is necessary to obtain an image for each field, and the clock conversion processing circuit
(2) At 118, fck the image signal of 2 fck rate
In the case of outputting at a rate, since a fold (moisture) signal is generated, FLT processing for band limitation is necessary, and therefore the selector circuit 153 causes the clock conversion front FLT 15 to operate.
2 is selected, and the clock conversion processing circuit (2) 118 outputs an image at the fck rate according to the interpolation ratio control of the clock conversion control circuit 154. Note that a folding signal is generated in each screen even when the plurality of screens are created, but since the phase of the folding component is inverted for each created screen, the folding component is removed by the combining process.

Next, the output signal (Y1, C1) of the clock conversion unit (1) 151 corresponds to, for example, the field memory circuit 120 when the image signal of two screens is obtained.
The image signal for the screen is recorded for two field periods, and is output as a high-quality still image synthesizing signal through the selection circuit 155 at a necessary timing. On the other hand, in the case of normal moving image shooting, it is output as a continuous field image signal through the selection circuit 155.

As described above, in this embodiment, the digital signal processing circuit including the horizontal pixel shift unit 102, the horizontal pixel shift processing circuit 108, the clock conversion front FLT 152, the selector circuit 153, and the clock conversion processing circuit (2) 118. (5) By including 150, a moving image with no aliasing signal can be obtained at the time of shooting a moving image at the output clock frequency rate, and a two-screen image with no deterioration in image quality without interpolating processing at the time of shooting a still image can be obtained. It is possible to output sequentially over a period of time.

(Sixth Embodiment) FIG. 29 is a block diagram of an image pickup apparatus having a plurality of images creating function according to a sixth embodiment of the present invention. In FIG. 29, FIG.
28 and common parts are indicated by the same numbers, and different parts will be mainly described.

The image pickup apparatus with a function of creating a plurality of images according to the present embodiment has a clock conversion unit (2) 158 provided with a clock conversion front FLT 159, a selector circuit 160 and a clock conversion processing circuit (4) 145, and vertical pixel shift processing. Digital signal processing circuit (6) 15 including circuit 136, horizontal pixel shift processing circuit 108, and clock conversion unit (2) 158
7, a clock conversion control circuit 161 for controlling the clock conversion unit (2) 158, a field memory circuit 147 for recording and reproducing the output signal of the digital signal processing circuit (6) 157,
A system control circuit 163 that comprehensively controls the entire system including a field memory control circuit 148 that controls the field memory circuit 147, a clock conversion control circuit 161, a field memory control circuit 148, and a selection circuit 162.
It is configured to include.

An image pickup apparatus having a plurality of images creating function of the sixth embodiment configured as described above will be described. Similar to FIG. 26, the plurality of R, G, and B output signals output via the horizontal pixel shift unit 102 and the vertical pixel shift unit 132 in the image pickup device unit 131 are the analog signal processing circuit 1.
It becomes a digital signal through 05 and the A / D conversion circuit 106. This digital signal is a digital signal processing circuit
(6) In 157, the vertical pixel shift processing circuit 138,
Horizontal pixel shift processing circuit 108 and clock conversion unit (2)
Through 158, luminance signal processing and color signal processing are performed, and luminance signals (Y1, Y3) and color signals (C1, C3) are output.
This output signal is input to the selection circuit 162 together with the output signal of the digital signal processing circuit (6) after writing / reading processing in the field memory circuit 147.

Next, the clock conversion unit (2) 1 in FIG.
The operation of 58 will be described. Clock converter (2) 15
8, in the case of obtaining a plurality of image signals such as four screens as in FIG. 28, the selector circuit 160 uses the clock conversion front FLT1.
The through side of 59 is selected, and the following clock conversion processing circuit
(4) At 145, the same processing as that performed by the image pickup apparatus with a multiple image creation function according to the fourth embodiment shown in FIG. 27 is performed.

On the other hand, in the case of normal moving image shooting, it is necessary to obtain an image for each field, and the clock conversion processing circuit (4) 118 outputs an image signal of 2 fck rate to fc.
In the case of outputting at the k rate, since a folded (moire) signal is generated, FLT processing for band limitation is necessary.
9 Select the via side, and clock conversion processing circuit (4) 145
In, the two systems of images at the fck rate are output according to the interpolation ratio control of the clock conversion control circuit 161. In addition, a folding signal is generated in each screen even when a plurality of screens are created in this case, but since the phase of the folding component is inverted in each created screen, the folding component is removed by the combining process.

Next, when the output signals (Y1, C1) and (Y3, C3) of the clock conversion unit (2) 158 are to obtain the image signals of four screens, for example, the field memory circuit 147 outputs four fields (= When the memory capacity is 2 frames), the image signals for a plurality of screens corresponding to the same subject are all recorded over a 2-field period, and output as a high-quality still image synthesizing signal through the selection circuit 162 at a necessary timing. To be done. On the other hand, in the case of normal moving image shooting, it is output as a continuous field image signal through the selection circuit 162.

As described above, in the present embodiment, the horizontal pixel shift unit 102, the vertical pixel shift unit 132, the horizontal pixel shift processing circuit 108, and the vertical pixel shift processing circuit 136.
And clock conversion front FLT 159 and selector circuit 160
And a digital signal processing circuit (6) 157 having a clock conversion processing circuit (4) 145 are provided to obtain a moving image with no aliasing signal when shooting a moving image at the output clock frequency rate, and an interpolation process when shooting a still image. It is possible to sequentially output images of four screens which have not been subjected to the above and have no image quality deterioration over a period of four fields.

The image pickup apparatus with a plural image creation function in the fifth and sixth embodiments is different from the image pickup apparatus with a plural image creation function in the second and fourth embodiments, respectively, at the time of shooting a moving image and at the time of still image shooting. Although a high-quality image can be obtained at the time of image capturing, the same effect can be obtained for the image pickup apparatus with a plurality of image creation functions according to the first and third embodiments. It is possible.

FIG. 30 is a block diagram of an image pickup apparatus and an image pickup system with a plural image creating function according to the second basic embodiment of the present invention. As shown in Figure 30,
The image pickup apparatus with a function of creating a plurality of images includes a high-density video signal creating means 201, an image dividing means 202, an image outputting means 203,
The image synthesis information creating means 204 and the image synthesizing means 205 are included.

In the image pickup apparatus with a plurality of image forming functions according to the second basic embodiment configured as described above, the image signal generated by the high density image signal generating means 201 is processed by the image dividing means 202. Divided image output means 20
Output by 3. At this time, the high-density video signal creating means 2
When the video signal created in 01 has a higher density than the video signal of the output sampling frequency rate of the image output means 203, a high image quality is obtained by synthesizing a plurality of video signals divided into images and output at the output sampling frequency rate. Video can be created. Further, at this time, the image composition information creating means 2
04 creates and outputs information related to image division and output by the image dividing unit 202 and the image output unit 203, and the image combining unit 205 can operably combine a plurality of video signals to create a high-quality image. is there. Figure 3 below
A specific description will be given of the image pickup apparatus with a multiple image generation function in the second basic embodiment shown by 0.

(Seventh Embodiment) FIG. 31 is a block diagram of an image pickup apparatus having a plurality of images creating function according to a seventh embodiment of the present invention. 29 in FIG.
Common parts are indicated by the same numbers, and different parts will be mainly described.

The image pickup apparatus with a plural image forming function according to the present embodiment includes an image pickup section 165 including a selection circuit 162, an output image control circuit 163, and a system control circuit 164 from the image pickup element section 131 shown in FIG. A recording processing circuit 166, a memory circuit 167, a recording medium 168, a reproduction processing circuit 169, a selection circuit 170 for selecting a reproduction image and a captured image, a recording / reproduction control circuit 171 for controlling the recording processing circuit 166 and the reproduction processing circuit 169, and these. A recording / reproducing unit 172 composed of a recording processing circuit 166 to a recording / reproducing control circuit 171, an image combining processing circuit 173, a memory circuit 174, an image combining control circuit 175 for controlling the image combining processing circuit 173 and the memory circuit 174, The image composed of these image composition processing circuit 173 to image composition control circuit 175. It is configured to include a synthesis section 176.

In this configuration, the A / D conversion circuit 106 and the horizontal pixel shift processing circuit 10 are separated from the image pickup device section 131.
8 and the vertical pixel shift processing circuit 136 obtains a high-density video signal, the clock conversion processing circuit (4) 145 and the clock conversion control circuit 161 divides the image into a plurality of images, the field memory circuit 147 and the field memory control. Circuit 148, selection circuit 162, and output image control circuit 16
3 corresponds to an image output unit, the system control circuit 164 corresponds to an image composition information creating unit, and the image composition unit 176 corresponds to an image composition unit.

The image pickup apparatus having a plurality of images forming function of the seventh embodiment configured as described above will be described focusing on the points that are largely different from those in FIG.

First, the image pickup section 165 includes an output image control circuit 163 controlled by the system control circuit 164, a field memory control circuit 148 and a selection circuit 162.
To control. Next, in the recording / playback unit 172, the recording processing circuit 166 causes the captured image signal (Y7,
C7) and the captured image information (S1) from the system control circuit 164 are subjected to signal processing necessary for recording using the memory circuit 167 and recorded in the recording medium 168. Also, the reproduction processing circuit 169 uses the memory circuit 167 to reproduce the reproduction image signal (Y) from the image data recorded on the recording medium 168.
8, C8) and reproduced image information (S2) are created. The picked-up image signal and picked-up image information, the reproduced image signal and the reproduced image information become a recording / reproducing unit output signal (Y9, C9, S3) through the selection circuit 170. Further, the image synthesizing unit 176 outputs the output signals (Y9, C9, S3) of the recording / reproducing unit 172.
The image information S3 is input to the image synthesis control circuit 175, and the image signals (Y9, C9) are output to the image synthesis processing circuit 173.
In step (1), the image is synthesized using the memory circuit 174 under the control of the image synthesis control circuit 175.

With such a configuration, in the digital signal processing circuit (6) in the image pickup section 165, as shown in the sixth embodiment, when the moving image is picked up, there is no aliasing signal at the output clock frequency rate. An image of a field unit is output, while an image of two systems (Y
1, C1) and (Y3, C3) are output for a total of four screens over a two-field period.

The image signals for four screens in total are output in the previous field (Y11, C11), (Y31, C).
31) and is output in the subsequent field (Y12, C1)
2) and (Y32, C32), the field memory control circuit 148, the selection circuit 162, and the output image control circuit 163 operate as follows, for example.

As a first operation example, first, as a picked-up image signal (Y7, C7) (Y
11 and C11) are output and (Y31, C31) is recorded in the field memory 147. Next, in the second field, as a captured image signal (Y7, C7) (Y
12 and C12) are output and (Y32, C32) is recorded in the field memory 147. After that, (Y31, C31) recorded in the field memory 147 is output as a picked-up image signal (Y7, C7) in the third field, and the picked-up image signal (Y7, C31) is output in the fourth field.
(7), (Y32, C32) recorded in the field memory 147 is output. At this time, the system control circuit outputs the spatial position information of the output image in each field as the captured image information (S1).

By this operation, the field memory circuit 147 in the image pickup section 165 has only to have a memory capacity for two field images, and the recording / reproducing section 172 records the image signal of one field screen in one field period. It is sufficient to sequentially perform the processing required for 4 field periods and record a total of 4 field images as a high quality still image on the recording medium. Further, in the image synthesizing unit 176, by inputting the reproduction signals (Y8, C8) of four fields and the reproduced image information (S2), which are images for high quality still images, from the recording medium 168, 4 shown in FIG. Screen composition is possible, and the selection circuit 170 causes the picked-up image signals (Y7, C
7) and also when (S1) is selected as the captured image information, the high-quality still image and the captured image information in the 4-field period from the image capturing unit with respect to the image signal of the 1-field screen in the 1-field period. The processing required for composition may be sequentially performed over a four-field period.

As a second operation example, the image synthesizing control circuit 175 works in conjunction with the system control circuit 164 or the recording / reproducing control circuit 171, so that the image synthesizing section 172 or the recording / reproducing section 172 synthesizes in the image synthesizing processing circuit 173. It is possible to obtain the photographed image signal (Y7, C7) or the reproduction signal (Y8, C8) required for the processing at the required timing.

By this operation, for example, when a high-resolution horizontal direction still image is created, (Y11, C11) and (Y12, C12) or (Y31, C31) and (Y
32, C32) for two field periods, and when a high resolution still image in the vertical direction is created, (Y11, C11) and (Y31, C31) or (Y12, C12) and (Y12, C12) are used. Y32, C32) may be combined for two field periods, and when a high-resolution still image in the horizontal and vertical directions is created, (Y11,
C11), (Y31, C31), (Y12, C12),
The four images of (Y32, C32) may be used and combined for four field periods. As described above, in the present embodiment, the horizontal pixel shift unit 102, the vertical pixel shift unit 132, and the digital signal processing circuit (6) 15 in the imaging unit.
7. By including the output image control circuit 163 and the like, it is possible to output an image necessary for synthesizing a high-quality still image at an appropriate timing, and record or record an image for high-quality still image in the recording / reproducing unit. It is possible to perform high-quality still image image composition in the image composition unit.

It should be noted that the image pickup apparatus with a plural image creation function in the seventh embodiment is higher than the image pickup apparatus with a plural image creation function in the sixth embodiment in conjunction with the recording / reproducing section and the image synthesizing section. Although the image quality still image can be synthesized with good operability, the same effect can be obtained by interlocking the recording / reproducing unit and the image synthesizing unit with respect to the image pickup apparatus with a plurality of image creating functions according to other embodiments. It is possible to get

Further, in the image pickup apparatus with a plural image forming function in the seventh embodiment, when the image for high-quality still image combination from the image pickup section is recorded on the recording medium by the recording / reproducing section and then reproduced. However, the present invention is not limited to this, and the same effect can be obtained by using a memory circuit used for recording processing or reproduction processing as a temporary storage memory for recording an image for high-quality still image composition to a required timing. It is possible.

Further, as the configuration example of the recording / reproducing section, the case where the same memory circuit is used for the recording process and the reproducing process has been described, but it is not limited to this, and it is clear that different memory circuits may be used. Is.

The case where the image synthesizing unit has an image synthesizing control circuit, an image synthesizing processing circuit, and a memory circuit has been described. However, the image synthesizing unit is not limited to this. It suffices to have it, and it is possible to obtain the same effect even with a general personal computer or the like. In other words, it is possible to configure a system in which the image synthesizing unit is not built in the imaging device but is separated.

In the above embodiment, the case where the output signal of the horizontal pixel shift processing circuit is one system of luminance signal (Y) and one system of color signal (C) (4: 2: 2 format) is shown. In the processing circuit, the case where both the luminance signal (Y) and the color signal (C) are divided into two in the horizontal direction has been shown, but the present invention is not limited to this, and for example, the difference in the resolution of the human eye for the luminance signal and the color signal. Therefore, it is conceivable that only a luminance signal is used to create a plurality of images for high-quality still image composition, and the color signals are used by replacing the signals of the same image.

As described in the above embodiment, the clock conversion processing circuit includes the interpolation processing circuit, the interpolation control circuit, and the RA.
By including the M and the RAM control circuit, the RA
When the W-CLK and the R-CLK of M have the same frequency, the clock frequency ratio becomes a magnification ratio of image expansion and compression processing, and functions as a zoom processing circuit. RAM W-CL
Even when K and R-CLK are different, it is possible to realize the clock conversion process and the zoom process at the same time by using the product of the actual clock frequency ratio and the desired zoom process ratio as the clock frequency ratio.

Further, the case of linear interpolation has been described as the interpolation processing, but the invention is not limited to this, and secondary interpolation or interpolation by convolutional integration may be used.

Further, in the above embodiment, the clock conversion processing circuit is composed of the interpolation processing circuit, the interpolation control circuit, the RAM and the RA.
Although the configuration including the M control circuit is shown, the configuration is not limited to this. For example, when the clock conversion ratio is 2: 1, the configuration may be such that the odd-numbered signal or the even-numbered signal of the input image is simply thinned and sampled. That is clear.

Further, in the above embodiment, as an example of means for inputting a signal having a sampling frequency different from the sampling frequency of the output signal, a horizontal pixel shift unit in the horizontal direction, which is means for inputting a signal having a double density of the output signal. The case of the + horizontal pixel shift processing is described in the vertical direction as the vertical pixel shift section + the vertical pixel shift processing, but the present invention is not limited to this. For example, XGA (horizontal 1024 × vertical 7
68) image is a VGA image (horizontal 640 × vertical 480)
System and progressive images (vertical 4
80 lines) interlaced image (240 vertical lines)
It is possible to obtain the same effect in a system that outputs as.

[0159]

As described above, the present invention is provided with the horizontal pixel shift unit and the clock conversion circuit, and with this configuration , two samples at the same time sampled at different spatial phases in the horizontal direction are provided.
By creating an image of a field component, it is possible to synthesize a high-quality still image from the 2 field images.

Further, the present invention comprises a horizontal pixel shift section, a vertical pixel shift section, and a clock conversion circuit, and with this configuration, images of four fields at the same time sampled at different spatial phases in the horizontal and vertical directions are obtained. By creating it, it is possible to synthesize a high-quality still image from the four-field image.

Also, at least means for obtaining a high-density video signal in either the horizontal direction or the vertical direction, a filter circuit for limiting the frequency band of this high-density video signal, and the filter circuit input signal and output signal are selected. Selection circuit, a clock conversion processing circuit that performs clock conversion on the output signal of the selection circuit, and a clock conversion control circuit that controls the selection circuit and the clock conversion processing circuit. In the mode, the selection circuit selects the filter circuit output signal, the clock conversion processing circuit obtains a single image, and when the clock conversion control circuit is in the still image mode, the selection circuit selects the filter circuit input signal to perform the clock conversion processing. By creating multiple images with different circuits, high-quality moving images with no aliasing components in the movie mode Obtained, the still picture mode it is possible to synthesize a high-quality still image from multiple images.

Further, the present invention is provided with a horizontal pixel shift section, a vertical pixel shift section, a clock conversion circuit and an output image control circuit, and with this configuration, a maximum of four fields sampled at different spatial phases in the horizontal and vertical directions. By creating an image and outputting it at a timing suitable for recording and composition, a high-quality still image can be combined with good operability.

[Brief description of drawings]

FIG. 1 is a block diagram of an image pickup apparatus with a multiple image generation function according to a basic embodiment of the present invention.

FIG. 2 is a block diagram showing a first basic configuration example of an image pickup apparatus with a multiple image creation function according to a basic embodiment of the present invention.

FIG. 3 is a block diagram showing a second basic configuration example of an image pickup apparatus with a multiple image creation function according to a basic embodiment of the present invention.

FIG. 4 is a block diagram of an image pickup apparatus with a multiple image creation function according to the first embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating an operation of horizontal pixel shifting of the image sensor section according to the same embodiment.

FIG. 6 is a schematic diagram illustrating an operation of a horizontal pixel shift processing circuit according to the same embodiment.

FIG. 7 is a clock conversion processing circuit in the same embodiment.
FIG. 3 is a block diagram showing a configuration example of (1).

FIG. 8 is a block diagram showing a configuration example of a basic interpolation processing circuit in the clock conversion processing circuit (1).

FIG. 9 is a schematic diagram illustrating a basic operation of an interpolation processing circuit.

FIG. 10 is a block diagram showing a basic configuration example of an interpolation processing circuit in the same embodiment.

FIG. 11 is a schematic diagram illustrating an operation of interpolation processing in the basic configuration example.

FIG. 12 is a schematic diagram illustrating an example of interpolation coefficient control of interpolation processing in the basic configuration example.

FIG. 13 is a block diagram showing a configuration example of an interpolation coefficient control circuit in the same embodiment.

FIG. 14 is a diagram showing a clock conversion processing circuit according to the same embodiment.
It is a 2nd block diagram which shows one structural example of (1).

FIG. 15 is a block diagram showing a configuration example of a clock conversion processing circuit (1) when the clock conversion ratio is 2: 1 in the embodiment.

FIG. 16 is a relationship diagram showing a spatial position of an output signal in the configuration example of the clock conversion processing circuit (1) when the clock conversion ratio is 2: 1.

FIG. 17 is a processing circuit in the clock conversion processing circuit (1)
It is an operation schematic diagram of (a).

FIG. 18: Processing circuit in clock conversion processing circuit (1)
It is an operation schematic diagram of (b).

FIG. 19 is a block diagram showing a configuration example having a one-system output function in the same embodiment.

FIG. 20 is a block diagram of an image pickup apparatus with a multiple image creation function according to a second embodiment of the present invention.

FIG. 21 is a diagram showing a clock conversion processing circuit according to the embodiment.
It is a 2nd block diagram which shows the structural example of (2).

FIG. 22 is a block diagram of an image pickup apparatus with a multiple image creation function according to a third embodiment of the present invention.

FIG. 23 is a diagram showing a clock conversion processing circuit according to the embodiment.
It is a block diagram showing a configuration example of (3).

FIG. 24 is a relationship diagram showing a spatial position of an output signal in the configuration example of the clock conversion processing circuit (3).

FIG. 25 is a block diagram showing a configuration example having a one-system output function in the same embodiment.

FIG. 26 is a block diagram of an image pickup apparatus with a multiple image creation function according to a fourth embodiment of the present invention.

FIG. 27 is a diagram showing a clock conversion processing circuit according to the same embodiment.
It is a block diagram showing a configuration example of (4).

FIG. 28 is a block diagram of an image pickup apparatus with a multiple image creation function according to a fifth embodiment of the present invention.

FIG. 29 is a block diagram of an image pickup apparatus with a multiple image creation function according to a sixth embodiment of the present invention.

[Fig. 30] Fig. 30 is a block diagram of an image pickup apparatus with a multiple image generation function according to a second basic embodiment of the present invention.

FIG. 31 is a block diagram of an image pickup apparatus with a multiple image creation function according to a seventh embodiment of the present invention.

FIG. 32 is a block diagram of an image pickup apparatus such as a video camera including a conventional still image creation function circuit.

FIG. 33 is a block diagram of a conventional image pickup apparatus using a pseudo frame signal.

[Fig. 34] Fig. 34 is a schematic diagram illustrating an operation of shifting vertical pixels of an image pickup element unit in an image pickup apparatus using a conventional pseudo frame signal.

[Explanation of symbols]

101 Image sensor unit 102 Horizontal pixel shift unit 103 image sensor drive circuit 104 drive control circuit 105 Analog signal processing circuit 106 analog-digital conversion circuit 107 Digital signal processing circuit (1) 108 Horizontal pixel shift processing circuit 109 Clock conversion processing circuit (1) 110 Clock conversion control circuit 111 encoder (a) 112 encoder (b) 113 System control circuit 201 High-density video signal generation means 202 image segmentation means 203 image output means 204 image composition information creation means 205 image composition means

Continuation of the front page (56) Reference JP-A-8-172636 (JP, A) JP-A-3-93377 (JP, A) JP-A-62-269488 (JP, A) JP-A-6-319144 (JP , A) JP-A-9-163388 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 9/09

Claims (6)

(57) [Claims] 1. Three different color signals C1, C2 and C3 are provided.
Means for obtaining the color signal C2 and the color signal C1
And C3 in the horizontal direction are shifted by a fixed pitch hp.
And a horizontal phase shifter for setting the color signal C1 in the horizontal direction.
Smell horizontally from the phase-shifted color signals C2 and C3
Water to obtain a signal of double density of the color signals C1, C2, C3
Flat pixel shift processing circuit and horizontal pixel shift processing circuit
A clock that converts the output signal at a ratio of 2: 1.
Clock conversion processing circuit and the clock conversion processing circuit
2 images for each pixel of double density signal in the horizontal direction
An image pickup system comprising a clock conversion control circuit for obtaining . 2. Three different color signals C1, C2 and C3
Means for obtaining the color signal C2 and the color signal C1
And C3 in the horizontal direction are shifted by a fixed pitch hp.
And a horizontal phase shifter for controlling the color signal C1.
The vertical phase of the color signal C2 is shifted by a constant pitch vp.
And a vertical phase shifter that controls the horizontal phase of the color signal C1.
And the color signals C2 and C3 that are vertically phase-shifted.
Positional relationship between the two field signals that make up the frame signal
And a frame processing circuit for obtaining a pseudo frame signal in
The color signal C in the horizontal direction from the pseudo frame signal
Horizontal pixel shift processing to obtain double density signal with density of 1, C2, C3
A logic circuit, and the horizontal pixel shift processing in the vertical direction and
2: 1 ratio clock for double density signal in horizontal direction
Clock conversion processing circuit for performing conversion, and the clock conversion
One image of double-density signal from the processing circuit in the horizontal direction
An image pickup system comprising a clock conversion control circuit for obtaining an image of each element. 3. Three different color signals C1, C2 and C3
The means for obtaining it must consist of multiple solid-state image sensors.
The imaging system according to any one of claims 1 to 2, wherein: 4. The plurality of solid-state image pickup devices output a color signal C1.
A first solid-state image sensor for obtaining a color signal C2 and a second solid-state image sensor for obtaining a color signal C2.
A body imaging device and a third solid-state imaging device for obtaining a color signal C3
The imaging system according to claim 3, comprising: 5. Three different color signals C1, C2, C3 are provided.
2. One color signal R, G, B.
The imaging system according to any one of 1 to 4 . 6. Three different color signals C1, C2, C3
One color signal R, G, B, and C1 = G
The imaging system according to any one of claims 1 to 4, which is a characteristic .