JP3106759B2 - Imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus for a next-generation television system, and more particularly to an image pickup apparatus of a progressive scanning system.

[0002]

2. Description of the Related Art In recent years, widening of screens has been promoted, as in television systems such as HDTV (1125 scanning lines) and second-generation EDTV (525 (625 scanning lines)). Further, in order to pursue higher image quality in the vertical direction, a progressive scanning type imaging device is desired. As described above, the aspect ratio is changed from 4: 3 to 16: 9 in the related art, and a progressive scanning imaging apparatus handles a signal having a wider band than the related art. Therefore, not only an image sensor and a display but also a signal processing circuit requires a dedicated circuit different from a video signal processing device of a standard television system. In particular, recently, digitalization of video signal processing circuits has progressed, and most of these circuits have been implemented as LSIs. When the screen is widened and sequentially scanned, the clock frequency of a circuit for performing digital processing of a video signal increases, so that an arithmetic circuit such as a multiplier, an adder, and a memory must be speeded up. Therefore, in order to digitally process a video signal in a video signal processing device in which a screen is widened and sequentially scanned, it is necessary to develop a dedicated digital processing circuit or LSI in consideration of the speed of an arithmetic circuit. There was a problem that cost became large.

In view of the above problems, when constructing a video signal processing device compatible with a television system with a wide screen, the circuit and the LSI of a conventional video signal processing device for a standard television are developed. In recent years, techniques for reducing costs and providing an inexpensive wide-screen video signal processing device have been proposed.

FIG. 11 is a block diagram showing one of the typical techniques, showing a configuration of a signal processing circuit in an image pickup apparatus supporting a wide screen. The main features of this method are
By dividing a wide screen into odd and even pixels and performing processing in parallel, a signal of a high-speed sequential scanning system is reduced in speed, thereby effectively utilizing a conventional signal processing circuit such as an LSI. In FIG. 11, reference numeral 33 denotes an input terminal to which an optical image passed through a lens or the like is input; An analog process circuit to be applied, 36 is an AD converter for converting an output signal of the analog process circuit 35 into a digital signal, and 37 is an AD converter.
The fck clock rate output signal of converter 36 is represented by fe, f
o, a dividing circuit for converting the signal into a clock rate signal, 38, 3
Reference numeral 9 denotes a digital signal processing LSI for performing gamma correction, matrix processing, and the like on each output signal of the division circuit 37;
Is a synthesizing circuit for synthesizing two digital signal processing LSI output signals of fe and fo clock rates into a fck clock rate signal, 41 is a DA converter for converting an output signal of the synthesizing circuit 40 into an analog signal, and 42 is fck, fe, A clock generating circuit for generating a clock pulse of fo, 43 is an output terminal.

Hereinafter, a conventional wide-screen imaging device (sequential scanning) will be described with reference to FIGS.

In FIG. 11, an optical image input from an input terminal 33 is formed on an image sensor 34 corresponding to a wide screen.
It is output as an electric signal by a predetermined vertical and horizontal read pulse drive (not shown). At this time, the horizontal read clock is faster than the read clock of the image sensor of the current television system (aspect ratio 4: 3). For example, the read of the image sensor of the current television system is 14.3 MHz (4 fsc; When fsc is the color subcarrier frequency), the read clock of the wide-screen image sensor having the same resolution as this image sensor is approximately 19 MHz due to the aspect ratio of 16: 9. Further, when the scanning is performed sequentially, the frequency becomes about 38 MHz (this clock frequency is fck).

The wide-band imaging signal read out by the high-speed clock fck is converted by the analog process circuit 35 into
Black level adjustment based on a black balance or the like, white level adjustment based on a white balance or the like, and further, a knee processing are performed. After that, this analog signal is subjected to a subsequent A to perform digital processing which is excellent in accuracy, control and characteristics.
It is converted into a digital signal by the D converter 36. This A
The D conversion is performed by a high-speed clock fck.
The output signal of the AD converter 36 is input to the dividing circuit 37. The dividing circuit 37 divides the signal into a signal at the fe rate and a signal at the fo rate using the low-speed clocks fe and fo output from the clock generating circuit 42 and outputs the divided signals. In the case of this conventional example, the clocks of fck, fe, and fo are generated by a phase obtained by dividing the frequency of fck by フ リ ッ プ フ ロ ッ by the flip-flop 44, as shown in an example of the internal configuration of the clock generation circuit 42 in FIG. Clocks that differ by 180 ° are fe and fo. In other words, the frequency is about 19 MHz
Are divided into two signals. Therefore, the processing speed is sufficiently compatible with circuits, LSIs, and the like having a signal processing speed of the conventional television system. For the division operation, for example, two systems of delay flip-flops are prepared, and
This can be easily performed by holding data with clocks e and fo.

The two divided signals are input to a digital signal processing LSIa 38 and a digital signal processing LSIb 39, respectively, and subjected to various digital processings such as gamma correction, blanking processing, and matrix processing. Digital signal processing LSIa38 and digital signal processing LSI
The operation of b39 is exactly the same, and the processing phase is 180 °
Only different. Here, as described above, the clock is about 19 MHz, which can sufficiently cope with the processing speed of the conventional television system, so that there is no problem in its operation. The output signals of the digital signal processing LSIa 38 and the digital signal processing LSIb 39 are synthesized into a signal of the fck rate by a synthesizing circuit 40 including a multiplexer and the like. The digital signal synthesized by the synthesizing circuit 40 is converted into an analog signal by the DA converter 41, and the original wideband wide screen signal is obtained from the output terminal 43.

[0009]

However, in the conventional imaging apparatus for wide screens having the above-described configuration, the imaging apparatus is divided into two systems of odd-numbered pixels and even-numbered pixels, and a wide-screen imaging signal of a progressive scanning system (high-speed imaging signal). Even if an LSI or a signal processing circuit corresponding to the current system can be shared by reducing the speed of the imaging signal), the signal is divided into a signal sequence of odd-numbered and even-numbered pixels. There is a problem in that only data for each pixel can be obtained, and accurate filtering processing cannot be performed.

As another method, the screen is divided into regions (for example, divided into two parts, left and right, or divided into the center and both sides), and each system in the divided regions is time-expanded to perform low-speed processing.
In some cases, a wide-screen-capable imaging device that combines the original screen after processing is obtained. In this case, there is no problem in the horizontal filtering process or the like. However, a circuit or an LSI that performs various controls of the imaging apparatus by extracting the average value, the peak value, and the like of the entire image from the image data of the video signal by digital processing. When using the image data, it is difficult to use the image data of the divided video signal, and a high-speed circuit or an LSI for separately detecting an average value, a peak value, and the like of the image data is used.
However, there is a problem that the circuit scale and the development cost increase.

[0011] In view of the above, the present invention provides an image pickup apparatus compatible with a television system having a wide screen,
Horizontal filtering processing can be performed accurately, and furthermore, development costs are reduced by sharing the signal processing circuit and LSI of the conventional imaging device for standard televisions without increasing the circuit scale, and the imaging device for an inexpensive wide-screen imaging device is used. It is intended to provide. It is another object of the present invention to provide a signal processing configuration capable of obtaining a vertical aperture signal suitable for an image pickup signal of a progressive scanning system by using a signal processing circuit or an LSI of an image pickup device for a standard television.

[0012]

In order to achieve this object, an image pickup apparatus according to the present invention comprises: an A / D converter for performing A / D conversion of an image signal corresponding to sequential scanning or sequential scanning;
The image pickup signal AD-converted by the converter is converted into an odd-numbered line (1, 3, 5,..., The scanning line) for each horizontal scanning line and an even-numbered line (2, 4, 6,. A line dividing circuit that divides the signal line into two signal lines of a scanning line), two time extending circuits that respectively time extend the two output signals output from the line dividing circuit, and the two time extending circuits Apply signal processing such as gamma correction and aperture correction to the output signal of the circuit 2
System digital signal processing circuit group, two time compression circuits for time-compressing output signals of the two system digital signal processing circuit groups to original time lengths, respectively, and output from the two time compression circuits. And a line synthesizing circuit for serializing image signals of odd lines and even lines and synthesizing the signals into an original sequential scanning image signal.

Also, in the image pickup apparatus of the present invention, the two time expansion circuits are each composed of an odd line (1, 3, 5,..., A scanning line) and an even line (2, 4, 6,. (Scanning line) image signal is time-extended so as to correspond to one horizontal scanning time of the interlaced scanning system from one horizontal scanning time of the sequential scanning system, and the output signals of the odd-numbered lines and even-numbered lines that are time-expanded are interlaced. The two time compression circuits are controlled to be output at the same timing in synchronization with the horizontal scanning of the scanning system, and the two time compression circuits are expanded at a time corresponding to one horizontal scanning time of the interlaced scanning system input at the same timing. This is an imaging device that compresses signals of each odd-numbered line and even-numbered line into one horizontal scanning time of a sequential scanning system.

In the image pickup apparatus of the present invention, a high-pass filter circuit for generating a vertical aperture signal in each of the two digital signal processing circuit groups corresponding to the image signal lines of the odd lines and the even lines is provided. , The original signal of the luminance signal or a signal similar to the luminance signal, 1H
(1 horizontal scanning time) delay signal, 2H (2 horizontal scanning times)
A selection circuit for selecting any two of the three delay signals; an addition circuit for adding the selected two signals; and an odd line system for the odd line system. An operation circuit for performing an operation based on three signals of an output signal, the 1H delay signal, and an output signal of the addition circuit of an even-numbered line; similarly, an output of the addition circuit of an even-numbered line is included in the even-numbered line. An image pickup apparatus including an arithmetic circuit that performs an arithmetic operation based on three signals of a signal, the 1H delay signal, and an output signal of the addition circuit in an odd line system.

In the image pickup apparatus of the present invention, a high-pass filter circuit for generating a vertical aperture signal in each of the two digital signal processing circuit groups corresponding to the image signal lines for the odd lines and the even lines is provided. , The original signal of the luminance signal or a signal similar to the luminance signal, 1H
(1 horizontal scanning time) delay signal, 2H (2 horizontal scanning times)
First to select any two of the three delayed signals
Selection circuit, an addition circuit for adding the selected two signals, and a second selection circuit for switching and selecting the output signal of the addition circuit of its own system and the output signal of the addition circuit of another system. And an arithmetic circuit for calculating the output signal of the second selection circuit and the 1H delay signal.

[0016]

According to the present invention, the sequential scanning or an image signal corresponding to the sequential scanning is AD-converted into a digital signal by the above-described configuration, and a signal sequence of an odd-numbered line and an even-numbered line are provided for each horizontal scanning line by a line dividing circuit. The signal sequence is divided into two signal sequences. The divided signal sequences of the two systems are slowed down by time expansion by a time expansion circuit, and are processed in parallel by a digital signal processing circuit group corresponding to each system. The signals subjected to the parallel processing are compressed by the time compression circuit in the time of the original sequential scanning system, and the original sequential scanning or an image signal corresponding to the sequential scanning is obtained by being serialized by the line synthesizing circuit.

Further, according to the present invention, in a group of digital signal processing circuits corresponding to two parallel signal lines of odd-numbered lines and even-numbered lines, a high-pass filter circuit for generating a vertical aperture signal in each of the systems has a luminance. A selection circuit for selecting any two of three signals: an original signal of a signal or a signal similar to a luminance signal, a 1H (one horizontal scanning time) delay signal, and a 2H (two horizontal scanning time) delay signal; And an adder circuit for adding the two signals, the output signal of each of the adder circuits is also output to another system, and the arithmetic circuit of each system adds the 1H delay signal of its own system to the adder circuit. The output signal of the circuit,
The operation is performed from three signals of the output signal of the addition circuit input from another system, and a vertical aperture signal suitable for sequential scanning is obtained.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an image pickup apparatus according to the first embodiment of the present invention. In FIG. 1, 1
An A / D converter for converting an image pickup signal corresponding to a sequential scan or a sequential scan into a digital signal, a line dividing circuit for dividing an output signal of the AD converter 1 into two signal lines of an odd line and an even line, , 4 are time expansion circuits for time-expanding the signals of the odd-line and even-line signal sequences, respectively, and 5 and 6 are digital signal processing for performing digital signal processing such as gamma correction and aperture correction on the time-expanded signals of each system. A group of circuits, 7 and 8, a time compression circuit for compressing the signals of the respective systems subjected to digital signal processing to the original time, and 9 a signal of the sequential scanning system based on the time-compressed signals of the respective systems. This is a line combining circuit for combining.

The operation of the first embodiment of the present invention will be described below with reference to FIGS. FIGS. 2A and 2B are a block diagram and a timing chart showing an example of the internal configuration of the line dividing circuit 2, and FIGS. 3A and 3B are diagrams showing the internal configuration of the time extending circuits 3 and 4. 4 (a) and 4 (b) are a block diagram and an example of an internal configuration of the time compression circuits 7 and 8, and FIGS. 4 (a) and 4 (b) are timing charts thereof. 3B is a block diagram showing an example of the internal configuration of the line synthesizing circuit 9 and a timing chart thereof.

In FIG. 1, a progressive scan image signal output from an image sensor (aspect ratio 16: 9) corresponding to a wide screen (not shown) is subjected to AD processing at a subsequent stage in order to perform digital processing excellent in accuracy, control and characteristics. It is converted into a digital signal by the converter 1. The progressive scanning image signal converted into a digital signal is divided by the line dividing circuit 2 into two systems of a signal sequence of an odd line and a signal sequence of an even line.

This operation will be described with reference to FIGS. 2 (a) and 2 (b). As shown in FIG. 2A, the line dividing circuit 2 is composed of two simple delay flip circuits 10 and 11 for outputting odd lines and even lines, a frequency dividing circuit 12 and an inverter 13. In the frequency dividing circuit 12, FIG.
As shown in the timing chart, the horizontal synchronizing signal (HD) of the sequential scanning system is frequency-divided to obtain a frequency-divided pulse. The frequency-divided pulse is directly input to the output enable terminal (EN) of the delay flip circuit 10 and further input to the output enable terminal (EN) of the delay flip circuit 11 via the inverter 13. Therefore, the delay flip circuit 1
Odd line output of 0, delay flip circuit 11
As shown in the timing chart of FIG. 2B, the output of the even line is used for each horizontal scanning line, and is divided into an odd line and an even line.

The signals divided into odd-numbered lines and even-numbered lines are input to time expansion circuits 3 and 4, respectively. here,
The time of each signal is extended from one horizontal scanning time of the sequential scanning system to a time at which low-speed processing is possible.

The decompression operation will be described with reference to FIGS. As shown in FIG. 3A, the time expansion circuits 3 and 4 include a memory A14, a memory B15, and a switch SW.
1 and SW2. In the case of the present embodiment, as shown in the timing chart of FIG. 7B, the time extension is to extend one horizontal scanning time (1H) of the sequential scanning to twice the time, that is, one horizontal scanning time of the interlaced scanning system. doing. The operation of writing and reading of the memory is performed by the time expansion circuit 3 corresponding to the signal sequence of the odd line by the memory A1.
4, the memory B is read out during the 2H period in the line in which the first odd line is written for 1H, and SW1 and SW2 are switched in the next odd line to switch the memory A14,
The reverse operation is performed in the memory B15. Similarly, the time expansion circuit 4 corresponding to the signal sequence of the even-numbered line also performs writing in the 1H period and reading in the 2H period in the memory A14,
It is performed alternately in the memory B15.

The signals of the odd-numbered line signal sequence and the even-numbered line signal sequence that have been time-expanded are input to digital signal processing circuit groups 5 and 6, respectively.
For example, gamma correction, color correction, horizontal and vertical aperture correction, matrix processing, and the like are performed. Since the signal of the signal line of the odd line and the signal of the signal line of the even line are time-expanded as described above, the processing speed may be half the speed of the sequential scanning, that is, the speed of the interlaced scanning system may be sufficient. Circuits and LSIs used in a television-type imaging device can be shared.

The output signals of the digital signal processing circuit groups 5 and 6 are input to the time compression circuits 7 and 8, respectively, and the operation is reverse to that of the time expansion circuits 3 and 4 to change the time of the interlace scanning system to the time of the sequential scanning system. Will be returned.

This operation will be described with reference to FIGS. As shown in FIG. 4A, the time compression circuits 7, 8
Also memory A16 and memory B17 and switches SW1 and S
W2. As shown in the timing chart of FIG. 11B, both the time compression circuits 7 and 8 read and write the memory A16 and the memory B17 alternately, write the input signal expanded in the 2H period in the 2H period, and write in the 1H period. read out. The read timing is read by the compression circuits 7 and 8 so as to correspond to the odd-numbered line and the even-numbered line, respectively.

The odd-numbered line and even-numbered line signals returned to the sequential scanning system signals by the time expansion circuits 7 and 8 are alternately selected by the line synthesizing circuit 9 and are synthesized and output as the sequential scanning system signals.

As shown in FIG. 5A, the line synthesizing circuit 9 is composed of, for example, a multiplexer 18, and switches the signals of the odd-numbered lines and the even-numbered lines by a frequency-divided pulse of the horizontal synchronizing signal and outputs the signals. By this operation, the sequential signal is restored as shown in the timing chart of FIG.

As described above, according to the first embodiment of the present invention, in order to divide an image signal of a wide screen and a progressive scan into two signal sequences of a signal sequence of an odd line and a signal sequence of an even line, The processing speed is halved, the processing speed of the interlaced scanning system is sufficient, and the circuits and LSIs used for signal processing of the conventional standard system can be used. Can be processed without any problems. Further, even when a circuit for extracting an average value, a peak, and the like of the entire screen by digital processing based on image data of an imaging signal or an LSI is used, even if such a circuit or LSI is not separately provided, a signal sequence of an odd-numbered line or By using the data of either one of the signal lines of the even-numbered lines, data having almost the same accuracy as the data of the conventional interlace scanning system can be detected.

In this embodiment, the line dividing circuit 2
And the line synthesizing circuit 9 is provided, but it goes without saying that the respective functions may be handled by switching the switches of the time expansion circuits 3 and 4 and the time compression circuits 7 and 8.

The method of dividing the lines is not to divide the two lines of odd lines and even lines, but to divide each line into an appropriate number of lines so that the line has an appropriate processing speed according to the processing speed of the digital signal processing circuit group. Needless to say, it can be divided.

Next, an image pickup apparatus according to a second embodiment of the present invention will be described. FIG. 6 is a block diagram showing the configuration of the second embodiment of the present invention. In FIG. 6, reference numeral 1 denotes an AD converter for converting a sequential scan or an image signal corresponding to the sequential scan into a digital signal, and 2 divides an output signal of the AD converter 1 into two signal lines of an odd line and an even line. Line dividing circuits 3 and 4 are time extending circuits for time extending the signals of the odd-line and even-line signal sequences, respectively.
Reference numeral 20 denotes a digital signal processing circuit group for performing digital signal processing such as gamma correction and aperture correction on the time-expanded signals of the respective systems, and reference numerals 7 and 8 denote the signals of the respective systems subjected to the digital signal processing at the original time. A time compression circuit 9 for compression is a line synthesis circuit for synthesizing the original signals of the sequential scanning system from the time-compressed signals of the respective systems.

The present embodiment differs from the first embodiment in that the digital signal processing circuit group 19 and the digital signal processing circuit group 20 exchange signals with each other.
The other circuits are completely the same, and therefore have the same operation and function, and the description of the operation is omitted. Hereinafter, signals exchanged with each other and their operations will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 7 is a block diagram of a conventional vertical aperture circuit for explaining the second embodiment, and an explanatory diagram of signal processing operation thereof. FIG. 8 is a timing chart for explaining the second embodiment. FIG. 9 is a block diagram showing the configuration of a vertical aperture circuit in the digital signal processing circuit groups 19 and 20 of the second embodiment, and FIG. 10 is a block diagram showing the configuration of the digital signal processing circuit groups 19 and 20 in the second embodiment. FIG. 14 is a block diagram illustrating another configuration of the vertical aperture circuit.

A conventional circuit for generating a vertical aperture signal is as follows.
For example, a digital signal processing circuit or LSI has a circuit configuration as shown in FIG. In FIG. 7, reference numerals 21 and 22 denote 1H delay circuits for giving a delay time of one horizontal scanning period, 23 denotes a multiplier having a circled number as a multiplier, 24 denotes an adder, and 25 denotes a subtractor.

In the configuration shown in FIG. 7A, a high-pass filter operation for subtracting the signal obtained by adding the original signal and the 2HD signal from the double 1HD signal is performed to obtain a vertical aperture signal (input signal). Is a luminance signal.) Therefore, the signal waveform is as shown in FIG. 3B, and the 1HD signal is subjected to vertical aperture correction by the obtained vertical aperture signal. Therefore, when the digital signal processing circuit group having the vertical aperture circuit having the configuration shown in FIG. 7 is used in a system of odd-numbered lines and even-numbered lines, for example, as shown in FIG. The calculation of 1, 3, and 5 lines shown in A) results in 4
In the system of the even-numbered lines corresponding to the line, the calculation of the 2, 4, and 6 lines shown in (B) is performed. Therefore, the boost frequency is the same as the boost frequency (52
5/2 TV). This means that the boost frequency does not change even if line synthesis is performed and the signal is returned to a progressive scan signal. In order to obtain the vertical aperture signal in the case of the original sequential scanning, the operation between the lines 2, 3, and 4 as shown by the dotted line is performed for the odd line 3 as shown in FIG. Must be calculated between the solid lines 3, 4 and 5. The signals exchanged between the digital signal processing circuit groups 19 and 20 are signals necessary to generate a vertical aperture signal in this sequential scanning.

Therefore, in the second embodiment of the present invention, the vertical aperture circuit is configured as shown in FIG. With this configuration, a vertical aperture signal for the original sequential scanning is obtained.

In FIG. 9, 21 and 22 are 1H delay circuits for giving a delay time of one horizontal scanning period, 23 is a multiplier having a multiplier in the circle, 24 is an adder, 25 is a subtractor, and 26 and 2
7 is a three-input one-output multiplexer, and 28 is a two-input one-output multiplexer.

Here, the multiplexers 26 and 27 are similar circuits, and the inputs are the same original signal and 1H delay signal (1
HD) and 2H delay signal (2HD) are input, and the manner of selection is separately controlled.

Now, assuming that the original signals of the odd and even lines are the fifth and sixth lines, respectively, the 1H delay signal of the odd line is the third line. The signal of the line itself and the added signal of the second and fourth lines of the even lines are necessary for the calculation. Therefore, as an output from the system of the even-numbered lines to the system of the odd-numbered lines, an addition signal of two lines of the 1H delay signal (the fourth line) and the 2H delay signal (the second line) is output. Similarly, the 1H delay signal of the even line becomes the fourth line, and from this fourth line, the original signal of the odd line (the fifth line) and the 1H delay signal (the third line) are changed from the odd line system to the even line system. ) Is output.

The multiplexers 26 and 27 of the two systems of the odd line and the even line are controlled so that the above-mentioned signals are selected and added.

In this manner, a vertical aperture signal corresponding to the sequential scanning is obtained in the system of each odd-numbered line and even-numbered line. In this embodiment, the multiplexer 28 is further provided.
Thus, it is possible to switch between a two-line addition signal output from the own system to another system and a two-line addition signal input from another system. To obtain a vertical aperture signal for progressive scanning, as described above, In order to select the two-line addition signal input from the system and obtain the vertical aperture signal of the interlaced scanning system, the two-line addition signal of the own system is selected and the multiplexer 26,
27 controls to select the original signal and the 2H delay signal.

If the configuration of the vertical aperture circuit is as shown in FIG. 9, it is possible to obtain a conventional vertical aperture signal even if this circuit is used alone for interlaced scanning signal input. It is possible to obtain a vertical aperture signal for sequential scanning at the processing speed of the interlaced scanning system as in the case where the signal is divided into two signals of odd and even lines as in this embodiment.

FIG. 10 shows a further application of the circuit configuration of FIG. In FIG. 10, reference numerals 21 and 22 denote 1H delay circuits for giving a delay time of one horizontal scanning period;
Is an adder, 25 is a subtractor, 26 and 27 are 3-input and 1-output multiplexers, 29, 30, and 31 are multipliers for multiplying the in-circle coefficients, and 32 is an adder.

In FIG. 10, multipliers 29, 30, 31
By appropriately setting the coefficients k1, k2, and k3 of
It is possible to make the circuit exactly the same as that of FIG. For example, if k1 = 2, k2 = 0, and k3 = −1, this is the same as the case where the selection of the multiplexer 28 in FIG. 9 is set to the I1 input. Conversely, if k1 = 2, k2 = −1, and k3 = 0, This is the same as when I0 is input. Also, k1, k
If the values of k2 and k3 are set more appropriately, the signal of the sequential scanning is finally calculated by five lines (for example, the signal of the third line with respect to the third line in FIG. Signal can be calculated), and a vertical aperture signal having various high-pass filter characteristics can be obtained.

As described above, according to the present embodiment, by adopting the circuit configuration shown in FIG. 9 or FIG. A vertical aperture signal can be obtained, and even when a signal input for progressive scanning is divided into, for example, a signal system of odd-numbered and even-numbered lines, the original vertical aperture signal of progressive scanning can be obtained. Further, it is also possible to obtain vertical aperture signals having various characteristics.

[0048]

As described above, according to the present invention, a horizontal filtering process is carried out by dividing a line into an image pickup apparatus compatible with a television system in which the screen is widened and sequentially scanned. The processing can be performed without any problem and the processing speed can be reduced. The signal processing circuit and LSI (digital signal processing LSI and data detection LSI) of the image pickup device for the conventional standard television can be shared. In addition, it is possible to provide an imaging device that can reduce the development cost and is inexpensive for wide screens (sequential scanning).

Further, even when the line is divided, a vertical aperture signal corresponding to the original sequential scanning can be obtained, and vertical aperture signals having various high-pass filter characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an imaging apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an example of an internal configuration of a line dividing circuit 2 according to the first embodiment and a timing chart thereof;

FIG. 3 is a block diagram showing an example of an internal configuration of time expansion circuits 3 and 4 in the first embodiment and a timing chart thereof.

FIG. 4 is a block diagram showing an example of the internal configuration of the time compression circuits 7 and 8 in the first embodiment, and a timing chart thereof.

FIG. 5 is a block diagram showing an example of an internal configuration of a line synthesizing circuit 9 in the first embodiment and a timing chart thereof.

FIG. 6 is a block diagram illustrating a configuration of an imaging apparatus according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a vertical aperture circuit of a conventional image pickup apparatus for explaining the second embodiment, and an explanatory diagram of signal processing operation thereof;

FIG. 8 is a timing chart for explaining the second embodiment.

FIG. 9 is a block diagram showing a configuration of a vertical aperture creating circuit in the digital signal processing circuit group according to the second embodiment;

FIG. 10 is a block diagram showing another configuration of the vertical aperture creating circuit in the digital signal processing circuit group according to the second embodiment;

FIG. 11 is a block diagram illustrating a configuration of a signal processing circuit of a conventional imaging device (supporting a wide screen).

FIG. 12 is a block diagram showing an example of an internal configuration of a clock generation circuit 42 in the conventional example and a timing chart thereof.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D converter 2 Line division circuit 3, 4 Time expansion circuit 5, 6, 19, 20 Digital signal processing circuit group 7, 8 Time compression circuit 9 Line synthesis circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N ^5/ 14-5/253 H04N 5/335 H04N ^7/ 00-7/015

Claims (4)

(57) [Claims] An A / D converter for performing AD conversion of a progressive scan or an image signal corresponding to the progressive scan, and an odd-numbered line (1, 3, 5) for each horizontal scan line. ,... The scanning line) and the even lines (2, 4, 6,.
.. A second scanning line), a line dividing circuit for dividing the signal sequence into two signal sequences, two time extending circuits for respectively time extending the two output signals output from the line dividing circuit, Two systems of digital signal processing circuits for performing signal processing such as gamma correction and aperture correction on the output signals of the two time expansion circuits, respectively; Two time compression circuits for performing time compression, and a line synthesis circuit for sequentially converting the image signals of the odd lines and the even lines output from the two time compression circuits into the original image signal of the sequential scanning system. An imaging device, comprising: 2. The two time expansion circuits generate image signals of odd lines (1, 3, 5,..., The scanning lines) and even lines (2, 4, 6,. ,
Time output is extended from one horizontal scanning time of the progressive scanning system to one horizontal scanning time of the interlaced scanning system, and the output signals of the odd-numbered lines and even-numbered lines that are time-expanded are synchronized with the horizontal scanning of the interlaced scanning system. The two time compression circuits are used to output the signals of the odd-numbered lines and the even-numbered lines expanded at a time corresponding to one horizontal scanning time of the interlaced scanning system input at the same timing. The image pickup apparatus according to claim 1, wherein the image data is compressed into one horizontal scanning time of a sequential scanning system. 3. A digital signal processing circuit group of two systems corresponding to the image signal system of each odd-numbered line and even-numbered line, wherein a high-pass filter circuit for generating a vertical aperture signal in each system includes a luminance signal or a luminance signal. Original signal of similar signal, 1H (1 horizontal scanning time) delay signal, 2
A selection circuit for selecting any two of the three signals of the H (two horizontal scanning time) delay signal; and an addition circuit for adding the selected two signals. And an operation circuit for performing an operation from three signals of the output signal of the addition circuit of the system, the 1H delay signal, and the output signal of the addition circuit of the even line system. 2. The arithmetic circuit according to claim 1, further comprising an arithmetic circuit that performs an arithmetic operation based on three signals of an output signal of the addition circuit of the system, the 1H delay signal, and an output signal of the addition circuit of the odd line system. Imaging device. 4. A high-pass filter circuit for generating a vertical aperture signal in each of two groups of digital signal processing circuits corresponding to a system of imaging signals of each odd-numbered line and an even-numbered line. Original signal of similar signal, 1H (1 horizontal scanning time) delay signal, 2
A first selection circuit for selecting any two of the three signals of the H (two horizontal scanning time) delay signal;
An addition circuit for adding two signals, a second selection circuit for switching and selecting an output signal of the addition circuit of the own system and an output signal of the addition circuit of another system, and an output of the second selection circuit The imaging apparatus according to claim 1, further comprising an arithmetic circuit that performs an arithmetic operation on a signal and the 1H delay signal.