JP3257145B2 - Imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus for a next-generation television system compatible with HDTV, EDTV and the like.

[0002]

2. Description of the Related Art In recent years, widening of screens has been promoted, as in television systems such as HDTV (1125 scanning lines) and second-generation EDTV (525 (625 scanning lines)). Further, in order to pursue higher image quality in the vertical direction, a progressive scanning type imaging device is desired. As described above, the aspect ratio is changed from 4: 3 to 16: 9 in the related art, and a progressive scanning imaging apparatus handles a signal having a wider band than the related art. Therefore, not only an image sensor and a display but also a signal processing circuit requires a dedicated circuit different from a video signal processing device of a standard television system. In particular, recently, digitalization of video signal processing circuits has progressed, and most of these circuits have been implemented as LSIs. When the screen is widened and sequentially scanned, the clock frequency of a circuit for performing digital processing of a video signal increases, so that an arithmetic circuit such as a multiplier, an adder, and a memory must be speeded up. Therefore, in order to digitally process a video signal in a video signal processing device in which a screen is widened and sequentially scanned, it is necessary to develop a dedicated digital processing circuit or LSI in consideration of the speed of an arithmetic circuit. There was a problem that cost became large.

In view of the above problems, a video signal processing apparatus compatible with a television system with a wide screen has been developed by sharing a circuit and an LSI of a conventional video signal processing apparatus for a standard television. Reduce costs,
In recent years, techniques for providing an inexpensive wide-screen video signal processing device have been proposed.

FIG. 7 shows one of the typical methods.
FIG. 2 is a block diagram illustrating a configuration of a signal processing circuit in an image pickup apparatus supporting a wide screen. The main feature of this method is that it divides the wide screen into odd and even pixels and processes them in parallel to reduce the speed of high-speed progressive scanning signals, thereby enabling the use of conventional signal processing circuits such as LSIs. To use.

In FIG. 7, reference numeral 33 denotes an input terminal into which an optical image passed through a lens or the like is input, reference numeral 34 denotes an image pickup device compatible with a wide screen (for example, an aspect ratio of 16: 9), reference numeral 35 denotes a black level, a white level, a pre-gamma, and the like. , An AD converter for converting an output signal of the analog process circuit 35 into a digital signal, and 37 an fck clock rate output signal of the AD converter
e, fo, a dividing circuit for converting a clock rate signal, 3
Reference numerals 8 and 39 denote digital signal processing LSIs for performing gamma correction, enhancement processing, matrix processing, and the like on output signals of the dividing circuit 37, respectively, and 40 converts two digital signal processing LSI output signals having fe and fo clock rates to fck clock rate signals. A synthesizing circuit for synthesizing 41;
DA converter for converting the output signal of
Is a clock generation circuit for generating clock pulses of fck, fe and fo, and 43 is an output terminal.

A conventional wide-screen imaging device (sequential scanning) will be described below with reference to FIGS.

In FIG. 7, an optical image input from an input terminal 33 is formed on an image sensor 34 corresponding to a wide screen, and is output as an electric signal by predetermined vertical and horizontal read pulse driving (not shown). At this time, the horizontal read clock is faster than the read clock of the image sensor of the current TV system (aspect ratio 4: 3). For example, the read of the image sensor of the current TV system is 14.3 MHz (4 fsc; fsc is the color sub-carrier frequency), the read clock of the wide-screen compatible image sensor having the same resolution as this image sensor is
With an aspect ratio of 16: 9, the frequency becomes approximately 19 MHz. Further, when the scanning is performed sequentially, the frequency becomes about 38 MHz (this clock frequency is fck).

The wide-band imaging signal read out by the high-speed clock fck is processed by the analog process circuit 35.
Black level adjustment based on a black balance or the like, white level adjustment based on a white balance or the like, and further, a knee processing are performed. After that, this analog signal is subjected to a subsequent A to perform digital processing which is excellent in accuracy, control and characteristics.
It is converted into a digital signal by the D converter 36. This A
The D conversion is performed by a high-speed clock fck.
The output signal of the AD converter 36 is input to the dividing circuit 37. The dividing circuit 37 divides the signal into a signal at the fe rate and a signal at the fo rate using the low-speed clocks fe and fo output from the clock generating circuit 42 and outputs the divided signals. In the case of this conventional example, the clock generation of fck, fe, and fo is performed by a phase obtained by dividing the frequency of fck by フ リ ッ プ フ ロ ッ by the flip-flop 44 as shown in an example of the internal configuration of the clock generation circuit 42 in FIG. Clocks that differ by 180 ° are fe and fo. That is, the signal is divided into two signals having a frequency of about 19 MHz. Therefore, the processing speed is sufficiently compatible with circuits, LSIs, and the like having a signal processing speed of the conventional television system. For the division operation, for example, two systems of delay flip-flops are prepared, and fe,
This can be easily performed by holding data with the clock of fo.

The two divided signals are input to a digital signal processing LSIa 38 and a digital signal processing LSIb 39, respectively, and are subjected to various digital processing such as gamma correction, enhancement processing, matrix processing and the like. Digital signal processing LSIa38 and digital signal processing LSIb3
The operation of No. 9 is exactly the same, except that the processing phase is different by 180 °. Here, the clock is about 19 as described above.
MHz, which can sufficiently cope with the processing speed of the conventional television system, there is no problem in its operation.
The output signals of the digital signal processing LSIa 38 and the digital signal processing LSIb 39 are synthesized into a signal of the fck rate by a synthesizing circuit 40 including a multiplexer and the like. The digital signal synthesized by the synthesizing circuit 40 is converted into an analog signal by the DA converter 41, and the original wideband wide screen signal is obtained from the output terminal 43.

[0010]

However, in the conventional imaging apparatus for wide screens having the above-described configuration, the wide-screen imaging signal (high-speed imaging signal) is divided into two systems of odd and even pixels to reduce the speed. Therefore, even if an LSI or a signal processing circuit corresponding to the current system can be shared, the data is divided into a signal sequence of odd-numbered and even-numbered pixels. However, there is a problem that accurate filtering processing cannot be performed.

For example, a horizontal aperture circuit included in the enhancement processing circuit generates an aperture signal by calculating a central pixel and peripheral pixels such as one tap and two taps. And accurate filtering cannot be performed.

[0012] In view of the above, the present invention provides an image pickup apparatus compatible with a television system having a wide screen.
Horizontal filtering processing can be performed accurately, and furthermore, development costs are reduced by sharing the signal processing circuit and LSI of the conventional imaging device for standard televisions without increasing the circuit scale, and the imaging device for an inexpensive wide-screen imaging device is used. It is intended to provide.

In order to achieve this object, an image pickup apparatus according to the present invention comprises an AD converter for AD-converting an output signal of an image pickup device with a clock having a predetermined frequency to convert the signal into a digital signal; The output signal is an odd pixel signal,
A pixel division circuit for dividing the pixel sequence into even-numbered pixel signals, and a two-system digital signal processing circuit for performing basic processing of the imaging apparatus, such as gamma processing, enhancement processing, and matrix processing, on the signal sequence of the divided odd-numbered pixel signals and even-numbered pixel signals And a pixel synthesizing circuit for synthesizing a two-system signal sequence of an odd-numbered pixel signal and an even-numbered pixel signal output from the two-system digital signal processing circuit system into a one-system signal sequence. A filter operation circuit included in the enhancement processing circuit of the signal processing circuit system is configured to generate the clock of the predetermined frequency.
When the delay in one clock is Z ^-1 and pixel division is not performed
Horizontal aperture signal with arbitrary boost frequency
Pixel signal pair Pi required for each other system to obtain
xaddde = Z-2m ^{+ (2n + 1)} + Z- ^{2m- (2n + 1)} , Pixad
do = Z- ^{(2m + 1) + (2n + 1)} + Z- ^{(2m + 1)-(2n + 1)} (m and n are
A pixel addition signal output circuit for outputting an integer) and the other system
Pixel signal pair Pix output from the conventional pixel addition signal circuit
addde, Pixaddo and filter operation of own system
From the center pixel other than the center pixel in the pixel signals used for processing
Pixel signal pair Pixadde1 = Z at symmetric position
^{-2m + (2n + 2)} + Z ^{-2m- (2n + 2)} , Pixaddo1 = Z
^{-(2m + 1) + (2n + 2)} + Z- ^{(2m + 1)-(2n + 2)} .

Further, in the image pickup apparatus of the present invention, the two-system pixel addition signal output circuit included in the filter operation circuit of the enhancement processing circuit is provided with a pixel signal pair necessary for an odd pixel signal sequence and an even pixel signal sequence. This is an imaging apparatus having the same circuit configuration so as to be switched and output and to be commonly used by switching the selection to both systems.

[0015]

According to the present invention, the output signal of the image sensor is converted into a digital signal by A / D conversion with a clock of a predetermined frequency, and the pixel signal is divided into an odd pixel signal and an even pixel signal. Divided into The two divided signal series are processed in parallel by digital signal processing circuits corresponding to the respective systems. The filter operation circuit of the enhancement processing circuit included in each of the two systems of digital signal processing circuits outputs a pixel signal pair necessary for each of the other systems in order to obtain a horizontal aperture signal of an arbitrary boost frequency obtained without division. A pixel addition signal output circuit is provided, and an output signal of each of the pixel addition signal output circuits is output to another system. In each of the filter operation circuits, a pixel signal pair other than the center pixel used in the filter operation processing of its own system and a pixel signal pair input from another system are selected by a selection circuit to obtain a desired horizontal aperture signal. be able to.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an image pickup apparatus according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an AD converter for converting an imaging signal into a digital signal, reference numeral 2 denotes a pixel dividing circuit for dividing an output signal of the AD converter 1 into two signal sequences of odd-numbered pixels and even-numbered pixels, and 3, 4 Gamma correction circuits for performing gamma correction on signal sequences of odd-numbered pixels and even-numbered pixels, enhancement processing circuits for performing horizontal and vertical aperture corrections, matrix circuits for generating Y, color difference signals, etc., This is a pixel synthesizing circuit that synthesizes the divided two pixel signal sequences into the original imaging signal.

The operation of the first embodiment of the present invention will be described below with reference to FIGS. 2 (a), (b),
(C) is an explanatory diagram for explaining data delay in pixel division, and 10 is a delay flip-flop for providing a delay time D. FIG. 3 is a block diagram showing an example of an internal configuration of a filter operation circuit of a horizontal aperture included in a conventional enhancement processing circuit. Reference numeral 11 denotes a delay flip-flop for providing a delay time D, and reference numeral 12 denotes a coefficient multiplied by a coefficient shown in FIG. The multiplier 13 is an adder. FIG. 4 (A)-
(D) shows the characteristic formulas (A) to (3) of the filter operation circuit of FIG.
FIG. 5D is a frequency characteristic diagram, and FIG. 5 is a block diagram showing an example of a filter operation circuit included in the enhancement processing circuit according to the embodiment of the present invention. 19 is a multiplier to be multiplied by the coefficient shown in the figure, 16, 20 are adders, 17, 21
Is a selector.

In FIG. 1, an image pickup signal output from an image pickup element (aspect ratio 16: 9) corresponding to a wide screen (not shown) is subjected to a subsequent AD converter for performing digital processing excellent in accuracy, control and characteristics. 1 is converted to a digital signal. The wide-screen imaging signal converted into a digital signal is divided into two systems of a signal sequence of odd-numbered pixels and a signal sequence of even-numbered pixels by the pixel dividing circuit 2 in the same manner as in the conventional example.

The signals of the odd-numbered pixel signal sequence and the even-numbered pixel signal sequence obtained by the pixel division are respectively applied to the gamma processing circuits 3 and 4 of the digital signal processing circuit, the enhancement processing circuits 5 and 6,
Gamma correction, horizontal and vertical aperture correction of signal processing required for the imaging device through matrix processing circuits 7 and 8,
Matrix processing and the like are performed. An odd pixel signal sequence,
Since the signal of the signal sequence of the even-numbered pixels is divided into pixels as in the conventional example, the processing speed may be half the speed of the sequential scanning or the interlaced scanning in the case of not dividing, and the imaging device of the conventional standard television system is sufficiently used. Circuit and LS used in
I can be shared. After various digital signal processing,
The odd-numbered pixel signal sequence and the even-numbered pixel signal sequence are synthesized by the pixel synthesizing circuit 9 and thereafter converted into an analog signal by a DA converter (not shown) to obtain an imaging device output signal (wide-screen-compatible imaging signal).

Here, the major difference from the conventional imaging apparatus is that
Signals are exchanged between the enhancement processing circuits 5 and 6, and an aperture signal having a desired frequency characteristic can be obtained even when pixel division is not performed.

The configuration and operation for achieving the above will be described below. FIGS. 2A, 2B and 2C are explanatory diagrams for explaining the delay of pixel data in pixel division. If the configuration of the delay circuit is shown in FIG. Given by time D at step 10,
Assuming that the tap positions of the delay flip-flops 10 are (1), (2), (3),..., The signals at the tap positions are (1), (2), (3) in FIG. The signal is delayed as shown in FIG. If the clock frequency without pixel division is fck, D = 1 / fck.
When the pixel is divided, the delay flip-flop 10 operates with the clocks of fcke and fcko obtained by dividing fck by に よ り using a clock generation circuit similar to the conventional example.
D = 2 / fck as shown in FIG. The data is divided into data rows D0, D2,... Of even pixels and data rows D1, D3,. At this time,
The data row of the even-numbered pixels and the data row of the odd-numbered pixels have a phase difference of a half cycle, that is, 1 / fck. Therefore, if the delay caused by one delay flip-flop 10 without pixel division is expressed as Z ⁻¹ (Z conversion), when the tap (1) is used as a reference, as shown in FIG. the position (2), (3), (4), the delay display the even pixel series of ... is ^{Z 0, Z -2, Z -4} , ···, odd sequence Z ^-1, Z ^{- 3} , Z ^-5 ,... Exponential part
The number indicates the amount of delay, but the delay display of the even-numbered pixel series
Represented as an even multiple of the delayed display when not divided, and odd pixels
The series delay display is an odd multiple of the delay display without division
It is expressed as Therefore, filter operations such as horizontal aperture
Delay table when not dividing for each series
(I.e., even-numbered pixel series are represented by Z ^-1 , Z ^-3 , Z ^-5 ,
Signal such as ..., odd pixel sequence ^{Z 0, Z -2, Z -4} , ·
.. etc.), an even pixel series signal,
Whether the odd pixel sequence signal is the center pixel for each operation
An odd-numbered delayed display signal is required. on the other hand
In the calculation with division, the delay display of each series
As can be seen, it is separated from the central pixel of the operation by a few even
That is, the calculation is performed with the pixels.

Here, taking the horizontal aperture filter operation circuit included in the conventional enhancement processing circuit having the configuration shown in FIG. 3 as an example, consider the frequency characteristics when a horizontal aperture signal is created. When pixel division is not performed, the arithmetic expression of the central pixel of the arithmetic operation and the one-tap pixel signal pair from the central pixel is expressed by the expression (A) as shown in the figure, and -Z ^-2 + 2Z ^-3 -Z ^-4 Become.

The calculation with a pixel signal pair two taps away from the center pixel is represented by the formula (B), which is -Z ^-1 + 2Z ^-3 -Z ^-5 .

On the other hand, when the pixel is divided, as shown in FIG.
Sea urchin, the delay display Z ⁰ when no pixel division, Z ^-1, ...,
Z ^-6 is Z ^0, Z ^-2, ..., a Z ^-12. Therefore, shown in the upper part of FIG.
The delay indication signal is transmitted to the delay flip-flop 11 and
And a multiplier 12 and an adder 13 to set the center pixel Z- ⁶ .
Expression (A) of one tap pixel signal pair from the center pixel
The operation to issue ^{characteristics, -Z -4 + 2Z -6 -Z -8} = Z -2 (-Z -2 + 2Z -4 -Z -6) , and the drawing took delay of Z ^-2 (C) Characteristics shown in the formula
Becomes Also, two pixels from the center pixel with respect to the center pixel Z- ⁶ .
Calculate the characteristics of the operation formula (B) with the pixel signal pair separated by a distance
Operation is shown in ^{-Z -2 + 2Z -6 -Z -10 =} Z -1 (-Z -1 + 2Z -5 -Z -9) , and the same figure (D) expression hazy delay Z ^-1 characteristic
Becomes If the pixel is divided in this way,
The characteristic when the pixel division shown in the characteristic formulas (A) and (B) is not performed
The horizontal aperture signal cannot be obtained. these
When the pixel is divided into two, the characteristics are both odd and even pixels.
The frequency characteristics of the signal series are the same except for the phase shift.
You.

The characteristic diagrams are shown in FIGS. 4A to 4D (characteristic expressions (A) to (D) correspond to the characteristic diagrams (A) to (D)). FIG. 4 shows that the characteristic expressions (A) to (D) are high-pass fills.
The center pixel and one clock away from the center pixel.
Calculation (corresponding to characteristic equation (A))
(Fck = 図 fck in FIG. 4A)
Position). Center pixel and center image
In an operation with a pixel two clocks away from the element,
(Corresponding to (B) and (C)), and from FIG.
And 3/4 frequency (fck in FIGS. 4B and 4C).
= 1 / 4fck, 3 / 4fck position)
Characteristics. Similarly, the center pixel and four clocks from the center pixel
In the calculation with pixels that are far away from each other (corresponding to characteristic equation (D)),
4 shows that 1/8, 3/8, 5/8, and 7/8 of the clock
It has the characteristic of boosting the frequency. Normal imaging device
Wave number characteristics show that attenuation is large for frequencies more than half of the clock.
As a result, in the case of the characteristic expressions (B) and (C),
Characteristic for boosting mainly 1/4 frequency, characteristic equation (D)
In case of, mainly boost 1/8 frequency of clock
Characteristics. When divided into pixels, the same filter circuit configuration
Then, boost frequency of 1/2 frequency when not dividing
Only characteristics can be obtained.

Therefore, the horizontal aperture operation circuit of the enhancement processing circuit in the image pickup apparatus of the present invention has a configuration shown in FIG. In this example, a horizontal aperture signal is obtained by calculating a pixel signal pair one tap away from the center pixel and the center pixel.

Assuming that the delayed display of the center pixel of the even-numbered pixel signal processing system is Z ^-4 , the selector 1 is selected by the control signal S1.
By selecting the I0 input of 7, operation of only the signal of the own system (even-numbered pixel signal processing system), i.e. the center pixel Z ^-4
The delay free multiplied by a predetermined multiple in the multiplier 15 of FIG.
The output signal of flip-flop 14 is added by adder 16
The pixel signal pair Pixaddo1 = Z− ² + Z− ^{6 of the} own system is operated by the adder 16 after the selector 17 to obtain the horizontal aperture signal of the characteristic expression shown in the expression (E) (the frequency characteristic diagram of FIG. 4). (B)). On the other hand, the I1 input of the selector I7 is supplied to the center pixel Z from another system (odd pixel signal processing system).
^-4 , a pixel signal pair Pixado = Z ^-3 + Z ^-5 separated by one tap when not divided into pixels is input. When this I1 input is selected, the characteristic shown in equation (G) is obtained by filter operation. The horizontal aperture signal of the formula is obtained, and the horizontal aperture signal having the same characteristic as the characteristic obtained by the calculation with the signal pair of the pixel separated by one tap when the pixel is not divided is obtained.

Further, to the circuit of the even-numbered pixel signal processing system, a pixel addition signal pair Pixadde = Z ^-4 + Z ^-6, which is also required by the circuit of the odd-numbered pixel signal processing system, is output.

Similarly, the center pixel delay display of the odd-numbered pixel signal processing system becomes Z- ⁵ because there is a phase shift of Z ^-1 compared to the signal of the even-numbered pixel. When the I0 input of the selector 21 is selected by the control signal S2, , Calculation of only the signal of its own system (odd pixel signal processing system) , that is, the center pixel
The ^{delay obtained} by multiplying Z ^-5 by a predetermined multiple by the multiplier 19 of FIG.
Output signal of flip-flop 18 is added by adder 20
The pixel signal pair Pixadde1 = Z ^-3 + Z ^{-7 of} the own system is calculated by the adder 20 after the selector 21 to obtain a horizontal aperture signal of the characteristic expression shown in Expression (F) (the frequency of FIG. 4). Characteristic diagram (B)).

Pixadde = Z ^-4 + Z ^-6 is input to the input of the selector I1 from another system (even-numbered pixel signal processing system). When this I1 input is selected, the characteristic shown in the equation (H) is obtained by filter operation. The horizontal aperture signal of the equation (the frequency characteristic diagram (A) of FIG. 4) is obtained.

The odd pixel signal processing circuit outputs a pixel addition signal pair Pixaddo = Z ^{−3 +} Z ⁻⁵ required for the even pixel signal processing system.

With the above-described configuration, the image pickup apparatus of the present invention provides a horizontal aperture signal having a characteristic when the even pixel signal processing system and the odd pixel signal processing system are divided into pixels, and a characteristic when the pixel is not divided. The horizontal aperture signal can be switched and output, and a horizontal aperture signal having a characteristic in the case of not performing pixel division, which has not been obtained by conventional pixel division, can also be obtained.

Needless to say, the phase shift between the even-numbered pixel signal processing system and the odd-numbered pixel signal processing system can be selected and synthesized according to the phase shift when synthesized by the pixel synthesizing circuit 9, so that there is no problem.

Next, an image pickup apparatus according to a second embodiment of the present invention will be described. FIG. 6 is a block diagram showing the configuration of the horizontal aperture filter operation circuit included in the enhancer processing circuit in the imaging device according to the second embodiment of the present invention. In FIG. 6, 22 is a delay flip-flop, 23 is a multiplier, 24 is an adder, 25, 26, 27, and 28 are selectors, and 29 is a subtractor.

The present embodiment differs from the first embodiment in that the even pixel signal processing system and the odd pixel signal processing system do not have separate circuits but have the same circuit shown in FIG. is there. The operation will be described below.

Assuming that the delay display of the center pixel when the pixel is not divided is Z ^-4 , the center pixels of the signal series of the even-numbered pixel and the odd-numbered pixel are represented by Z ^-8 and Z ^-9 . Therefore,
As an operation for obtaining a horizontal aperture characteristic when pixel division is not performed in each system, a pixel addition signal pair necessary for an operation of a pixel signal separated from the center pixel by one tap is represented by an even pixel signal processing system of Z ⁻⁷ + Z ^{The -9} odd pixel signal processing system is Z ^-8 + Z ^-10 .

When the circuit of FIG . 6 is used, as described above,
The delay display without division is as shown in the figure.
The center pixel is Z ^-4 and the delay flip-flop 22
The signals of Z- ¹ , Z- ² , Z- ³ , Z- ⁴ , Z- ⁵ , Z- ⁶ and Z- ⁷ are obtained.
Can be The even pixel system and the odd pixel system obtained by dividing the circuit of FIG.
If applied to several pixel systems, the center pixel is Z ^-8 , Z
^-9 , the delay flip-flop 22
Each output is not shown, but the even-numbered pixel series is Z ^-2 ,
Z ^-4 , Z ^-6 , Z ^-8 , Z ^-10 , Z ^-12 , Z ^-14 , even pixel system
Column ^{Z -3, Z -5, Z -7} ,, Z -11, Z -13, I and Z ^-15
You. Therefore, when the circuit of FIG. 6 is used for an even-numbered pixel signal processing system, if the input I1 of the selector 25 is selected by the select signal S1, the Z- ^{8 of} the central pixel can be selected.
Z- ^{10, which} is delayed by one clock, is selected.
Is added to the center pixel Z ^-8 by the adder 24, and a pixel addition signal pair Z ^-8 + Z ^-10 required in the odd pixel signal processing system
Is output as the A output.

On the other hand, when the circuit shown in FIG. 6 is used in an odd pixel signal processing system, the selector 25 receives the select signal S1.
By selecting the I0 input of the
Z- ⁷ one clock before the original Z- ⁹ is selected,
The signal is added to the center pixel Z- ⁹ by the adder 24, and the pixel addition signal pair Z- ⁷ + Z- ⁹ required in the even-numbered pixel signal processing system is A.
Output as output.

Similarly, the selector 2 is selected from the select signal S1.
6, when the I1 input of the selector 27 is selected, in the even pixel signal processing system, as shown in FIG.
At 26, Z- ⁶ , one clock before the center pixel Z- ⁸ , and the center image
Z- ¹² delayed by two clocks from the original Z- ⁸ is adder 2
4 to select the signal added, so that Z ^-6 + Z ^-12
Is output as the B output. In the selector 27, the central pixel
Of Z ^-8 than two clocks before Z ^-4 and of the central pixel Z ^-8 than 3
Clock-delayed Z ^-14 is added by adder 24
Select the signal, so Z ^-4 + Z ^-14 is output as C output
Is output. Therefore, a pixel signal pair which is required in the odd pixel signal processing system and is 3 taps away from the center pixel Z- ^9, and 5
A pixel signal pair separated by a tap is obtained. In the odd pixel signal processing system, the selector 26, the selector 26,
When the I0 input of the selector 27 is selected, as shown in FIG.
As described above, first, in the selector 26, two ^{clicks are performed} from the center pixel Z- ⁹ .
One clock delay from Z ^-5 before locking and Z ^{-9 of the} center pixel
The selected Z ^-11 is selected by the adder 24.
Therefore, Z ^-5 + Z ^-11 is output as the B output. C
In the collector 27, Z ^{-3 which} is three clocks before Z ^{-9 of the} center pixel
And Z ^{-13 which} is two clocks delayed from Z ^{-9 of the} center pixel
Since the signal added by the adder 24 is selected, Z ^-3
+ Z ^-13 is output as the C output. Therefore, a pixel signal pair that is 3 taps away from the center pixel Z- ⁸ and a pixel signal pair that is 5 taps away, which are required in the even pixel signal processing system, are obtained.

The A, B, and C outputs of each system are as described above.
Output, as shown in FIG.
And I0, I2, I4 inputs of the selector 28
Is input to Therefore, odd-numbered pixels are used in the even-numbered pixel signal processing system.
Z ^-7 + Z ^-9 of the A output of the signal processing system is the I of the selector 28.
0, Z ^-5 + Z ^-11 of the B output to I2 of the selector 28,
Z output Z ^-3 + Z ^-13 is input to I4 of the selector 28.
You. Also, as shown in FIG.
One pixel of the center pixel Z- ^{8 is} calculated in the even pixel signal processing system .
The signal of Z- ⁶ before lock and Z- ¹⁰ of 1 clock delay are
Z ⁻⁶ + Z ⁻¹⁰ added by the adder 24 is input. Ma
In addition, I3 of the selector 28 has an even pixel signal processing system.
2 clocks before Z ^-4 and 2 clock of the central pixel Z ^-8 in the calculation
Z obtained by adding the Z- ¹² signal of the delay to the adder 24
^-4 + Z ^-12 is input. In addition, I5 of the selector 28
Is the central pixel Z- ⁸ of the calculation in the even pixel signal processing system.
Z- ² signal before clock and Z- ¹⁴ signal with 3 clock delay
Are added by the adder 24, and Z ⁻² + Z− ¹⁴ is input.
Similarly, the odd pixel signal processing system has the even pixel signal processing.
Z- ⁸ + Z- ¹⁰ of the A output of the logical system is the I0 of the selector 28.
And Z ^-6 + Z ^-12 of the B output is connected to I2 of the selector 28 and C
The output Z ^-4 + Z ^-14 is input to I4 of the selector 28.
You. An odd pixel signal processing system is provided at I1 of the selector 28.
Z ^-7 and 1 one clock before the center pixel Z ^-9 in the calculation within
The clock delay Z- ¹¹ signal is added by the adder 24.
Z ^-7 + Z ^-11 is input. In addition, the selector 28
I3 has a central pixel Z by an operation in the odd pixel signal processing system.
Z- ⁵ two clocks before ^-9 and Z- ¹³ two-clock delay
Z ^-5 + Z ^-13 is of input signals are added by the adder 24
It is. The odd pixel signal processing is applied to I5 of the selector 28.
In the calculation in the system, Z ^-3 three clocks before the center pixel Z ^-9 and
Adder 24 adds Z- ¹⁵ signal with 3 clock delay
The input Z ^-3 + Z ^-15 is input. Here, in both systems, if the select signals S2 to S7 of the selector 28 are the same, if the I0 input is selected, a pixel addition signal pair (input from another system) at a position one tap away from the center pixel, I1 If the input is selected, a pixel addition signal pair at a position one tap away from the own system, that is, a position two taps away, and if the input is selected, a pixel addition signal pair at a position three taps away (input from another system), I3 If the input is selected, a pixel addition signal pair at a position two taps away from the own system, that is, a position four taps away, and if the input is selected, a pixel addition signal pair at a position five taps away (input from another system), I5 If an input is selected, a pixel addition signal pair at a position 3 taps away from the own system, that is, a position 6 taps away is output from the selector 28, and the center pixel Z of each system is output. ^-8 and Z ^-9 are filtered and the pixels are not divided
A horizontal aperture signal having desired characteristics similar to the above is obtained.

As described above, according to the second embodiment of the present invention, even if the even pixel signal processing system and the odd pixel signal processing system have the same circuit configuration as shown in FIG. By changing the setting of the select signal, a signal necessary for another system can be output, and a signal exactly the same as a horizontal aperture signal having characteristics when pixel division is not performed can be obtained. The use of the same circuit configuration provides versatility. For example, when the enhancer processing circuit is implemented as an LSI, the same LSI can be used, and the development cost can be reduced.

In the first and second embodiments of the present invention, the filter operation circuit has a horizontal aperture circuit structure. However, it goes without saying that the filter operation circuit of another circuit can be similarly applied.

[0044]

As described above, according to the present invention, in configuring an image pickup apparatus compatible with a television system having a wide screen, pixels are divided into two signal sequences of even-numbered pixels and odd-numbered pixels. Even when the processing is performed, a signal having the same characteristics as the filter characteristics such as the horizontal aperture when the pixel is not divided can be obtained.

In addition, the same signal processing circuit or LSI can be used in the two signal processing systems, so that an imaging device that can reduce the development cost and is inexpensive for a wide screen can be provided, and its practical effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of an imaging apparatus according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining data delay in pixel division.

FIG. 3 is a block diagram showing an example of an internal configuration of a filter operation circuit of a horizontal aperture included in a conventional enhancement processing circuit;

4 is a characteristic equation (A) to of the filter operation circuit of FIG. 3;
(D) Frequency characteristic diagram

FIG. 5 is a block diagram showing a configuration of a filter operation circuit included in an enhancement processing circuit of the imaging apparatus according to the first embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a filter operation circuit included in an enhancement processing circuit of the imaging apparatus according to the second embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a signal processing circuit of a conventional imaging device (supporting a wide screen).

FIG. 8 is a block diagram showing an example of an internal configuration of a clock generation circuit 42 in the conventional example and a timing chart thereof.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D converter 2 Pixel division circuit 3, 4 Gamma processing circuit 5, 6, Enhancement processing circuit 7, 8, Matrix processing circuit 9 Pixel synthesis circuit 14, 18, Delay flip-flop 15, 19 Multiplier 16, 20 Adder 17, 21 selector

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-12769 (JP, A) JP-A-3-268678 (JP, A) JP-A-3-38177 (JP, A) JP-A-4- 186975 (JP, A) (58) Fields surveyed (Int. Cl. ⁷ , DB name) H04N 5/208

Claims (2)

(57) [Claims] An A / D converter for converting an output signal of the imaging device into a digital signal by performing an A / D conversion with a clock of a predetermined frequency; and dividing the digitized output signal of the imaging device into an odd pixel signal and an even pixel signal. A two-system digital signal processing circuit system for performing basic processing of an imaging device such as gamma processing, enhancement processing, matrix processing, and the like on the divided odd-numbered pixel signal and even-numbered pixel signal signal sequence; A pixel synthesizing circuit for synthesizing two signal sequences of odd-numbered pixel signals and even-numbered pixel signals output from a digital signal processing circuit of one system into one signal sequence. The filter operation circuit included in the enhancement processing circuit is configured to output the predetermined frequency
When the delay of one clock of the clock is Z ⁻¹ , the pixel
Horizontal for any boost frequency obtained without splitting
To obtain the aperture signal,
Pixel signal pair Pixadde = Z−2m ^{+ (2n + 1)} + Z
^{-2m- (2n + 1)} , Pixaddo = Z- ^{(2m + 1) + (2n + 1)} + Z
Pixel addition signal that ^{outputs-(2m + 1)-(2n + 1)} (m and n are integers)
Signal output circuit and the pixel addition signal circuit of the other system.
The pixel signal pair Pixadde, Pixadd to be applied
o and the pixel signals used in the filter operation
Pixel signals at symmetric positions from the center pixel other than the center pixel
Pixaddde1 = Z -2m ^{+ (2n + 2)} + Z ^{-2m- (2n + 2)} , P
ixaddo1 = Z- ^{(2m + 1) + (2n + 2)} + Z- ^{(2m + 1)-(2n + 2)}
An imaging apparatus comprising a selection circuit for selecting any one of the following. 2. The pixel addition signal output circuit of the two systems included in the filter operation circuit of the enhancement processing circuit is configured to switch and output a pixel signal pair required for a series of odd pixel signals and a series of even pixel signals. 2. The image pickup apparatus according to claim 1, wherein the same circuit configuration is used so that the two circuits can be commonly used by switching the selection.