JPH11308575A - Interpolation arithmetic unit and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale and number of processing steps, to conduct interpolation arithmetic operation with high precision and to conduct the interpolation arithmetic operation at an optional rate in real time. SOLUTION: This unit is provided with delay circuits 2, 3 connected on a cascade to extract outputs of 1st and 2nd taps, 1st and 2nd multiplier circuits 4, 5 that multiplies 1st and 2nd filter coefficients respectively, an adder circuit 9 that sums outputs of the multiplier circuits 4, 5, and a coefficient generating circuit 6 that generates the filter coefficient in response to phase information. The filter coefficient is generated so that a combination of multi-degree polynomials with a gain '1' where they are in point symmetry at a position of '0.5' is obtained, that is, a relation of f2 (p)=1-f1 (p) is obtained, where f1 (p) is a 1st filter coefficient and f2(p) is a 2nd filter coefficient. Thus, the interpolation is conducted with high precision and one filter coefficient is obtained from the other coefficient by subtraction and the interpolation is processed in real time at an optional ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interpolation apparatus and method suitable for use in enlargement and reduction of an image or conversion of a sampling frequency or the number of lines.

[0002]

2. Description of the Related Art Standard television broadcast signals include N
The TSC (National Television System Committee) method and the PAL (Phase Alternation by Line) method are known. In the NTSC system, the number of scanning lines in one frame is 525, while in the PAL system, the number of scanning lines in one frame is 625. The number of scanning lines differs between the NTSC system and the PAL system.

[0003] Not only standard systems such as NTSC system and PAL system, but also HDTV (High Definition
Television) is being developed. In the HDTV system, the number of scanning lines in one frame is one.
There are 125 lines.

Further, in a computer image, a video signal of a format different from that of a television broadcast is used, and the number of pixels of a VGA (Video Graphics Array) is (6).
40 × 480) dots, and the number of pixels of SVGA (Super VGA) is (1024 × 768) dots.

As described above, when performing system conversion between video signals of a plurality of systems having different numbers of pixels in the horizontal direction and the number of scanning lines, an interpolation operation is performed. In addition, when the image is enlarged or reduced, the number of pixels in the horizontal direction and the vertical direction is converted, and at this time, an interpolation operation is performed.

In the interpolation operation, the value of pixel data at a position that did not exist in the original image is obtained using peripheral pixel data.

For example, as shown in FIG. 7, it is assumed that original pixels Ra, Rb, Rc and Rd are arranged side by side at a sampling interval S in the horizontal direction. Then, the pixel data at the position Q indicated by the arrow is formed by interpolation.

Since there is a correlation between neighboring pixel data arranged in the horizontal direction, the pixel data at the position Q is not
It can be obtained from the pixel data of a, Rb, Rc, and Rd. That is, the filter coefficients are Ha, Hb, Hc, H
Assuming that d, the pixel data at the position Q can be obtained by a convolution operation as follows: Q = Ha × Ra + Hb × Rb + Hc × Rc + Hd × Rd

Here, in order to perform an optimal interpolation operation, the number of taps and how to obtain a filter coefficient poses a problem. According to the sampling theorem, ideal interpolation uses a sinc function f (x) = sinc (x) = sin (x) / x as an interpolation function as shown in FIG. It is supposed to be a convolution operation until the future.

However, a convolution operation from the past infinite time to the future infinite time is practically impossible. Therefore, how to approximate the sinc function to a simple interpolation function for a finite period is a practical problem. As the number of taps increases, the circuit scale increases accordingly.
Further, when the calculation of the filter coefficient becomes complicated, the circuit scale increases, and the process of obtaining the filter coefficient becomes complicated.

Conventionally, as an approximation method for an interpolation operation, a nearest neighbor approximation method, a bilinear approximation method, a cubic approximation method, and the like have been known. In the nearest neighbor approximation method, as shown in FIG. 9A, interpolation is performed using the nearest pixel data. That is, in the nearest neighbor approximation method, (−0.5 <x ≦
When 0.5), f (x) = 1, and when (−0.5 ≧ x, x> 0.5), f (x) = 0.

In the nearest neighbor approximation method, interpolation is performed by replacing the nearest pixel data. Therefore, the processing is simple, but the accuracy of the interpolation is not good.

In the bilinear approximation method, as shown in FIG. 9B, interpolation data is obtained by using a weighted average of two neighboring pixels. That is, in the bilinear approximation method, when (| x | ≦ 1), f (x) = 1− | x |, and when (| x |> 1), f (x) = 0.

In the bilinear approximation method, the calculation is performed with two taps, so that the circuit scale is relatively small. In addition, the set of filter coefficients becomes a coefficient that becomes “1” when two filter coefficients are added, so that the coefficient can be relatively easily obtained.

That is, assuming that the phase is p, the filter coefficient is obtained by (x ₁ = p, x ₂ = 1−p).
Is (p = 0), the coefficient set is (1, 0), and when the phase p is (p = 0.5), the coefficient set is (0.5, 0.5). When the phase p is (p = 0.3), the coefficient set is (0.7, 0.3). Therefore, the filter coefficient can be obtained in real time.

However, in the bilinear approximation method, although the interpolation accuracy is improved as compared with the nearest neighbor approximation method, the screen becomes blurred, and it is difficult to obtain good image quality.

In the cubic approximation method, as shown in FIG. 9C, a filter coefficient is obtained by using a third-order polynomial, and interpolation data is obtained from four pixels by a convolution operation. That is, in the cubic approximation method, (| x | ≦
In the case of 1), f (x) = | x | ³ -2 | x | ² +1. In the case of (1 <| x | ≦ 2), f (x) = − | x | ³ −5 | x | ² -8 | x | +4, and becomes a when the, f (x) = 0 ( 2 <| | x).

In the cubic approximation method, the accuracy of correction is higher than that of the nearest neighbor approximation method and the bilinear approximation method, and a good picture is obtained. However, the cubic approximation method requires an operation using a 4-tap FIR filter, and the filter coefficients cannot be easily obtained.

That is, FIG. 10 shows a configuration of a conventional interpolation circuit in the case where an interpolation operation is performed by the cubic approximation method.

In FIG. 10, 101, 102, 10
3, 104 are delay circuits. These delay circuits 101 to
104 are cascaded. Each delay circuit 101-104
Has a delay of one sample. These delay circuits 101 to 104 constitute a shift register.

From input terminal 111 to delay circuits 101 to 10
4 is supplied with digital video data. The delay circuits 101 to 104 have a clock input terminal 1
12 supplies a clock. With this clock,
Digital video data from the input terminal 111 is transferred. Therefore, between the stages of the delay circuits 101 to 104,
Four consecutive samples of pixel data are obtained.

The delay circuits 101, 102, 103, 104
Are supplied to multiplication circuits 105, 106, 107 and 108, respectively. Multiplication circuits 105, 106, 107, 10
8 is supplied with a filter coefficient from the coefficient generation circuit 109.

The coefficient generating circuit 109 has an input terminal 113
Supplies phase information. The coefficient generating circuit 109 generates a filter coefficient according to the phase information. The filter coefficients are supplied to multiplication circuits 105 to 108.

The multiplication circuits 105 to 108 form a delay circuit 10
Each pixel data from between the stages 1 to 104 is multiplied by a filter coefficient from the coefficient generation circuit 109. The outputs of the multiplication circuits 105 to 108 are supplied to the addition circuit 110.
The output of the adder circuit 110 is taken out from the output terminal 114.

As shown in FIG. 10, the interpolation operation by the cubic approximation method can be realized by a 4-tap FIR filter. Then, in the coefficient generation circuit 109, a filter coefficient corresponding to the phase is obtained, and this filter coefficient is supplied to the multiplication circuits 105 to 108.

In an actual interpolation operation circuit, the above-described configuration may be realized by hardware as it is, or the procedure may be realized by software using a software program installed in a processor. However, in the case of real-time image processing, the realization by a software program is practically difficult because the inter-sample period of video data is as short as 50 nanoseconds.

The filter coefficient can be obtained by a third-order polynomial as in the above equation. For example, if the phase p is (p =
0), the coefficient set is (0.0, 1.0, 0.
0, 0.0), and the data of the pixel whose position matches is output as it is. When the phase p is (p = 0.5), the coefficient set is (−0.125, 0.625, 0.6)
25, -0.125), and the phase p is (p = 0.3)
, The coefficient set is (−0.063, 0.84
7, 0.363, -0.147).

[0028]

As described above, when the interpolation operation is performed by cubic approximation, and when the conversion ratio has a predetermined relationship, the phase p changes regularly. Coefficient sets may be prepared in advance, and these coefficient sets may be switched by phase data.

However, in order to make the conversion ratio general, it is necessary to store the coefficient sets of all combinations. However, storing the coefficient sets of all the combinations increases the circuit scale and requires a process of transferring the coefficients again, which complicates the process. For this reason, when the conversion ratio is intended to have generality, the coefficient set is set to 3
It must be obtained directly from the degree polynomial. However, calculating a coefficient set from a third-order polynomial requires a large number of multiplication processes. For this reason, it becomes difficult to perform a filter operation in real-time processing.

Accordingly, it is an object of the present invention to provide an interpolation operation apparatus and method capable of reducing the circuit scale and the number of processing steps.

Another object of the present invention is to provide an interpolation operation apparatus and method capable of performing an interpolation operation accurately with a small circuit scale.

It is another object of the present invention to provide an interpolation calculation apparatus and method capable of obtaining filter coefficients in real time by interpolation calculation at an arbitrary ratio.

[0033]

According to a first aspect of the present invention, there is provided an interpolation operation device for performing an interpolation operation by a convolution operation by multiplying outputs of first and second taps by first and second filter coefficients. Cascaded delay means for extracting outputs of the first and second taps, and a second means for multiplying the outputs of the first and second taps output from the delay means by first and second filter coefficients, respectively. First and second multiplying means, adding means for adding outputs of the first and second multiplying means, and coefficient generating means for generating first and second filter coefficients according to the phase information; The first and second filter coefficients are generated by a combination of polynomials that are point-symmetric at a position where the gain is “1” and the phase is “0.5”, and an interpolation operation output is obtained from the adding means. Interpolation operation device .

According to a fourth aspect of the present invention, there is provided an interpolation operation device for performing an interpolation operation by a convolution operation by multiplying outputs of a first and a second tap by first and second filter coefficients. Cascaded delay means for extracting the output of the tap, subtraction means for subtracting the output of the first and second taps output from the delay means, and multiplication for multiplying the output of the subtraction means by a first filter coefficient Means and the first
Adding means for adding the output of the tap and the output of the multiplying means,
Coefficient generating means for generating a first filter coefficient in accordance with the phase information, wherein the first and second filter coefficients are point-symmetric at a position where the gain is “1” and the phase is “0.5”. An interpolation operation device, which is generated by a combination of polynomial expressions and obtains an interpolation operation output from an adding means.

According to a sixth aspect of the present invention, there is provided an interpolation operation method for performing an interpolation operation by a convolution operation by multiplying outputs of first and second taps by first and second filter coefficients. The filter coefficient is generated by a combination of polynomials that are point-symmetrical at a position where the gain is “1” and the phase is “0.5”. The outputs of the first and second taps are extracted, and the first and second taps are extracted. And the second filter coefficients are generated, the outputs of the first and second taps are multiplied by the first and second filter coefficients, respectively, and the outputs of the first and second multiplication means are added to perform an interpolation operation. There is an interpolation calculation method characterized in that an output is obtained.

According to a ninth aspect of the present invention, there is provided an interpolation apparatus for performing an interpolation operation by a convolution operation by multiplying the output of the first and second taps by a filter coefficient, wherein the first and second filter coefficients have a gain. When the phase is “0.
5 ”is generated by a combination of polynomials that are point-symmetrical at the position“ 5 ”, the outputs of the first and second taps are taken out,
And the output of the second tap is subtracted, a first filter coefficient is generated according to the phase information, the output of the subtraction means is multiplied by the first filter coefficient, and the output of the first tap and the multiplied output are added. Thus, an interpolation calculation method is characterized in that an interpolation calculation output is obtained.

With a two-tap filter, a filter coefficient is generated based on a combination of multi-order polynomials. For this reason, without lowering the accuracy of the interpolation calculation,
The interpolation operation can be performed with a small number of taps, so that the circuit scale and the number of processing steps can be reduced.

Further, a combination of multi-order polynomials having a gain of “1” and being point-symmetrical at a position of “0.5”, that is,
Assuming that the first filter coefficient is f ₁ (p) and the second filter coefficient is f ₂ (p), the filter coefficients are set so that f ₂ (p) = 1−f ₁ (p). Has been generated.
Therefore, one filter coefficient can be obtained by subtracting the other filter coefficient. As a result, real-time processing can be performed by an interpolation calculation at an arbitrary ratio.

[0039]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of an interpolation circuit to which the present invention is applied. In FIG. 1, digital video data is supplied to an input terminal 1. This digital video signal is supplied to a cascade connection of the delay circuits 2 and 3. The delay circuits 2 and 3 respectively have 1
This is to delay the sample. Delay circuits 2 and 3
Is supplied with a clock from the terminal 7. Two consecutive samples of pixel data are obtained from the outputs of the delay circuits 2 and 3.

The output of the delay circuit 2 is supplied to the multiplication circuit 4. The output of the delay circuit 3 is supplied to the multiplication circuit 5. Multipliers 4 and 5 are supplied with filter coefficients from a coefficient generator 6.

The phase information is supplied from a terminal 8 to the coefficient generating circuit 6. The coefficient generation circuit 6 generates coefficients for the multiplication circuits 4 and 5 based on the phase information. The coefficient at this time is obtained by combining multi-order polynomials, as described later. By using a combination of such multi-order polynomials, approximation can be performed with high accuracy even though the filter is a two-tap filter.

The coefficients obtained by the coefficient generation circuit 6 are supplied to the multiplication circuits 4 and 5. The multiplication circuits 4 and 5 multiply the outputs of the delay circuits 2 and 3 by the coefficient from the coefficient generation circuit 6. The outputs of the multiplication circuits 4 and 5 are supplied to the addition circuit 9. The output of the multiplication circuit 4 and the output of the multiplication circuit 5 are added by the addition circuit 9. The output of the adding circuit 9 is output from the output terminal 10.

In the interpolation circuit to which the present invention is applied, approximation is performed by the following combination of second-order polynomials.

When 0 ≦ | x |, f (x) = 1-2 | x | ^{2 When} 0.5 ≦ | x | ≦ 1, f (x) = 2 (1-2 | x |) ² When | x |> 1, f (x) = 0 Thus, this approximation expression is limited to the range of (−1 <x <1). For this reason, when this approximation formula is used as an interpolation function, a two-tap FI
Interpolation operation can be performed by the R filter.

FIG. 2 shows such an interpolation approximate expression. In FIG. 2, the horizontal axis indicates the value of x, and the vertical axis indicates the value of f (x). A1 shows an interpolation approximation formula as described above, A2 shows a cubic approximation formula, and A3 shows a bilinear approximation formula.

As described above, the linear approximation is performed in the bilinear approximation formula, whereas the interpolation approximation formula such as the above formula performs approximation using a quadratic formula. In the cubic approximation, the range of (−2 <x <2) is required, so that a 4-tap calculation process is required. However, in the interpolation approximation formula such as the above expression, (−1 <x <1) , Approximation can be performed with two taps.

As described above, by performing approximation using a combination of second-order polynomials as shown in the above equation, interpolation approximation can be accurately performed with a small number of taps.

That is, FIG. 3 shows frequency characteristics when a four-fold large interpolation filter is realized. In FIG. 3, B1 indicates the frequency characteristic of the interpolation filter by an approximate expression of a combination of second-order polynomials as in the above equation, B2 indicates the frequency characteristic of the interpolation filter by a cubic approximate expression, and B3 indicates the bilinear 9 shows a frequency characteristic of an interpolation filter based on an approximate expression.

As is clear from the frequency characteristics shown in FIG. 3, the interpolation filter based on the approximate expression of the combination of the quadratic polynomials as shown in the above equation is lower than the interpolation filter based on the bilinear approximation method. This is advantageous in the reproducibility of the signal in the above, and has a function of suppressing an extra high frequency signal component, so that characteristics closer to the cubic approximation method can be obtained.

By the way, in the similarity by combining two-dimensional polynomials as in the above equation, a quadratic equation must be calculated to obtain one filter coefficient, and two filter coefficients are required for one interpolation point. Therefore, many calculations are required to obtain the filter coefficients. For example,
In order to obtain one coefficient, at least one multiplication and one addition (subtraction) are required. Therefore, in order to obtain the coefficients of the two-tap interpolation filter, at least two multiplications and two additions (subtractions) are required, and it is desired to reduce the number of calculation processes.

In this example, as shown in FIG. 2, the characteristic is point-symmetric at the position "0.5". That is, when the first filter coefficient is f ₁ (p) and the second filter coefficient is f ₂ (p), the relationship is f ₂ (p) = 1−f ₁ (p). Therefore, when one filter coefficient is obtained, the other Fector coefficient is obtained by subtraction. This enables real-time processing.

In other words, it is now divided into two regions and expressed using the phase p (0 ≦ p <1).

(A) In the case of p (0 ≦ p <0.5) For −1 ≦ x <0.5, x = 1−p (0 ≦ p <
0.5) can be expressed as f ₁ (p) = 2p ² .

For 0 <x ≦ 0.5, p = x (0 ≦
As p <0.5), it can be expressed as f ₂ (p) = 1-2p ² .

Therefore, there is a relationship of f ₂ (p) = 1−f ₁ (p).

(B) When p (0 ≦ p <0.5) For −1 ≦ x <0.5, x = 1−p (0.5 ≦ p
As <1), it can be expressed as f ₁ (p) = 1-2 (1-p) ² .

For 0 <x ≦ 0.5, p = x (0.
As 5 ≦ p <1), it can be expressed as f ₂ (p) = 1-2 (1-p) ² .

Therefore, there is a relationship of f ₂ (p) = 1−f ₁ (p).

Thus, two coefficients f ₁ (p) and f ₂
All the relations with (p) can be expressed as f ₂ (p) = 1−f ₁ (p). This indicates that if _one coefficient f ₁ (p) is obtained, the other coefficient f ₂ (p) can be easily obtained by subtraction.

Accordingly, the coefficients can be obtained from these factors as shown in the flowchart of FIG.

In FIG. 4, when the phase p is input, it is determined whether or not this phase p is (0 ≦ p <0.5) (step S1). If the phase p is (0 ≦ p <0.5), one coefficient is obtained from (f ₁ (p) = 2p ² ) (step S2).

In step S1, the phase p is (0 ≦ p <0.
If not (5), (f ₁ (p) = 1-2 (1-
p) ² ), one coefficient is obtained (step S)
3). Since the double is obtained by bit shift, the multiplication process is unnecessary.

When one coefficient is obtained in step S1 or S2, the process proceeds to step S4, where the other coefficient is set to (f ₂
(P) = 1−f ₁ (p)) (step S
4).

As described above, in this example, the calculation amount for obtaining the coefficient is a maximum of three multiplications and four addition (subtraction) operations.
In other words, only one bit shift is required.

FIG. 5 shows another example of an interpolation operation circuit to which the present invention is applied. As described above, in this filter operation, when the outputs of the taps are Rb and Rc, an operation of Q = f ₁ (p) × Rb + f ₂ (p) × Rc is performed. Here, one coefficient f ₁ (p)
Relation mother, there is a _{f 2 (p) = 1-} f 1 (p) and f ₂ (p) and. Therefore, the above equation can be modified to Q = Rc + (Rc−Rb) f ₁ (p). The example shown in FIG. 5 performs processing based on the above equation.

In FIG. 5, digital video data is supplied to an input terminal 21. This digital video data is supplied to the cascade connection of the delay circuits 22 and 23.
The delay circuits 22 and 23 each delay one sample. The delay circuits 22 and 23 have terminals 29
Is supplied with a clock. From the delay circuits 22 and 23, pixel data of two consecutive samples are obtained.

The output of the delay circuit 22 is supplied to a subtraction circuit 24 and an addition circuit 25. Delay circuit 2
3 is supplied to the subtraction circuit 24. The output of the subtraction circuit 24 is supplied to the multiplication circuit 26. In the multiplication circuit 26,
A filter coefficient is supplied from the coefficient generation circuit 27.

The phase information is supplied from a terminal 28 to the coefficient generation circuit 27. The coefficient generation circuit 27 generates a coefficient for the multiplication circuit 26 based on the phase information.

The coefficients obtained by the coefficient generation circuit 27 are supplied to the multiplication circuit 26. The multiplication circuit 26 multiplies the output of the delay circuit 26 by a coefficient from the coefficient generation circuit 27. The output of the multiplication circuit 26 is supplied to the addition circuit 25. The output of the delay circuit 22 and the output of the multiplication circuit 26 are added by the addition circuit 25. The output of the addition circuit 25 is output from the output terminal 30.

FIG. 6 is a flowchart showing the processing of the coefficient generation circuit 27. In FIG. 6, when the phase p is input, it is determined whether or not the phase p satisfies (0 ≦ p <0.5) (step S11). If the phase p is (0 ≦ p <
If 0.5), one coefficient is obtained from (f ₁ (p) = 2p ² ) (step S12).

In step S1, the phase p is (0 ≦ p <0.
If it is not 5), from equation (6), (f ₁ (p) = 1−
2 (1-p) ² ), one coefficient is obtained (step S13).

As described above, in this example, the amount of calculation for obtaining the coefficient is a maximum, with two multiplications and four additions (subtractions).
In other words, only one bit shift is required.

As described above, in the interpolation circuit to which the present invention is applied, a filter coefficient is generated by the FIR filter based on a combination of polynomial expressions. For this reason, the interpolation operation can be performed with a small number of taps without lowering the accuracy of the interpolation operation, and the circuit scale and the number of processing steps can be reduced.

In the above-described example, the filter coefficient is obtained by a combination of second-order polynomials. However, this function is not limited to this. If the relationship between the two coefficients f ₁ (p) and f ₂ (p) satisfies f ₂ (p) = 1−f ₁ (p), the two coefficients can be obtained in real time. Such a function may be used. In other words, it suffices to combine two functions that are point-symmetric at a distance of 0.5.

[0075]

According to the present invention, a filter coefficient is generated by a two-tap filter based on a combination of multi-order polynomials. For this reason, the interpolation operation can be performed with a small number of taps without lowering the accuracy of the interpolation operation, and the circuit scale and the number of processing steps can be reduced.

According to the present invention, the gain is "1".
Where a combination of multi-order polynomials that are point-symmetric at the position of the phase “0.5”, that is, the first filter coefficient is f
_{When 1} (p) and the second filter coefficient are f ₂ (p), the filter coefficient is generated such that f ₂ (p) = 1−f ₁ (p).
Therefore, one filter coefficient can be obtained by subtracting the other filter coefficient. As a result, real-time processing can be performed by an interpolation calculation at an arbitrary ratio.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of an interpolation circuit to which the present invention is applied.

FIG. 2 is a graph used to explain an example of an interpolation circuit to which the present invention is applied;

FIG. 3 is a frequency characteristic diagram used to explain an example of an interpolation circuit to which the present invention is applied;

FIG. 4 is a flowchart used to describe an example of an interpolation circuit to which the present invention is applied;

FIG. 5 is a block diagram of another example of the interpolation circuit to which the present invention is applied;

FIG. 6 is a flowchart used to explain another example of the interpolation circuit to which the present invention is applied.

FIG. 7 is a schematic diagram used for describing interpolation calculation.

FIG. 8 is a graph used to explain a conventional interpolation circuit.

FIG. 9 is a graph used to explain a conventional interpolation circuit.

FIG. 10 is a block diagram of an example of a conventional interpolation circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Input terminal, 4, 5 ... Multiplication circuit, 6 ... Coefficient generation circuit, 9 ... Addition circuit

Claims (10)

[Claims] 1. An interpolation operation device for performing an interpolation operation by a convolution operation by multiplying outputs of first and second taps by first and second filter coefficients, and taking out outputs of the first and second taps. Cascaded delay means, and first and second multiplication means for multiplying the output of the first and second taps output from the delay means by the first and second filter coefficients, respectively. An adder for adding outputs of the first and second multipliers; and a coefficient generator for generating the first and second filter coefficients according to phase information, wherein the first and second filters are provided. The coefficient is generated by a combination of polynomials that are point-symmetric at a position where the gain is “1” and the phase is “0.5”, and an interpolation operation output is obtained from the addition means. . 2. The coefficient generation means, after obtaining the first filter coefficient f ₁ (p), calculates the second filter coefficient f ₂ (p) by f ₂ (p) = 1−f ₁ ( The interpolation arithmetic device according to claim 1, wherein the interpolation arithmetic device is obtained by the following calculation. 3. The interpolation operation apparatus according to claim 1, wherein the filter coefficients are based on a combination of second-order polynomials. 4. An interpolation device for performing an interpolation operation by a convolution operation by multiplying the outputs of the first and second taps by the first and second filter coefficients, for extracting outputs of the first and second taps. Cascaded delay means; subtraction means for subtracting the outputs of the first and second taps output from the delay means; multiplication means for multiplying the output of the subtraction means by the first filter coefficient; An adder that adds the first tap output and an output of the multiplier, and a coefficient generator that generates the first filter coefficient in accordance with phase information, wherein the first and second filter coefficients are And an interpolating device which is generated by a combination of polynomials which are point-symmetric at a position where the gain is "1" and the phase is "0.5", and wherein an interpolating operation output is obtained from the adding means. 5. The apparatus according to claim 4, wherein the filter coefficients are based on a combination of second-order polynomials. 6. An interpolation calculation method for performing an interpolation calculation by convolution by multiplying outputs of first and second taps by first and second filter coefficients, wherein the first and second filter coefficients are gains. Is generated by a combination of polynomials that are point symmetric at a position of “1” and a phase of “0.5”. The outputs of the first and second taps are extracted, and the first and second taps are extracted according to phase information. , And multiplies the outputs of the first and second taps by the first and second filter coefficients, respectively, and adds the outputs of the first and second multiplication means, and performs an interpolation operation. An interpolation calculation method characterized by obtaining an output. 7. When the first filter coefficient f ₁ (p) is obtained, the first and second filter coefficients are calculated using the second filter coefficient f ₁ (p).
7. The interpolation calculation method according to claim 6, wherein the filter coefficient f ₂ (p) is determined by an operation of f ₂ (p) = 1−f ₁ (p). 8. The interpolation calculation method according to claim 6, wherein said filter coefficients are based on a combination of second-order polynomials. 9. An interpolation operation device for performing interpolation by convolution by multiplying outputs of first and second taps by filter coefficients, wherein the first and second filter coefficients have a gain of “1” and a phase of Is generated by a combination of polynomials that are point-symmetric at a position of “0.5”, takes out the outputs of the first and second taps, subtracts the outputs of the first and second taps, and according to the phase information To generate the first filter coefficient, multiply the output of the subtraction means by the first filter coefficient, add the first tap output and the multiplied output, and obtain an interpolation operation output. An interpolation calculation method, characterized in that: 10. The interpolation calculation method according to claim 9, wherein said filter coefficients are based on a combination of second-order polynomials.