JP3106707B2 - Wide screen compatible imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus compatible with a television system having a wide screen.

[0002]

2. Description of the Related Art In recent years, widening of screens has been promoted, as in television systems such as HDTV (1125 scanning lines) and second-generation EDTV (525 (625 scanning lines)). Since the aspect ratio is changed from 4: 3 to 16: 9 in the related art, these video signal processing devices for HDTV and wide EDTV handle video signals having a wider band than the conventional one. Therefore,
Not only an image sensor and a display but also a signal processing circuit requires a dedicated circuit different from the video signal processing device of the standard television system. In particular, recently, digitalization of video signal processing circuits has progressed, and most of these circuits have been implemented as LSIs. Widening the screen increases the clock frequency of the circuit that performs digital processing of the video signal.
Arithmetic circuits such as adders and memories must be speeded up. In addition, the size of the memory must be increased as the memory becomes wider. Therefore, in order to digitally process a video signal in a video signal processing device having a wide screen,
A dedicated digital processing circuit or LSI must be developed in consideration of the speed of the arithmetic circuit and the memory size, which has a problem that the development cost increases.

In view of the above problems, when constructing a video signal processing device compatible with a television system with a wide screen, the circuit and the LSI of a conventional video signal processing device for a standard television are developed. In recent years, techniques for reducing costs and providing an inexpensive wide-screen video signal processing device have been proposed.

FIG. 12 is a block diagram showing one of the typical techniques, showing a configuration of a signal processing circuit in an image pickup apparatus compatible with a wide screen. The main features of this method are
By dividing a wide screen and performing processing in parallel, a conventional signal processing circuit such as an LSI is effectively used. In this example, the division is processed as two divisions.
In FIG. 12, 2 is an image sensor having a wide aspect ratio,
Reference numerals 22 and 23 denote time expansion circuits, reference numerals 24 and 25 denote video signal processing circuits, and reference numeral 26 denotes a time compression circuit. Hereinafter, FIGS. 13 to 1
4, a conventional wide-screen-capable imaging device will be described.

FIG. 13 is a block diagram illustrating the configuration and operation of the time expansion circuits 22 and 23, and FIG. 14 is a block diagram illustrating the configuration and operation of the time compression circuit 26.

The wide-screen image pickup device 2 picks up a wide-screen image, outputs a wide-band video signal, and inputs it to the time expansion circuits 22 and 23. The time expansion circuit 22 separates and expands the video signal of the left screen, and the time expansion circuit 23 separates and expands the video signal of the right screen to parallelize the video signals of the left screen and the right screen. You. The time expansion circuits 22 and 23 are composed of memories, and write the video signal data of only the left screen or the right screen into the memory based on the high-speed clock for sampling the wideband video signal W, and use the low-speed clock obtained by dividing the high-speed clock. By reading the memory, the video signals L and R obtained by separating the video signals of the left screen and the right screen, extending the time, and parallelizing them can be obtained.

The time expansion circuits 22 and 23 require 0.5H (H is one horizontal scanning time) for writing and 1H for reading as operations of the memory.
As shown in (a), the memory is composed of two memories, the memory B is read on the line where the memory A is being written, and the reverse operation is performed by switching SW1 and SW2 on the next line. The operation of the time expansion circuits 22 and 23 is shown in FIG.
(B).

The time-expanded video signals L and R are supplied to video signal processing circuits 24 and 25, and signal processing required for the image pickup apparatus, for example, gamma correction, color correction, horizontal and vertical aperture correction, matrix processing, etc. Is performed. Since the video signals L and R are time-expanded, the speed required for the video signal processing circuits 24 and 25 is reduced by half, and the size of the line memory used in the vertical aperture correction circuit is also reduced by half. Circuit and LS used in
I can be shared.

The video signals L 'and R' processed by the video signal processing circuits 24 and 25 are joined by a time compression circuit 26, time-compressed, converted into a wideband video signal, and output. The time compression circuit 26 can also be constituted by a memory,
The configuration is as shown in FIG. FIG.
In the memories L and R of (a), data of the video signals L 'and R' is written based on a low-speed clock. The data in the memory L is read by a high-speed clock in synchronization with the scanning timing of the left screen, and the data in the memory R is read by the high-speed clock in synchronization with the scanning timing of the right screen. The video signals L ", R" read from the memories L, R are switched to the left and right sides of the screen by the switch SW, and the video signals L ", R" are joined to obtain a wideband video signal W '. The memories L and R shown in FIG.
Is 1H for writing and 0.5H for reading
13A, and the memory A,
B, and write and read are switched for each line. FIG. 14 shows the operation of the memories L and R.
(B).

In the above description, the case where the processing speed is halved by dividing the screen into two is described. However, the number of divisions is arbitrary, and it depends on the bandwidth of the video signal of the wide screen and the processing speed of the video signal processing circuit. Then, the optimal number of divisions may be determined. For example, a desired process can be performed by dividing the image into two in a wide EDTV and three or more in an HDTV.

[0011]

However, in the above-described imaging apparatus for a wide screen having the conventional configuration as described above, even if an LSI or a signal processing circuit corresponding to the current system can be shared by dividing the image pickup apparatus, it is necessary to divide the image pickup apparatus. A memory for processing video signals in parallel and a memory for synthesizing based on the divided video signals are required. Further, when a circuit or an LSI for extracting an average value, a peak value, and the like of an image from image data of a video signal by digital processing and performing various controls of the imaging apparatus is used, the image data of the divided video signal is used. It is difficult to detect the average value, peak value, etc. of the image data separately.
However, there is a problem that the circuit scale and the development cost increase.

[0012] In view of the above, the present invention provides an image pickup apparatus compatible with a television system having a wide screen.
An object of the present invention is to provide a low-cost wide-screen imaging device by reducing the development cost by sharing a signal processing circuit and an LSI of a conventional imaging device for a standard television without increasing the circuit scale.

[0013]

In order to achieve this object, a wide-screen-capable imaging apparatus according to the present invention has a predetermined frequency f.
a wide-screen-capable image sensor that reads an image signal by ck, an AD converter that converts an output signal of the image sensor into a digital signal with a clock pulse having the same frequency as the read frequency fck of the image sensor, and an AD converter. The output signal is 1 / n of the read frequency fck of the image sensor.
(N is a positive integer) The frequency of the divided clock is 3
N clock pulses shifted by 60 ° / n
A dividing circuit for dividing, n digital signal processing circuits for performing digital signal processing with clock pulses corresponding to each output signal of the dividing circuit, and each output signal of the n digital signal processing circuits A wide-area circuit comprising: a synthesizing circuit that samples at the readout frequency fck of the image sensor according to the phase and synthesizes the signal at an fck rate; and a DA converter that converts an output signal of the synthesizer circuit into an analog signal at the readout frequency fck of the image sensor. This is a screen-capable imaging device.

Further, the wide-screen-capable imaging device of the present invention includes a wide-screen-capable image sensor for reading an image signal at a predetermined frequency fck, and an output signal of the image sensor for 1 / n of the read frequency fck of the image sensor. (N is a positive integer) A divided clock frequency and a phase of 360 ° /
n AD converters for converting into digital signals by n kinds of clock pulses shifted by n, and n digital signals to be subjected to digital signal processing by clock pulses corresponding to respective output signals of the n AD converters A processing circuit, a synthesizing circuit for sampling each output signal of the n digital signal processing circuits at a read frequency fck of the image sensor according to the phase of each output signal, and synthesizing them at an fck rate, and an output signal of the synthesizing circuit. Readout frequency fck of the image sensor
And a DA converter that converts the analog signal into an analog signal.

Further, the wide-screen compatible imaging apparatus of the present invention includes a wide-screen compatible image sensor for reading an image signal at a predetermined frequency fck, and an output signal of the image sensor having the same frequency as the read frequency fck of the image sensor. An AD converter that converts a digital signal with a clock pulse;
The output signal of the A / D converter is divided into n parts by n kinds of clock pulses whose clock frequency is 1 / n (n is a positive integer) divided by the readout frequency fck of the image sensor and whose phase is shifted by 360 ° / n. Dividing circuit, n digital signal processing circuits for performing digital signal processing with clock pulses corresponding to each output signal of the dividing circuit, and a phase of each output signal of the n digital signal processing circuits. A synthesizing circuit for sampling at the readout frequency fck of the image sensor and synthesizing it at an fck rate, a DA converter for converting an output signal of the synthesizer to an analog signal at the readout frequency fck of the image sensor, and the AD converter A thinning-out circuit for thinning out the output signal of the image signal by a predetermined clock fm; A widescreen image pickup apparatus having detected a data detection circuit for outputting data for various control data and the like.

[0016]

According to the present invention, the output signal of the image sensor corresponding to a wide screen is read out at a predetermined clock fck, and is converted into a digital signal by AD conversion at the clock of fck. Is a positive integer) The clock frequency is divided by n and the phase is shifted by 360 ° / n. This n
By processing the divided video signals in parallel with n digital signal processing circuits, the processing speed and bandwidth required by the digital signal processing circuits are reduced, and the conventional digital signal processing circuits for standard television system processing And LSI can be used. In addition, the n video signals processed by the digital signal processing circuit are sampled and synthesized by the synthesizing circuit using the fck clock according to the phase of each signal, and then DA converted to obtain a wide-screen wide-band video signal. it can.

Further, according to the present invention, a digital signal that has been A / D-converted by a clock of fck by a thinning circuit is converted to a predetermined clock fm.
The data detection circuit used for conventional standard television system processing and L
Enable SI.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a wide-screen-capable imaging apparatus according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an input terminal to which an optical image that has passed through a lens or the like is input, 2 denotes an image sensor that supports a wide screen (for example, an aspect ratio of 16: 9), and 3 denotes processing such as black level, white level, and pre-gamma. The analog processing circuit 4 is an AD converter for converting the output signal of the analog processing circuit 3 into a digital signal, and the division 5 is for converting the output signal of the AD converter 4 into a signal having an fck clock rate and an fck clock rate. Circuits, 6 and 7, digital signal processing LSIs for performing gamma correction, matrix processing, etc. on the output signals of the division circuit 5, respectively, and 8 synthesizes two digital signal processing LSI output signals of fe and fo clock rates into an fck clock rate signal. 9 is a DA converter for converting the output signal of the synthesizing circuit 8 into an analog signal, and 10 is fck,
A clock generating circuit for generating clock pulses fe and fo, and 11 is an output terminal.

The operation of the first embodiment of the present invention will be described below with reference to FIGS. FIG. 2 is a configuration diagram showing an example of the internal configuration of the clock generation circuit 10 and a timing chart thereof. FIGS.
FIG. 5 is a configuration diagram showing an example and a timing chart thereof.
FIG. 6 is a configuration diagram showing an example of the internal configuration of the synthesis circuit 8 and a timing chart thereof.

In FIG. 1, an optical image input from an input terminal 1 is formed on an image sensor 2 corresponding to a wide screen, and is output as an electric signal by predetermined vertical and horizontal read pulse driving (not shown). At this time, the horizontal read clock is used for the image pickup device of the current television system (aspect ratio 4: 4).
3) The read clock is faster than the read clock of 3).
fsc; fsc is the color subcarrier frequency), the read clock of the wide-screen compatible image sensor having the same resolution as this image sensor is approximately 19 MHz with an aspect ratio of 16: 9 (this clock frequency is fck). ).

The wide-band image signal read out by the high-speed clock fck is subjected to black level adjustment by black balance and the like, white level adjustment by white balance and the like, and further, to a knee processing by the analog processing circuit 3. Thereafter, this analog signal is converted to a subsequent AD signal in order to perform digital processing which is excellent in accuracy, control, and characteristics.
The signal is converted into a digital signal by the converter 4. In this embodiment, this AD conversion is performed by a high-speed clock fck. The output signal of the AD converter 4 is input to the dividing circuit 5. In the division circuit 5, the clock generation circuit 1
0 and low speed clocks fe and fo output from fe
The signal is divided into a signal of the rate and a signal of the fo rate and output. In the case of the present embodiment, the clocks of fck, fe, and fo are generated by a phase obtained by dividing the frequency of fck by よ り from the flip-flop 12, as shown in an example of the internal configuration of the clock generation circuit 10 in FIG. Clocks that differ by 180 ° are fe and fo. In other words, the frequency is about 9M
Hz signals. Therefore, the processing speed is sufficiently compatible with circuits, LSIs, and the like having a signal processing speed of the conventional television system.

The dividing operation of the dividing circuit 5 will be described below with reference to FIGS. The internal configuration of the dividing circuit 5 is, for example, as shown in FIG. In FIG. 3, reference numerals 13 and 14 denote 8-bit delay flip-flops (here, the AD converter 4 is described as an 8-bit AD converter).
The 8-bit output signal of the AD converter 4 at the fck rate is input to both the delay flip-flops 13 and 14. Clock f output from clock generation circuit 10
e is input to the delay flip-flop 13 and the clock fo is input to the delay flip-flop 14. Therefore, as shown in the timing chart of FIG.
The signals at the fck rates of 0, D1, D2, D3,... Are divided into two systems: a signal sequence of D0, D2,. Is done.

The divided two signals are input to a digital signal processing LSI 6 and a digital signal processing LSI 7, respectively, and subjected to various digital processings such as gamma correction, blanking processing, and matrix processing. The operations of the digital signal processing LSI 6 and the digital signal processing LSI 7 are completely the same, except that the phases of the processing are different by 180 °.
Here, as described above, the clock is about 9 MHz,
Since it can sufficiently cope with the processing speed of the conventional television system, there is no problem in its operation. The output signals of the digital signal processing LSI 6 and the digital signal processing LSI 7 are combined into a signal of the fck rate by the combining circuit 8 and restored to the original wideband wide screen signal.

The combining operation of the combining circuit 8 will be described below with reference to FIGS. The internal configuration of the synthesis circuit 8 is, for example, as shown in FIG. In FIG. 5, 15 is an 8-bit multiplexer that switches and outputs two systems of input signals.
Reference numeral 16 denotes a delay flip-flop. The multiplexer 15 selects and outputs the I0 input when the S input is low (0) and the I1 input when the S input is high (1). The clock fo is input to this S input. Further, fck is input to the clock input of the delay flip-flop 16. Therefore, as can be seen from the timing chart of FIG.
o, the multiplexer 15 outputs the output signal d of the digital signal processing LSI 6 when the S input is low.
, And output signals d1, d3,... Of the digital signal processing LSI 7 when the S input is high. The output signal is held in the delay flip-flop 16 by the clock fck, and the data is stored in d0, d1, d.
, D3,... Are synthesized.
The digital signal synthesized by the synthesizing circuit 8 is converted into an analog signal by a DA converter 9, and a wide-screen wide-screen imaging signal is obtained from an output terminal 11.

As described above, according to the first embodiment of the present invention, a memory is not required for dividing and synthesizing an image signal of a wide screen, and a simple data holding circuit, a multiplexer circuit, and the like, which are good at digital circuits, are used. It can be configured, and the circuit scale can be significantly reduced. This is an important difference from the conventional example.

It is needless to say that the function of the dividing circuit 5 may be provided to each of the first-stage delay flip-flops in the digital signal processing LSI 6 and the digital signal processing LSI 7.

Next, a wide-screen image pickup apparatus according to a second embodiment of the present invention will be described with reference to FIG. 7, reference numeral 1 denotes an input terminal to which an optical image passed through a lens or the like is input, and 2 denotes a wide screen (for example, an aspect ratio of 16:
9) An image sensor, 3 is an analog process circuit for performing processes such as black level, white level, and pre-gamma, and 17, 18
Is an AD converter that converts an output signal of the analog process circuit 3 into a digital signal at fe and fo clock rates;
Reference numeral 7 denotes a digital signal processing LS for performing gamma correction, matrix processing, and the like on output signals of the AD converters 17 and 18, respectively.
I and 8 are synthesizing circuits for synthesizing two digital signal processing LSI output signals of fe and fo clock rates into an fck clock rate signal, 9 is a DA converter for converting the output signal of the synthesizing circuit 8 into an analog signal, and 10 is fck , Fe, fo
And a clock generation circuit 11 for generating the clock pulse.

The present embodiment differs from the first embodiment in that the dividing circuit 5 is omitted and two AD converters are provided. The other circuits are completely the same, and therefore have the same operation and operation, and the description of the operation will be omitted.

The advantages of this embodiment are that the dividing circuit can be omitted, and that the AD converters 17 and 18 have fe and fo (approximately 9 MHz) obtained by dividing the frequency of fck (approximately 19 MHz) by half.
Since the operation is performed in z), a high-speed A / D converter is not required, and it is possible to cope with a higher read clock of a wide-screen image pickup signal.

Next, wide-screen image pickup apparatuses according to third and fourth embodiments of the present invention will be described with reference to FIGS. 8 and 9, reference numeral 1 denotes an input terminal to which an optical image passed through a lens or the like is input, 2 denotes an image pickup device compatible with a wide screen (for example, an aspect ratio of 16: 9), 3 denotes a black level, a white level, a pre-gamma, and the like. 4 is an AD converter that converts the output signal of the analog process circuit 3 into a digital signal, and 5 is the fck of the AD converter 4.
Dividing circuits for converting clock rate output signals into signals of fe and fo clock rates, digital signal processing LSIs 6 and 7 for performing gamma correction, matrix processing, and the like on output signals of the dividing circuit 5, respectively, and 8 for fe and fo clock rates 9 is a synthesizing circuit for synthesizing the two digital signal processing LSI output signals into the fck clock rate signal, 9 is a DA converter for converting the output signal of the synthesizing circuit 8 into an analog signal, and 10 is a clock pulse for fck, fe and fo. A clock generating circuit 11 is an output terminal. 19 is AD
A thinning circuit for appropriately thinning out the output signal of the converter 4, a data detection LSI 20 for detecting an average value, a peak value, and the like of the imaging screen from the output signal of the thinning circuit 19, and 21 for fck, f
This is a clock generation circuit that generates a clock fm for thinning out the thinning-out circuit 19 in addition to the clock generation of e and fo.

The operation of the third and fourth embodiments will be described below. The difference between the third embodiment shown in FIG. 8 and the fourth embodiment shown in FIG. 9 is that the third embodiment shown in FIG. In the fourth embodiment shown in FIG. 9, a digital signal processing LSI 20 is used as an input signal of the data detection LSI 20.
The point is that it is obtained from one output signal of the same dividing circuit 5 as the input signal to I7. Also, the third and fourth of FIGS.
Is very different from the first and second embodiments shown in FIGS. 1 and 7 in that a data detection LSI is provided, and the other division operations and synthesis operations are completely the same. The description of the operation is omitted.

In FIG. 8, the thinning circuit 19 is constituted by, for example, a delay flip-flop.
By holding the high-speed output signal of the AD converter 4 at the fck rate with the clock fm, the signal of the fm rate can be thinned out. By setting this clock fm to an appropriate value, the processing speed is reduced, and a data detection LSI compatible with a conventional television system or a smaller L
The SI can be made available. In addition, FIG.
In this embodiment, the thinning operation is also performed by the operation of the dividing circuit 5, and the thinning circuit can be omitted.

According to the third and fourth embodiments of the present invention, detection of an average value, a peak value, and the like of an imaged screen, which has been difficult by a method in which a conventional screen is divided into, for example, left and right, is difficult. It can be easily performed by a conventional data detection LSI or the like compatible with the television system.

Further, even if the data is thinned out, the accuracy of detection of the average value, peak value, etc. of the imaged image is reduced to 1/2 or 1/4 as in the fourth embodiment shown in FIG. If there is, it will be understood from the following description that there is no problem.

In order to obtain an average value, a peak value and the like of a screen in an image pickup apparatus or the like, for example, the image pickup screen shown in FIG.
As shown in (5), the block is divided into 48 (horizontal) × 15 (vertical) = 720 blocks, and the average value of the image data of each block is obtained. The peak value of the screen is the maximum value among them, and the average value of the entire screen is obtained by adding the average value of the image data of each block and dividing by 720. Further, as shown in FIG. 10B, one block depends on the number of pixels of the image sensor, but for example, 16 pixels × 16 pixels
The line is composed of 256 pixel data.

Here, as in the fourth embodiment, the data is divided by 1 /
Consider the case of thinning to 2. For example, the input data is as shown in FIG. In this case, only 32 pixels in one line are shown. However, if no thinning is performed, the average value 1 lava for one line in the area 1 and the area 2 is 1 lav = 1200/16 = 75 and 1 lav = 12, respectively.
80/16 = 80. Averaging region 1 and region 2 results in 77.5. Also, when thinning is performed, when pixels are selected as 1, 3, 5,..., The average value 1lavm1 for one line is as follows: 1lavm1 = 1200/16 = 75 2, 4, 6,. In the case of selection, the average value 1lavm2 for one line is 1lavm2 = 1280/16 = 80. Therefore, a slight error occurs irrespective of how the pixel is selected. In the case of high-frequency image data, the error is considered to be large. However, the captured image data has such a characteristic that there is a large correlation with neighboring pixels and the energy of the high-frequency component is small. Considering, for example, averaging 720/2 = 360 blocks, there is almost no error.

As described above, the third and fourth embodiments of the present invention
According to the embodiment, it is possible to use a conventional data detection LSI for a television system or a smaller LSI without developing a high-speed data detection LSI for a wide screen.

In the case of the fourth embodiment shown in FIG. 9, it goes without saying that an LSI in which the data detection LSI 20 is incorporated in the digital signal processing LSI 7 may be used. In each embodiment, it goes without saying that a digital signal processing LSI capable of supporting a wide screen may be arranged behind the synthesizing circuit 8. It goes without saying that the clock and the number of divisions for the division circuit 5 may be other appropriate division ratios and division numbers (for example, 1/4 division, 4 divisions) other than 1/2 division of fck.

In each of the embodiments, the digital signal processing section uses an LSI. However, it is needless to say that a discrete circuit not formed into an LSI may be used.

[0041]

As described above, according to the present invention, in configuring an image pickup apparatus compatible with a television system having a wide screen, division and synthesis of a wide screen image pickup signal without using a memory or the like. Since the processing can be performed, the signal processing circuit and the L of the conventional imaging device for a standard television can be used without increasing the circuit scale.
An SI (LSI for digital signal processing itself, LSI for data detection, etc.) can be used in common, and an imaging device that can reduce development costs and is inexpensive for a wide screen can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a wide-screen-capable imaging device according to a first embodiment of the present invention.

FIG. 2 is a clock generation circuit 10 according to the first embodiment;
Block diagram showing an example of the internal configuration of the device and its timing chart

FIG. 3 is a block diagram showing an example of an internal configuration of a dividing circuit 5 in the first embodiment.

FIG. 4 is a timing chart showing the operation of the dividing circuit 5 in FIG. 3;

FIG. 5 is a block diagram showing an example of an internal configuration of a synthesis circuit 8 according to the first embodiment.

FIG. 6 is a timing chart showing the operation of the synthesis circuit 8 in FIG. 5;

FIG. 7 is a block diagram illustrating a configuration of a wide-screen-capable imaging device according to a second embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a wide-screen-capable imaging device according to a third embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a wide-screen-capable imaging device according to a fourth embodiment of the present invention.

FIG. 10 is an explanatory diagram showing an example of screen division for detecting image data in the third and fourth embodiments.

FIG. 11 is an explanatory diagram for calculating an average value of screen division blocks in the third and fourth embodiments.

FIG. 12 is a block diagram illustrating a configuration of a signal processing circuit of a conventional wide-screen compatible imaging device.

FIG. 13 is an explanatory diagram of the configuration and operation of the time expansion circuits 22 and 23 in FIG.

14 is a diagram illustrating the configuration and operation of a time compression circuit 26 in FIG.

[Explanation of symbols]

 Reference Signs List 3 analog process circuit 4, 17, 18 AD converter 5 division circuit 6 digital signal processing LSI 7 digital signal processing LSI 8 synthesis circuit 9 DA converter 10, 21 clock generation circuit 19 thinning circuit 20 data detection LSI

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N ^5/ 14-5/253 H04N 5/335 H04N ^7/ 00-7/015

Claims (3)

(57) [Claims] 1. An image sensor for reading an image signal at a predetermined frequency fck, and an AD converter for converting an output signal of the image sensor into a digital signal with a clock pulse having the same frequency as the read frequency fck of the image sensor. And n types of clock pulses whose output signals from the AD converter are divided by a clock frequency of 1 / n (n is a positive integer) of the readout frequency fck of the image sensor and whose phases are shifted by 360 ° / n each A divided circuit that divides the output signal of the divided digital circuit by n, a digital signal processing circuit that performs digital signal processing with a clock pulse corresponding to each output signal of the divided circuit, The read frequency fck of the image sensor according to the phase of the signal
A wide-screen-compatible imaging device, comprising: a synthesis circuit for sampling at a rate of fck and synthesizing to an fck rate; and a DA converter for converting an output signal of the synthesis circuit to an analog signal at a read frequency fck of the imaging device. 2. A wide-screen image sensor for reading an image signal at a predetermined frequency fck, and an output signal of the image sensor divided by 1 / n (n is a positive integer) of a read frequency fck of the image sensor. N AD converters for converting into digital signals by n kinds of clock pulses having a clock frequency and a phase shifted by 360 ° / n, and a digital signal using clock pulses corresponding to each output signal of the n AD converters N digital signal processing circuits for performing signal processing; and readout frequency fck of the image sensor according to the phase of each output signal of each of the output signals of the n digital signal processing circuits.
A wide-screen-compatible imaging device, comprising: a synthesis circuit for sampling at a rate of fck and synthesizing to an fck rate; and a DA converter for converting an output signal of the synthesis circuit to an analog signal at a read frequency fck of the imaging device. 3. A wide-screen image sensor for reading an image signal at a predetermined frequency fck, and AD conversion for converting an output signal of the image sensor into a digital signal with a clock pulse having the same frequency as the read frequency fck of the image sensor. And n types of clock pulses whose output signals from the AD converter are divided by a clock frequency of 1 / n (n is a positive integer) of the readout frequency fck of the image sensor and whose phases are shifted by 360 ° / n each A divided circuit that divides the output signal of the divided digital circuit by n, a digital signal processing circuit that performs digital signal processing with a clock pulse corresponding to each output signal of the divided circuit, The read frequency fck of the image sensor according to the phase of the signal
A synthesizing circuit for sampling at a fck rate, a DA converter for converting an output signal of the synthesizing circuit into an analog signal at a read frequency fck of the image sensor, and a data for converting an output signal of the AD converter at a predetermined clock fm. A wide-screen imaging device, comprising: a thinning circuit that thins out the data; and a data detection circuit that detects data such as an average value and a peak value of the imaging signal based on the data of the thinning circuit and outputs various control data. apparatus.