JP3681465B2 - Prompter video signal processor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a video signal processing device for a prompter, and more particularly to signal processing when a manuscript read by a news caster or the like is displayed on a display device during photographing by a television camera or the like.
[0002]
[Prior art]
In broadcasting by a TV camera, etc., a prompter device is used in which a display device is arranged near the front side of the TV camera. This prompter device displays various manuscripts that can be read by newscasters, presenters, performers, etc. Can do. In this type of apparatus, the image signal processing apparatus performs processing for capturing image data of a document in an image memory and displaying the image data on a display.
[0003]
That is, the document is taken by the document camera, and the video signal supplied from the document camera is temporarily stored in the image memory. In addition, a sub-carrier transmitted simultaneously with the video signal is separated, and a write and read clock signal is formed based on this sub-carrier. By writing and reading image data to and from the image memory by this clock signal, The original image is displayed on the display. Then, this manuscript can be scrolled up and down, left and right, or sent page by page, so that a newscaster or the like can read the manuscript.
[0004]
[Problems to be solved by the invention]
However, in the conventional prompter video signal processing apparatus, because the NTSC system employs a four-field sequence, there is a phase shift in the subcarrier used for each field, and the screen shifts due to this phase shift. There was a problem that it was difficult to see.
[0005]
FIG. 8 shows the waveforms of the subcarrier and the clock signal. Generally, as the clock frequency, frequencies such as 4 fsc, 2 fsc, and fsc synchronized with the subcarrier (frequency fsc) are used. The above problem will be described in the case of fsc. That is, in the 4-field sequence, as shown in FIGS. 8A to 8D, the subcarrier has the same phase in the fields of 1ODD and 4EVEN, and the same phase in 2EVEN and 3ODD, but 1ODD and 2EVEN or 3ODD. And 4EVEN, there is a 180 degree phase shift between them. Such a phase shift is called frequency interleaving, and this frequency interleaving is performed so that the color subcarrier of the color video does not affect the screen of the black and white video (the screen is not a vertical stripe but a checkered pattern). To be done.
[0006]
The subcarriers form 1 ODD and 4 EVEN field clock signal 1 as shown in FIG. (E), and 2 EVEN and 3 ODD field clock signal 2 as shown in FIG. (G). The clock signals 1 and 2 are also rectangular waves having a phase difference of 180 degrees. Therefore, the display position of the readout field data in FIG. (F) and the readout field data in FIG. (H) are shifted by half of one pixel.
[0007]
FIG. 9 shows the storage state of data in the image memory M. For example, assuming that black and white data as shown in the figure is stored as part of the original character, 10 (I) and 10 (II). That is, the image memory M stores black data at addresses 22, 32, and 42, and this data is read out as both odd and even field data.
[0008]
Accordingly, as shown in the screen S of FIG. 1I, for example, black (hatched portion) pixels of lines 22, 23, and 24 in the 1ODD field and black pixels of lines 285, 286, and 287 in the 2EVEN field. And are displayed offset by half the amount. Further, as shown in the screen S of FIG. (II), the display position is shifted by half the amount of black pixels in the 3ODD field and black pixels in the 4EVEN field. Moreover, there is a difference of half in the odd fields and even fields.
[0009]
Here, paying attention to the pixel data at the position P on the screen S in FIG. 10, only the pixels in the 4EVEN field are black among the 4 fields, and as shown in FIG. 11, every 1/60 seconds on the screen. In addition, no-signal, white, no-signal, and black colors are repeatedly displayed. Therefore, the presence of such a portion makes it difficult to see the line of the character and makes it particularly noticeable in fine characters.
[0010]
The present invention has been made in view of the above problems, and its purpose is to provide a video signal for a prompter that can improve the visibility of an image when using a clock frequency synchronized with a subcarrier of a four-field sequence. It is to provide a processing apparatus.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a video signal processing apparatus for a prompter that forms a clock signal synchronized with a subcarrier for a four-field sequence and performs document display processing using this clock signal. Provided is a timing signal generation circuit that inputs a carrier wave and forms a clock signal of the same phase that eliminates the phase shift of the sub-carrier wave. All the image data of four fields are received by the clock signal of the same phase from the timing signal generation circuit. Processed and displayed.
[0012]
According to the configuration of the action <br/> above, in the clock signal formed by a timing signal generating circuit, a phase shift present on the sub-carrier is removed, an image with all of the data are the same-phase clock signals of four fields It will be read from memory. Therefore, unlike the conventional case, when the half of the pixel is shifted, no signal, white, no signal, and black are not repeatedly displayed in this order, so that the state of the screen is eliminated.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows an overall configuration of a video signal processing device for a prompter as an example of an embodiment. In the figure, a video input terminal 10 is connected to a video output terminal of a document camera, and a document image photographed by the document camera is supplied from the input terminal 10. The video input terminal 10 is connected to an image memory 12 such as an SRAM via an A / D converter 11, and the image memory 12 can store several tens of original images. In addition, a video amplifier 14 is connected to the image memory 12 via a D / A converter 13, and a video output terminal 15 is connected to the video amplifier 14.
[0014]
On the other hand, a video signal is inputted from the video input terminal 10 and a sync separation circuit 17 for separating subcarriers (subcarriers), and various timing signals (clock signals) are obtained from the subcarriers obtained by the sync separation circuit 17. A timing generator (timing signal generation circuit) 18 to be formed is provided, and this clock signal is supplied to the image memory 12 and other circuits. Further, a CPU 19 that supervises control, an address decoder 20 that selects an address designated by the CPU 19, and the like are provided, and an operation unit 21 that performs vertical and horizontal scroll operations, page feed operations, and the like is connected to the CPU 19. Arranged.
[0015]
FIG. 2 shows a detailed circuit for forming a clock signal from subcarriers in the timing generator 18 described above. In this circuit, an inverter 24 is included to input a sine wave subcarrier (SC) and convert it into a rectangular wave, a waveform conversion circuit 25, an inverter 26 that inverts and outputs the input from the waveform conversion circuit 25, A three-state buffer 27 for selecting the output of the inverter 26 and a three-state buffer 28 for selecting the output of the waveform conversion circuit 25 are provided. A delay circuit 29 and a flip-flop circuit 30 are provided to turn on any of the three-state buffers 27 and 28. The flip-flop circuit 30 is input to the D terminal. It operates by the output of the delay circuit 29.
[0016]
The embodiment is configured as described above, and the operation thereof will be described with reference to FIGS. First, when the writing mode is selected by an operation button or the like, the video signal (composite signal) shown in FIG. 3A photographed by the document camera is input from the video input terminal 10 in FIG. The image signal data is sent to the image memory 12 via the A / D converter 11. At the same time, in the sync separation circuit 17 of FIG. 1, the subcarrier (SC) is separated from the video signal, and this subcarrier is supplied to the timing generator 18. In the timing generator 18, the write operation is performed by the circuit of FIG. And a clock signal for reading is formed.
[0017]
FIG. 4 shows signal waveforms formed in each part of the circuit of FIG. 2, and the input of the waveform conversion circuit 25 of FIG. 2 is shown by (A) in FIGS. 4 [I] and [II]. A sine wave subcarrier (SC) is supplied. As described in FIG. 6, this subcarrier is divided into two types having a 180-degree phase difference between the 1ODD and 4EVEN fields in FIG. [I] and the 2EVEN and 3ODD fields in FIG. Signal. It is assumed that the starting point T1 in the figure coincides with the rising point T1 of the synchronizing signal (inverted state) in FIG.
[0018]
First, the fields 1ODD and 4EVEN in FIG. 4I will be described. The subcarriers in FIG. 4A are converted into rectangular wave signals (inverted signals) shown in FIG. . The rectangular wave signal of FIG. (B) is inverted by the inverter 26 which takes High only when it is Low, and the rectangular wave signal of FIG. (C) is formed. The rectangular wave signal shown in FIG. (C) is delayed by a predetermined amount in the delay circuit 29 and is supplied to the D terminal of the flip-flop circuit 30 as a signal shown in FIG.
[0019]
In the flip-flop circuit 30, when the D terminal input is in the low state as shown in FIG. 4D at the rising edge (T1) of the synchronizing signal (inverted state) applied to the CK terminal, the Q terminal becomes low, Q Since the bar terminal becomes High, the three-state buffer 27 is turned on (the three-state buffer 28 is turned off). Accordingly, the three-state buffer 27 outputs the rectangular wave signal shown in FIG. 4C as a clock signal, as shown in FIG.
[0020]
On the other hand, the subcarriers of FIG. 4A in the 2EVEN and 3ODD fields of FIG. 4 [II] are converted into the rectangular wave signal shown in FIG. 4B by the waveform conversion circuit 25, and the case of FIG. In comparison, the signal is 180 degrees out of phase. The rectangular wave signal of FIG. (B) is inverted by the inverter 26 to be the rectangular wave signal of FIG. (C) as in the case of FIG. [I], and the rectangular wave signal of FIG. The circuit 29 is delayed by a predetermined amount.
[0021]
In the flip-flop circuit 30, since the D terminal input is in the high state as shown in FIG. 4D when the synchronizing signal applied to the CK terminal rises (T1), the Q terminal is high and the Q bar terminal is high. Becomes Low. Accordingly, the three-state buffer 28 is turned on (the three-state buffer 27 is turned off), and in this case, as shown in FIG. 5E, the rectangular wave signal in FIG.
[0022]
In this way, clock signals having the same phase are formed even when the subcarriers are out of phase, as indicated by the clock signals (E) in FIGS. 4 [I] and [II]. This clock signal is used as a clock signal for writing from the starting point T2 of the substantial image signal of the video signal in FIG. 3, and thereby the video signal is stored at a predetermined address in the image memory 12.
[0023]
In the image reading process, the clock signal shown in FIG. (E) is used, and image data is sequentially read from the image memory 12 by this clock signal. This image data is supplied to the video amplifier 14 via the D / A converter 13, and after being subjected to predetermined amplification, it is supplied from the video output terminal 15 to the prompter display unit. The original text is displayed as an image.
[0024]
FIG. 5 shows the display state of the original image processed by the clock signal of the above embodiment, which corresponds to the memory state shown in FIG. That is, in this example, the clock signals having the same phase shown in FIG. 5E are used for all the fields from 1ODD to 4EVEN, so that the lines 22, 23, 24 and 285, 286, 287 are used as shown in FIG. The black pixel display (shaded portion) of the line is aligned vertically without shifting by half a pixel in all four fields. Therefore, it is possible to display the character lines in a clear state without any disturbance of the image.
[0025]
FIGS. 6 and 7 show processing for diagonal lines of characters. For example, as shown in FIG. 6, monochrome data is stored in the image memory 12 as part of the diagonal lines. To do. Also in this case, since processing is performed with clock signals having the same phase in both the odd and even fields, as shown in FIG. 7, the black pixels are displayed in an obliquely aligned state. Therefore, a good display state can be obtained even for the diagonal lines.
[0026]
【The invention's effect】
As described above, according to the present invention, in the prompter video signal processing apparatus for forming a clock signal with subcarriers for a four-field sequence, the phase shift of the subcarriers is eliminated by the timing signal generation circuit. A phase clock signal is formed, and all image data in four fields are read and processed by this clock signal. Therefore, in the NTSC four-field sequence, the state that becomes prominent in fine characters and the like is improved, and an easy-to-read original image is obtained. It is possible to display.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing an overall configuration of a video signal processing apparatus for a prompter according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing an internal configuration of the timing generator of FIG. 1;
FIG. 3 is a waveform diagram showing a video signal and a synchronization signal processed by the circuit of FIG. 1;
FIG. 4 is a waveform diagram showing signals obtained by each part of the timing generator of FIG. 2;
FIG. 5 is an explanatory diagram showing a display state of a screen of the prompter device in the embodiment.
FIG. 6 is an explanatory diagram showing a storage state of diagonal lines of characters stored in an image memory.
7 is an explanatory diagram showing a display state of a screen when the oblique line in FIG. 6 is processed.
FIG. 8 is a waveform diagram showing signals used in a video signal processing device of a conventional prompter.
FIG. 9 is an explanatory diagram illustrating an example of a storage state of characters stored in an image memory.
FIG. 10 is an explanatory diagram showing a display state of a screen of a conventional prompter device.
11 is an explanatory diagram showing a display time of a color displayed by one pixel on the screen of FIG.
[Explanation of symbols]
12 ... Image memory,
17 ... Sync separation circuit,
18 ... Timing generator,
19 ... CPU,
25 ... Waveform conversion circuit,
27, 28 ... three-state buffer,
29 ... Delay circuit,
30 ... flip-flop circuit,
S: Screen.

Claims (1)

In a video signal processing apparatus of a prompter that forms a clock signal synchronized with a subcarrier for a four-field sequence and performs document display processing using this clock signal.
Provided with a timing signal generation circuit that inputs the subcarrier and forms a clock signal of the same phase that eliminates the phase shift of the subcarrier,
A video signal processing apparatus for a prompter, which processes and displays all image data of four fields by a clock signal having the same phase from the timing signal generation circuit.

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