JPS59181789A - Television signal processing system - Google Patents

Television signal processing system

Info

Publication number
JPS59181789A
JPS59181789A JP58242032A JP24203283A JPS59181789A JP S59181789 A JPS59181789 A JP S59181789A JP 58242032 A JP58242032 A JP 58242032A JP 24203283 A JP24203283 A JP 24203283A JP S59181789 A JPS59181789 A JP S59181789A
Authority
JP
Japan
Prior art keywords
signal
television signal
television
scanning
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58242032A
Other languages
Japanese (ja)
Other versions
JPS6262115B2 (en
Inventor
Kazumasa Matsui
松井 一征
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Hitachi Ltd
Original Assignee
Hitachi Denshi KK
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK, Hitachi Ltd filed Critical Hitachi Denshi KK
Priority to JP58242032A priority Critical patent/JPS59181789A/en
Publication of JPS59181789A publication Critical patent/JPS59181789A/en
Publication of JPS6262115B2 publication Critical patent/JPS6262115B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00Television systems
    • H04N7/01Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level

Abstract

PURPOSE:To obtain a television signal which generates no flicker by obtaining a signal of a line sequential scanning by an image pickup device, converting it to a television signal of an interlaced scanning by using a storing circuit, transmitting it, converting it to a signal of a line sequential scanning of a frame frequency of (n) times of a frame frequency in an image receiving side, and reproducing a picture. CONSTITUTION:Both of buffer storing circuits 213, 215 are storing circuits which have a storage capacity of a picture element of half of one scanning line, and can set independently a speed of write and a speed of read-out, and constituted of a semiconductor random access storage integrated circuit, a magnetic core random access storage device, etc. A television signal 201 and 204 are read to the center of a scanning line in a 0.5 scanning line buffer storing circuit 213 and 215, respectively, read out at a speed of two times to an output 213' and 215', respectively, and when the output 213' and 215' are switched and outputted alternately by a half period of a horizontal period by using a switching circuit 224, a converted television signal 225 which sets one field as one new frame and does not execute an interlaced scanning is obtained as shown by a waveform 225.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、テレビ信号処理方式、更に詳しく言えば、テ
レビ信号を眼が疲労しないより良い画質の得られるテレ
ビ信号に変換する信号処理方式に関するものである。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a television signal processing system, and more specifically, to a signal processing system for converting a television signal into a television signal that provides better image quality without causing eye fatigue. It is.

〔発明の背景〕[Background of the invention]

現行の標準テレビ方式においては、所要周波数帯域を減
らすために飛越走査を採用している。そのため、画面の
垂直に急激に変化する部分にちらつきを感じてしまう。
Current standard television systems employ interlaced scanning to reduce the required frequency band. As a result, flickering appears in parts of the screen that change rapidly vertically.

第1図を用いてちらつきの生じる理由を説明する。第1
図において、第1フイルドの走査線群1が順次走査され
、次に、走査線群1の中間に存在する第2フイルドの走
査線群2が順次走査され、また第1フイルドの走査線群
1が走査されるというように走査が行なわれる。したが
って、画面が垂直方向に急激に変化している場合、たと
えば図1に示すように上が黒で下が白へ急激に変化して
いる場合には、第1フイルドの黒から白への変化3と第
2フイルドの黒から白への変化4の場所が1走査線間隔
だけずれてしまう。したがって、白黒の変化の場所がフ
レーム周期で上下することになりこれが、画面の垂直に
急激に変化する部分でちらつきを感じさせる。
The reason why flickering occurs will be explained using FIG. 1st
In the figure, the scanning line group 1 of the first field is sequentially scanned, then the scanning line group 2 of the second field located in the middle of the scanning line group 1 is sequentially scanned, and the scanning line group 1 of the first field is sequentially scanned. is scanned, and so on. Therefore, if the screen changes suddenly in the vertical direction, for example from black at the top to white at the bottom, as shown in Figure 1, the change from black to white in the first field 3 and the location of the change from black to white in the second field 4 are shifted by one scanning line interval. Therefore, the location of the change in black and white moves up and down with the frame period, which causes a flicker to appear in areas of the screen where there is a sudden vertical change.

上記のちらつきは、通常の画面ではあまり気にならない
けれども、多くの水平線が規則的lこ並んだり、水平に
近い線が一点に集中する画面では、非常に気になる。ま
た、長時間テレビ画像を観視する場合の眼の疲労の原因
となる。
The above-mentioned flicker does not bother you much on a normal screen, but it becomes very noticeable on a screen where many horizontal lines are arranged regularly or near-horizontal lines are concentrated at one point. It also causes eye fatigue when viewing television images for a long time.

〔発明の目的〕[Purpose of the invention]

したがって、本発明の目的は、飛越走査を採用している
テレビ信号から、ちらつきを生じないテレビ信号を得る
テレビ信号処理方式を実現することである。
Therefore, an object of the present invention is to realize a television signal processing method for obtaining a flickering-free television signal from a television signal employing interlaced scanning.

〔発明の概要〕 本発明では、上記の目的を達成するため、撮像装置で線
順次走査の信号を得て、これを記憶回路を用いて飛越走
査(インクレース)のテレビ信号に変換して送信L 、
受像側で上記テレビ信号のフレーム周波数のn倍のフレ
ーム周波数の線順次走査の信号に変換して画像を構成す
るようにしたものである。
[Summary of the Invention] In order to achieve the above object, the present invention obtains a line-sequential scanning signal using an imaging device, converts it into an interlaced scanning television signal using a memory circuit, and transmits the signal. L,
On the image receiving side, an image is constructed by converting it into a line-sequential scanning signal with a frame frequency n times the frame frequency of the television signal.

以下の実施例では、インクレースは現在一般に行なわれ
ている2:1の場合について、説明するが本発明はn 
(n〉2以上の整数):1の場合についても実現できる
In the following example, the ink race will be explained in the case of 2:1, which is generally practiced at present, but the present invention
(n>An integer greater than or equal to 2): The case of 1 can also be realized.

〔発明の実施例〕[Embodiments of the invention]

第21スは本発明tこよるテレビ信号処理方式の一実施
例における送信側の撮像装置の出力である線順次走査さ
れた画像信号を2=1のインクレース六れたテレビ信号
に変換する部分の構成を示す構成図である。
The 21st step is a part that converts the line-sequentially scanned image signal, which is the output of the image pickup device on the transmitting side, into a 2=1 incremented television signal in an embodiment of the television signal processing method according to the present invention. FIG. 2 is a configuration diagram showing the configuration of.

飛越走査を行なわない、すなわちフレームを上から下ま
で順次走査する撮像装置からの三原色信号101.10
2および103は、一般に知られているマトリックス回
路104によって輝度信号105と二つの色信号106
および107に変換される。信号105,106および
107は1フィルド分の容量を持つ緩衝記憶回路108
,109および110にそれぞれ読み込まれる。
Three primary color signals 101.10 from an imaging device that does not perform interlaced scanning, that is, scans the frame sequentially from top to bottom.
2 and 103 are a luminance signal 105 and two color signals 106 by a generally known matrix circuit 104.
and 107. Signals 105, 106 and 107 are sent to a buffer memory circuit 108 with a capacity for one field.
, 109 and 110, respectively.

緩衝記憶回路108,109および110は、同期信号
111からタイミング発生回路112によって発生させ
られるタイミング信号113によって走査線を一本おき
に出力114’、115゜116に読み出して飛越走査
を行なった信号に変換する。二つの色信号に対応する出
力115および116は、一般に知られている変調回路
117に与えられ搬送色信号118に変換される。輝度
信号に対応する出力114と搬送色信号118は、加算
回路119によって加算され複合カラーテレビ信号12
0となる。すなわち、1/30秒毎に525本の預次走
査された信号が緩衝記憶回路、108.109,110
に記録され、走査線を1本おきに読み出すから262.
5本分の信号が1/60秒の間に読出され1フィルド分
の画像信号を得て、次の1/60秒の間に残りの262
.5本分が続出されlフィールドの信号に変換されるこ
れをくり返することによって、通常のテレビ信号と同様
のインタレースされた信号となる。
Buffer memory circuits 108, 109, and 110 read every other scanning line to outputs 114', 115°116 using a timing signal 113 generated by a timing generation circuit 112 from a synchronization signal 111, and convert the signal into an interlaced scanning signal. Convert. Outputs 115 and 116 corresponding to the two color signals are applied to a commonly known modulation circuit 117 and converted into a carrier color signal 118. The output 114 corresponding to the luminance signal and the carrier color signal 118 are summed by an adder circuit 119 to form a composite color television signal 12.
It becomes 0. That is, 525 signals scanned every 1/30 seconds are stored in the buffer memory circuit, 108, 109, 110.
262. is recorded and every other scanning line is read out.
Five signals are read out in 1/60 second to obtain one field of image signals, and the remaining 262 signals are read out in the next 1/60 second.
.. Five broadcasts are output one after another and converted into an 1-field signal. By repeating this process, an interlaced signal similar to a normal television signal is obtained.

第2図においてマトリックス回路104と1フィルド緩
衝記憶回路108,109,110の順序を逆にしても
所定の動作をするけれども、三つの緩衝記憶回路の帯域
を輝度信号と同じにしなけわ、ばならないため回路規模
が大きくなる。
In FIG. 2, even if the order of the matrix circuit 104 and the one-field buffer memory circuits 108, 109, and 110 is reversed, the prescribed operation will still occur, but the band of the three buffer memory circuits must be made the same as that of the luminance signal. Therefore, the circuit scale increases.

第3図は、第2図の変換回路によって発生させられた飛
越走査を行なうカラーテレビ信号を、公知の輝度、色信
号分離回路により輝度信号と色信号に分離した後に、飛
越走査をしない(順次走査)信号に変換するための変換
回路の構成を示す図面である。
FIG. 3 shows a color television signal generated by the conversion circuit shown in FIG. 2, which is subjected to interlaced scanning, and which is separated into a luminance signal and a chrominance signal by a known luminance and chrominance signal separation circuit. 2 is a drawing showing the configuration of a conversion circuit for converting into a scanning (scanning) signal.

第3図1とおいて、入力信号201は、ニつの1フイル
ド遅延回路202および203によって、1フイルド遅
延した信号204と2フイルド遅延した信号205が発
生させられる。入力信号201と1フイルド遅延された
信号204は、スイッチ回路206の二つの入力となり
、また、1フィルド遅延さ拘また信号204と2フイル
ド遅延された信号205は、スイッチ回路207の二つ
の入力となる。スイッチ回路206と207は、垂直同
期信号208により制御され、1フイルド遅延された信
号が第1フイルドに有る場合には、入力信号201とフ
ィルド遅延され信号204を出方209および210に
それぞれ接続する。また、1フイルド遅延された信号2
04が第2フイルドに有る場合には、1フイルド遅延さ
せられた信号204と2フイルド遅延させられた信号2
05を出力209および210にそれぞれ出方する。し
たがって、出力209と210には、常に同じフレーム
の第2フイルドと第1フイルドが現われていることにな
る。
In FIG. 3, an input signal 201 is generated by two one-field delay circuits 202 and 203 into a signal 204 delayed by one field and a signal 205 delayed by two fields. Input signal 201 and signal 204 delayed by 1 field become two inputs of switch circuit 206, and signal 204 delayed by 1 field and signal 205 delayed by 2 fields become two inputs of switch circuit 207. Become. Switch circuits 206 and 207 are controlled by a vertical synchronization signal 208 and connect input signal 201 and field-delayed signal 204 to outputs 209 and 210, respectively, when the one-field delayed signal is present in the first field. . Also, the signal 2 delayed by 1 field
04 in the second field, the signal 204 delayed by 1 field and the signal 2 delayed by 2 fields.
05 to outputs 209 and 210, respectively. Therefore, the second field and first field of the same frame always appear in the outputs 209 and 210.

出力209と210は、走査線緩衝配憶回路213と2
15とスイッチ回路224によって飛部の信号変換の動
作を説明する。
Outputs 209 and 210 are output to scan line buffer circuits 213 and 2.
15 and the switch circuit 224 will be explained below.

第4図は、説明の便宜上第2図のスイッチ206.2図
と同一物は同一の番号を付している)。
In FIG. 4, for convenience of explanation, the same parts as the switch 206.2 in FIG. 2 are given the same numbers).

前述の如く、信号209と210はそれぞれ同一フレー
ムにおける第2フイールドと第」フィルドの信号が発生
しているおり、これらは走査線数止フィルド周期の関係
によって、第4図の如く180度の位相差を持ち、隣り
合う走査線が同一の時刻に存在するようになる。
As mentioned above, the signals 209 and 210 are generated from the second field and the second field in the same frame, respectively, and due to the relationship between the number of scanning lines and the field period, these are separated by 180 degrees as shown in Figure 4. There is a phase difference so that adjacent scanning lines exist at the same time.

よ/l   、、?/に− 緩衝記憶回路t71、Q−〆うはいずれも、−走査線の
半分の画素の記憶容量を持ち、書き込みの速度と読出し
の速度を独立にできる記憶回路で、半導体ランダムアク
セス記憶集積回路、磁心ランダダムアクセス記憶装置な
どで構成される。記憶容量が0.5走査線で良い理由は
、読み出した後へ順次残りの部分を読み込めば良いから
である。したがって、1走査線分の記憶容量を用意す、
れば、読出した後へ書きこむ必要がなくなるので、緩衝
記憶回路213および215゛の制御回路が簡単になる
Yo/l...? /N- buffer memory circuits t71 and Q-U are both memory circuits that have a storage capacity of half the pixels of a -scanning line and can make the write speed and read speed independent, and are semiconductor random access memory integrated circuits. , a magnetic core random access storage device, etc. The reason why a storage capacity of 0.5 scanning lines is sufficient is that after reading out the remaining portions, it is sufficient to sequentially read in the remaining portions. Therefore, the storage capacity for one scanning line is prepared.
If so, there is no need to write after reading, and the control circuits for the buffer memory circuits 213 and 215' can be simplified.

これらの緩衝記憶回路213、j15およびスイッチ回
路224を駆動するため、テレビ信号201から同期信
号分離回路226で水平同期信号227を分離し1それ
を用いてクロック発生回路228で水平同期信号に同期
したクロック信号229を作り、書き込みを制御する。
In order to drive these buffer memory circuits 213, j15 and switch circuit 224, a horizontal synchronizing signal 227 is separated from the television signal 201 in a synchronizing signal separation circuit 226, and is used to synchronize with the horizontal synchronizing signal in a clock generating circuit 228. A clock signal 229 is generated to control writing.

又読み出しは上記クロック信号の2倍の速度で読み出す
。又直倍器230で上記分離された水平同期信号から、
水平同期信号の半分の周期を持つ同期信号231を発生
し、スイッチ回路224を制御する。
Also, reading is performed at twice the speed of the above clock signal. Also, from the horizontal synchronization signal separated by the quadrupler 230,
A synchronization signal 231 having a period half that of the horizontal synchronization signal is generated to control the switch circuit 224.

したがって、テレビ信号201および204を0.5走
査線緩衝記憶回路213と215にそれぞれ走査線の中
央まで読み込んでおいて、それぞれ出力213′および
215′に第4図の波形213′(破線)、215’(
実線)のように2倍のスピ。
Therefore, the television signals 201 and 204 are read into the 0.5 scan line buffer storage circuits 213 and 215, respectively, up to the center of the scan line, and the waveforms 213' (dashed line) in FIG. 4 are output to the outputs 213' and 215', respectively. 215'(
The speed is doubled as shown in solid line).

−ドで読み出して、スイッチ回路224を用いて、水平
周期の半分の周期で出力213′と215′を交互に切
り換えて出力すれば、波形225に示すようlこ、1フ
イルドを新しい1フレームきする飛越走査を行なわない
変換されたテレビ信号225が得られる。
If the switch circuit 224 is used to alternately switch and output the outputs 213' and 215' at half the horizontal period, one field will be converted into one new frame as shown in the waveform 225. A converted television signal 225 is obtained without interlacing.

以上本発明を実施例によって説明1.だが、本発明は上
記実施例に限定されるものでなく、17ii7質の許す
んぎり、テレビ信号の輝度成分、あるいは輝度成分の低
周波部のみに適用することも本発明に含まれるものであ
る。又、実施例は2:1のインタレースされたテレビ信
号について説明したが一般にn e Iのインタレース
された場合にも適用される。この場合は送信側の変換回
路では(11−1)個のフィルド分の緩衝記憶回路を必
要とI’l、受信側では2(n−1)個のフィルド遅延
回路が必要となる。
The present invention will be described above with reference to examples.1. However, the present invention is not limited to the above-mentioned embodiments, and the present invention also includes application to only the luminance component of a television signal or the low frequency portion of the luminance component, as long as the 17ii7 quality allows. . Further, although the embodiments have been described with respect to a 2:1 interlaced television signal, the present invention generally applies to a ne I interlaced case as well. In this case, the conversion circuit on the transmitting side requires buffer memory circuits for (11-1) fields, and the receiving side requires 2(n-1) field delay circuits.

また、本発明の詳細な説明をアナログ処理とディジタル
処理の区別なく説明して舟だが、ディジタル処理および
標本化をともなう処理を行なう場合には、AD変換回路
、DA変換回路、泥波回路が必要となる。しかしながら
、これらの回路をどのようjご用いるかは、関連分野の
技術者の常識とするさころなので、説明樋省いた。
In addition, although the detailed explanation of the present invention will be explained without distinguishing between analog processing and digital processing, when performing processing that involves digital processing and sampling, an AD conversion circuit, a DA conversion circuit, and a mudwave circuit are required. becomes. However, how to use these circuits is a matter of common knowledge for engineers in related fields, so I have omitted the explanation.

〔発明の効果〕〔Effect of the invention〕

本発明は順次走査の嘩像装置の出力をインタレ−ス信号
にして伝送し、受信部で順次走査のテレビ信号として再
生するため、インタレースによる現行の伝送帯域を使用
しながら、走査線の多い画像をちらつきがなく再生する
ことができる。
The present invention transmits the output of a progressive scanning television imager as an interlaced signal, and reproduces it as a progressive scanning television signal at the receiver. Images can be played back without flickering.

【図面の簡単な説明】[Brief explanation of the drawing]

i1図は、従来の飛越走査を説明する図面、第2図およ
び第3図は、それぞれ本発明によるテレビ信号処理方式
における送信側および、受信側における信号変換回路の
構成を示す図、w、4図は上記第3図の信号変換回路の
構成図第5図は、第3図の動作を示す波形図である。1
04・・・・・・マスリックス回路、108,109,
110・・・・・・緩衝記憶回路、112・・・・・・
タイミング発生回路、117・・・・・・変調回路、2
02,203・・・・・・フィルド遅延−楽/ 1”1 2θl 嵜 2j図 堝3図 2θl 1tj/
Figure i1 is a diagram explaining conventional interlaced scanning, and Figures 2 and 3 are diagrams showing the configurations of signal conversion circuits on the transmitting side and receiving side, respectively, in the television signal processing system according to the present invention. The figure is a block diagram of the signal conversion circuit shown in FIG. 3 above. FIG. 5 is a waveform diagram showing the operation of FIG. 3. 1
04...Mathrix circuit, 108, 109,
110...Buffer memory circuit, 112...
Timing generation circuit, 117...Modulation circuit, 2
02,203...Filled delay-Raku/ 1"1 2θl 嵜 2j fig. 3 fig. 2θl 1tj/

Claims (1)

【特許請求の範囲】 1、送信側で撮像装置によって得られた線順次の画像信
号を1フレームがnフィルドからなるインクレースされ
たテレビ信号に変換し、受信側で上記テレビ信号をフレ
ーム周波数が上記テレ−ビ信号のフレーム周波数のn倍
の線順次走査信号に変換するテレビ信号処理方式。 2、第1項記載のテレビ信号処理方式において、受信側
で、入力された第1のテレビ信号と、第1のテレビ信号
から1フイルド遅延された第2のテレビ信号と、第1の
テレビ信号から2フイルド遅延された第3のテレビ信号
とを得て、第2のテレビ信号が第1フレーム−の信号で
あるときは上記第1およびs2のテレビ信号が、第2の
テレビ信号が第2フレームの信号であるときは上記第2
および第3のテレビ信号が発生するように上記第1、第
2、第3のテレビ信号から2つのテレビ信号を選択し、
上記選択された2つのテレビ信号のそれぞれの時間を1
/2に圧縮し、圧縮された上記2つのテレビ信号を走査
線単位で交互に切換えて時系列のテレビ信号に変換する
テレビ信号処理方式○
[Claims] 1. On the transmitting side, a line-sequential image signal obtained by an image pickup device is converted into an incremented television signal in which one frame consists of n fields, and on the receiving side, the television signal is converted to an incremented television signal with a frame frequency. A television signal processing method for converting the television signal into a line sequential scanning signal n times the frame frequency of the television signal. 2. In the television signal processing method described in paragraph 1, on the receiving side, the input first television signal, the second television signal delayed by one field from the first television signal, and the first television signal. When the second television signal is the signal of the first frame, the first and s2 television signals are obtained, and the second television signal is delayed by two fields. If it is a frame signal, the second
and selecting two television signals from the first, second, and third television signals such that a third television signal is generated;
1 time for each of the two TV signals selected above
A television signal processing method that converts the two compressed television signals into a time-series television signal by alternating the two compressed television signals in scanning line units.
JP58242032A 1983-12-23 1983-12-23 Television signal processing system Granted JPS59181789A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58242032A JPS59181789A (en) 1983-12-23 1983-12-23 Television signal processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58242032A JPS59181789A (en) 1983-12-23 1983-12-23 Television signal processing system

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP51155083A Division JPS6025949B2 (en) 1976-12-24 1976-12-24 TV signal processing method

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP1145343A Division JPH0242884A (en) 1989-06-09 1989-06-09 Television signal processing circuit
JP3136260A Division JPH04227392A (en) 1991-06-07 1991-06-07 Television signal processing system

Publications (2)

Publication Number Publication Date
JPS59181789A true JPS59181789A (en) 1984-10-16
JPS6262115B2 JPS6262115B2 (en) 1987-12-24

Family

ID=17083252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58242032A Granted JPS59181789A (en) 1983-12-23 1983-12-23 Television signal processing system

Country Status (1)

Country Link
JP (1) JPS59181789A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6457051A (en) * 1987-08-26 1989-03-03 Emoto Kogyo Kk Hot air space heater with heat exchanging and ventilating function
JPH01179847A (en) * 1987-12-29 1989-07-17 Takenaka Komuten Co Ltd Ventilator for building

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4871522A (en) * 1971-12-21 1973-09-27
JPS4976419A (en) * 1972-11-27 1974-07-23
JPS51110915A (en) * 1975-03-25 1976-09-30 Mitsubishi Electric Corp

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4871522A (en) * 1971-12-21 1973-09-27
JPS4976419A (en) * 1972-11-27 1974-07-23
JPS51110915A (en) * 1975-03-25 1976-09-30 Mitsubishi Electric Corp

Also Published As

Publication number Publication date
JPS6262115B2 (en) 1987-12-24

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