JPH06339125A - System converter for video signal - Google Patents

Abstract

PURPOSE:To realize the system conversion of a high definition television signal into a standard television signal by deciding a read start timing from a memory so as to reduce memory capacity with respect to picture data of the same line of a different field. CONSTITUTION:Data quantity of an HDTV signal A in the horizontal direction and in the line direction are reduced in the unit of fields and reduced picture data are written in a memory 4. When the field of the HDTV signal A and a field of an NTSC signal differ, picture data from the memory 4 are read faster by 1H than the case that the field is equal only for a period of a 2nd field of the NTSC signal. Moreover, even when picture data are read out of the memory 4 slower by 1H than the case that fields are equal for a period of the 1st field of the NTSC signal, the vertical relation of the line between fields is kept normal and the obtained effect is entirely equal to each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal format conversion device for converting a wide band high definition television signal into an existing standard television signal.

[0002]

2. Description of the Related Art A high definition television signal has a band of 2
Since it is as high as 0 MHz or more, it is difficult to directly transmit it using a broadcasting satellite or the like. Therefore, as a method of significantly compressing the band of this high definition television signal, MUSE (M
The ultimate sub-nyquist sampling encoding method has been proposed and put to practical use. It transmits 1/4 of the samples of the original high definition television signal sequentially,
This is a method of transmitting one complete high-definition television signal image in 4 fields of SE signal. Therefore, on the receiving side, it is necessary to recover the untransmitted samples by interpolating the transmitted samples. This restoration means interpolates using samples of the past three fields in the still image area, and interpolates only samples of the current field in the moving image area. The switching of the interpolation means is performed on the receiving side by detecting the amount of movement of the image. Although high-definition television broadcasting can be viewed by the signal processing described above,
Since this signal processing circuit is very expensive, it will take a considerable amount of time before it becomes popular for general household use.

Therefore, for example, a device described in Japanese Patent Laid-Open No. 4-196788 converts a high-definition television signal into a standard television signal which is widely used in ordinary households to watch high-definition television broadcasting. It is possible to do it.

In the above system conversion device, the data amount in the horizontal direction (time axis direction) and the vertical direction (line direction) of a high definition television signal (hereinafter referred to as an HDTV signal) is appropriately reduced, and a standard television signal ( Hereinafter, the data amount is similar to that of the standard TV signal). In order to convert the aspect ratio, image data is written in the memory during a period corresponding to the effective line period of the HDTV signal, for example, a high level period of the signal WE in FIG. 2, and a standard TV which is a high level period of the signal RE in FIG. The image data is read from the memory over a period corresponding to about 3/4 of the effective line period of the signal.

With this system conversion device, it becomes possible to watch high-definition television broadcasting on a TV for standard television signals.

[0006]

In the system conversion device described above, the image data is written to the memory in synchronization with the frame pulse of the HDTV signal, and the image from the memory is synchronized with the vertical synchronization signal VD of the standard TV signal. Data is being read. At this time, this frame pulse and VD
Have a phase synchronization relationship in the frame period, and the first field of the standard TV signal is started a predetermined time after the start of the first field of the HDTV signal. As a result, the image data in which the data amount of the video signal of the first field of the HDTV signal is reduced is the image data of the first field of the standard TV signal and the image data in which the data amount of the video signal of the second field of the HDTV signal is reduced. Are converted into image data of the second field of the standard TV signal, and the vertical relationship of the same line between different fields is not reversed. As shown in the lower left diagram of FIG. An image of one frame is constructed in the order of n lines of two fields, n + 1 lines of the first field, n + 1 lines of the second field, ... Then, as shown in FIG. 2, after the signal WE is set to the high level, the signal RE is set to the high level,
After the signal WE is set to the low level, the signal RE is set to the low level, that is, after the writing to the memory is started, the reading from the memory is started, the writing to the memory is finished, and the next writing is started from the memory. By establishing the phase synchronization relationship between the frame pulse and VD so as to complete the reading of, the memory can be made a memory having a capacity of the image data amount for one field of the standard TV signal.

However, when the frame pulse and VD do not have the phase synchronization relationship in the frame cycle but the phase synchronization relationship in the field cycle, for example, the standard TV shown in FIG.
It is possible that the first and second fields of the signal will be swapped. In such a case, if the above-described processing is performed using the memory having the capacity of the image data amount of one field of the standard TV signal, the image data obtained by reducing the data amount of the video signal of the first field of the HDTV signal is obtained. Standard T
The image data of the second field of the V signal is converted into the image data of the first field of the standard TV signal by converting the image data of the video signal of the second field of the HDTV signal into the image data of the first field of the standard TV signal. As shown in FIG. 5, an image in which lines are vertically reversed between different fields is constructed. Therefore, in such a case, the image data of the first field of the HDTV signal is converted into the first field of the standard TV signal.
In order to convert the image data of the second field of the HDTV signal into the image data of the second field of the standard TV signal into the image data of the field, a memory having a capacity equal to or more than the image data amount of one frame of the standard TV signal is used. It becomes necessary, and there is a problem that the cost of the device is increased due to the increase of the circuit scale.

In view of the above-mentioned conventional technique, an object of the present invention is to reduce the capacity of a memory used and to realize a system conversion of a high definition television signal into a standard television signal at a low cost. To provide a method conversion device.

[0009]

In order to achieve the above object, the present invention thins out image data between image data that are continuous on the time axis of an HDTV signal and between adjacent lines. The image data reduced by the thinning process is written in the memory in units of fields. At this time, the field of the image data written in the memory is identified and compared with the field of the standard TV signal to be constructed by the image data written in the memory. If the same field is detected, the image data reading from the memory is started after a predetermined time delay from the field change of the standard TV signal. On the contrary, when reading the image data with a reduced data amount as the video signal of the first field of the standard TV signal from the memory, the image data from the memory is detected at the same timing as when the same field is detected. To start reading. Then, in the case of reading from the memory the image data of which the data amount is reduced as the video signal of the second field of the standard TV signal which is detected as a different field, it corresponds to one line from the predetermined time when the same field is detected. The reading of the image data from the memory is started earlier than the period.

[0010]

The amount of image data reduced by the thinning means of the image data of the HDTV signal is the standard TV in field units.
It becomes almost equal to the data amount of the signal, and the HDT
It becomes possible to convert the V signal into a standard TV signal. Also, a field of image data of the HDTV signal to be written in the memory and a standard TV to be composed of this image data.
By comparing with the signal field, it becomes possible to determine the read start timing from the memory so that the normal vertical relationship of the images is established for the image data of the same line in different fields. That is, when the same field is detected, the same line of different fields is started by starting the reading of the image data from the memory after delaying for a predetermined time from the field change time, as in the system conversion device described in the above-mentioned prior art. The image data of the first field is displayed above the image data of the second field on the screen with respect to the image data of 1.

On the contrary, when different fields are detected, the image data of the first field displayed on the upper side of the screen of the HDTV signal becomes the image data of the second field of the standard TV signal and becomes the lower side of the screen. Will be displayed in. However, since the image data is read out early by the means described above for a period corresponding to one line, it is displayed above the image data of the first field in the standard TV signal on the screen, which is different in the HDTV signal. It is possible to perform conversion to a standard TV signal while maintaining the vertical relationship of the image data on the same line between fields.

Therefore, according to the present invention, it is possible to convert an HDTV signal into a standard TV signal in field units,
The capacity of the memory used is halved compared to the conventional one, and it becomes possible to realize a low-priced video signal format conversion device with a reduced circuit scale.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a block diagram showing an embodiment of a video signal format conversion apparatus to which the present invention is applied, FIG. 3 is a block diagram showing an embodiment of the horizontal data amount reduction processing circuit of FIG. 1, and FIG. FIG. 5 is a block diagram showing an embodiment of the vertical data amount reduction processing circuit of FIG. 1, FIG. 5 is a waveform diagram of each part for explaining the processing operation of FIG. 3, and FIG. 6 illustrates the processing operation of FIG. 7 is a block diagram showing each embodiment of the memory control circuit (1) of FIG. 1 and a waveform chart of each part thereof, and FIG. 8 is a waveform diagram of each part of the memory control circuit (2) of FIG. 9 is a block diagram showing an embodiment, FIG. 9 and FIG. 10 are waveform charts of respective parts for explaining the processing operation of FIG. 8, and FIG. 11 shows a relationship between respective lines of an HDTV signal and a standard TV signal by system conversion. It is a waveform diagram.

In this embodiment, an HDTV signal of 1125 lines per frame is used as a high definition television signal.
N, which is a standard TV signal of 525 lines per frame
The case where the system is converted to the TSC signal will be described.

In FIG. 1, an HDTV signal A input through a terminal 100 is supplied to a synchronization detection circuit 7 and a data amount reduction process composed of horizontal and vertical data amount reduction processing circuits 2 and 3. It is supplied to the circuit 1.
The horizontal data amount reduction processing circuit 2 is configured by the block diagram shown in FIG. 3, for example.

In FIG. 3, the HDTV signal A (A in FIG. 5) input through the terminal 120 is supplied to the latch circuit 15, and at the same time, by the clock ck1 (ck1 in FIG. 5) input through the terminal 120. It is delayed by a period corresponding to one sample, and further delayed by the latch circuits 16 and 17 by a period corresponding to one sample. This latch circuit 1
Delayed HDTV signals A1, A1 (A1 in FIG. 5), A2 (A2 in FIG. 5), A3 (A3 in FIG. 5) from 5, 16, and 17
Are supplied to multipliers 18, 19 and 20, respectively, and are multiplied by 1/4, 1/2 and 1/4, respectively. The output signals from the multipliers 18, 19, 20 are added by the adder 21, and the output signal J (J in FIG. 5) is supplied to the latch circuit 22. In the latch circuit 22, the output signal J from the adder 21 divides the clock ck1 from the frequency divider 23 into a frequency of ½ to generate a clock ck2 (ck in FIG. 5).
Latched in 2). As a result, the HDTV signal A ′ (A ′ in FIG. 5) whose data amount is reduced by half as compared with the HDTV signal A supplied through the terminal 120 is output from the latch circuit 22 and is output through the terminal 130. Is output.
Then, for example, the data is supplied to the vertical data amount reduction processing circuit 3 configured by the block diagram shown in FIG.

In FIG. 4, the HDTV signal A ′ (A ′ in FIG. 6) from which the data amount has been reduced from the horizontal data amount reduction processing circuit 2 is supplied through the terminal 140, and the multiplier 3
It is input to the 4 and 1 line delay circuits 30. Then, for example, in the 1-line delay circuit 30 configured by a 1-line memory, the signal is delayed by a period corresponding to 1 line of the HDTV signal A ′ with the reduced data amount, and the signal A1 ′ (A1 ′ in FIG. 6) is output. To be done. Further, the signal is delayed by the 1-line delay circuit 31 for a period corresponding to 1 line, and the signal A2 '
(A2 'in FIG. 6) is output. This delay circuit 30, 3
The output signals A1 'and A2' from 1 are respectively applied to the multiplier 3
The signals K1 and K2 from the memory control circuit (1) 6 supplied to the terminals 3 and 32 and supplied via the terminal 150.
(K1 and K2 in FIG. 6) are multiplied by n1, n2 and n3 together with the multiplier 34, respectively. In this embodiment, a case will be described in which the vertical data amount reduction processing circuit 3 reduces 8 lines of an HDTV signal to 3 lines of a standard TV signal. Therefore, the period of eight lines of the HDTV signal, that is, the period of eight horizontal synchronizing signals (HD in FIG. 6) is divided into four types by the signals K1 and K2 from the memory control circuit (1) 6 as shown in FIG. Split into. Then, during the period of K1 = High level and K2 = Low level, the HDTV signals having a time difference of a period corresponding to one line are respectively n by the multipliers 34, 33 and 32.
1 = 3/8 times, n2 = 1/2 times, n3 = 1/8 times. Similarly, during the period of K1 = High level and K2 = High level, the HDTV signals having the time difference of the period corresponding to one line are n1 = 1/8 times and n2 = 1 / n in the multipliers 34, 33 and 32, respectively. In the period of K1 = Low level and K2 = High level, the HDTV signals having a time difference of a period corresponding to one line are n1 and n3 = 3/8, respectively.
= 1/4 times, n2 = 1/2 times, and n3 = 1/4 times.
The other periods of K1 = Low level and K2 = Low level are not specified in this embodiment because they are not written in the memory as described later. And the multipliers 34 and 3
The image data multiplied by n1, n2, and n3 from 3, 32 is supplied to the adder 36, and the addition output signal A ″ (A ″ in FIG. 6) is output via the terminal 160 and input to the memory 4. .

In the memory 4, for example, the memory control circuit (1) 6 constructed by the block diagram shown in FIG.
The image data A ″ from the data amount reduction processing circuit 1 is written according to the control signals WE and RST-W from.

That is, the terminal 200 in FIG.
And 210, the signal HP of the horizontal sync frequency according to the HDTV signal from the sync detection circuit 7 (H in FIG. 7 (2)).
P) and the signal VP of the vertical synchronizing frequency (V in FIG. 7B).
P) is supplied. The signal VP conforms to the vertical synchronizing signal of the HDTV signal, and its pulse width is a period corresponding to one line.
(1H), its frequency is equal to the field frequency, and its interval is 562.5 lines (562.5
H). This signal VP is the delayed pulse generation processing circuit 5
0 to synchronize with the rising edge of the signal HP for a period substantially corresponding to the effective line period, and to establish an interlace relationship between fields after the line number reduction process.
Similarly, from the rising of the signal VP of the first field of the DTV signal to the rising of the signal VP of the second field is 564H, similarly, from the rising of the signal VP of the second field to the rising of the signal VP of the first field is 561H. The signal VP is delayed by using the signal HP so that And
At the same time as outputting the signal VP 'delayed from the signal VP, the signal RST-W (FIG. 7) having the pulse width of the same period as the cycle of the clock ck2 is synchronized with the falling edge of the signal VP'.
(RST-W of (2)) is supplied to the memory 4 via the terminal 250 as a reset signal of the write address of the memory 4. The output signal VP ′ from the delay pulse generation processing circuit 50 is supplied to the load terminal of the counter 40 via the AND circuit 49. A signal HP is supplied to the clock terminal of the counter 40 via the terminal 200, and 8 is set as the load value. Therefore, when the signal VP 'is supplied to the load terminal, the outputs Qa, Qb, Qc of the counter 40 (Qa, Qb, Qc in FIG. 7 (2)) all become 0, after which the counter 4 is incremented. Then, at the eighth clock of the signal HP, the carry signal RCO (RCO in FIG. 7 (2)) becomes High level, and A
It is supplied to the load terminal of the counter via the ND circuit 49. As a result, the above processing is performed on the signal HP in field units.
Are sequentially repeated every 8 clocks of, and signals Qa, Qb, Qc are repeatedly output every 8 clocks of signal HP.
The output signals Qa, Qb, Qc from the counter 40 are directly applied to the AND circuits 44, 45, 46, and simultaneously, the AND circuits 44, 4 via the inverter circuits 41, 42, 43.
5,46. From this AND circuit 44, Qa
= Qb = Qc = Low level outputs a High level signal, AND circuit 45 outputs a Qa = Qc = Low level signal and Qb = High level outputs a High level signal, and AND circuit 46 outputs When Qa = Qc = High level and Qb = Low level, a High level signal is output. The output signals from the AND circuits 44 and 45 are O
The output signals from the AND circuits 45 and 46 are supplied to the R circuit 47 and the OR circuit 48, respectively. As a result, from the OR circuit 47, a period of Qa = Qb = Qc = Low level,
Hig during Qa = Qc = Low level and Qb = High level
The signal K1 at the h level (K1 in FIG. 7 (2)) is output, and the OR circuit 48 outputs Qa = Qc = Low level and Qb.
= High level period and Qa = Qc = High level Qb
= A signal K2 that becomes High level during the Low level period (Fig. 7
(2) K2) is output. This OR circuit 47, 48
The output signals K1 and K2 from the respective terminals are supplied to the vertical data amount reduction processing circuit 3 via the terminals 220 and 230 to set the above-mentioned coefficient for data amount reduction in the line direction, and are also supplied to the OR circuit 52. It In the OR circuit 52,
A period in which the signal K1 or the signal K2 is at a high level, that is, a period in which Qa = Qb = Qc = Low level and a period in which Qa = Q.
When c = Low level and Qb = High level, and Qa = Q
A signal WE (WE in FIG. 7 (2)) that is at the High level is output during the period of c = High level and Qb = Low level, and is supplied to the memory 4 via the terminal 240 as a writing allowable period to the memory.

In the memory 4, the image data A ″ from the data amount reduction processing circuit 1 is written according to the control signals RST-W and WE from the memory control circuit (1) 6. That is, it is supplied for each field. The write address of the memory is reset by the signal RST-W generated, and the clock c
At the same time as writing from address 0 at k1, HD
Image data is intermittently written during a period of three lines in which the signal WE is at a high level intermittently during a period of eight lines of a TV signal. By the writing process to the memory 4, the number of lines in one field is reduced to about 3/8. And
After a predetermined time from the start of writing to the memory 4, for example, as shown in FIG.
The control signals RST-R, RE from the memory control circuit (2) 8 constituted by the block diagram shown in FIG.
The image data is read from the memory 4 by.

In FIG. 8, signals VD, SYNC-N and C input through terminals 260 and 280 are output signals from the standard TV signal sync signal generation circuit 9. Standard T
In the V signal synchronizing signal generating circuit 9, the vertical synchronizing signal V of the HDTV signal from the HDTV signal synchronizing signal detecting circuit 7 is generated.
In synchronism with P, the vertical frequency signal VD (VD of FIG. 9) of the NTSC signal which is the standard TV signal, the composite sync signal SYNC (SYNC of FIG. 10) and the period of the first field are, for example, at the High level and are set to the High level. In the period, for example, the field identification signal F (F (1), F (2) in FIG. 9) that is at the Low level is output. The signal F supplied via the terminal 280 is input to one terminal of the EX-OR circuit 67 of the comparison circuit 10 including the exclusive OR circuit (EX-OR circuit) 67 and the NAND circuit 68.
The field identification signal C of the HDTV signal from the sync signal detection circuit 7 supplied via the terminal 270 to the other terminal.
Is entered. In this embodiment, the field identification signal C is also a signal that is at a high level during the first field period and is at a low level during the second field period, similar to the field identification signal F of the standard TV signal. Therefore, the output from the EX-OR circuit 67 is a signal that is at the High level only during the period when the polarities of the signals C and F are different, that is, during the period when the fields of the HDTV signal and the standard TV signal are different, and is supplied to the NAND circuit 68. . The signal C is input to the other terminal of the NAND circuit 68, and as a result, the signal H that is at the Low level during the period in which the HDTV signal and the standard TV signal are different from each other in the first field period is the comparison circuit H. It is output from 10.

Further, the NT supplied through the terminal 260
The vertical frequency signal VD (VD in FIG. 9) of the SC signal is input to the delay circuit (1) 60. This delay circuit (1) 6
The composite sync signal SYNC (SYNC in FIG. 10) of the NTSC signal supplied via the terminal 260 is input to the clock terminal 0 of 0 via the inverter circuit 63. The waveform in the vicinity of the vertical synchronizing signal of the synchronizing signal SYNC differs between the first field and the second field as shown in FIG. Therefore, the delay circuit (1) 60 latches the signal VD by using the signal obtained by inverting the synchronization signal SYNC as a clock, so that the latch output signal VD ′ in the second field period is shorter than that in the first field period. A period corresponding to 1/2 line, that is, 0.5
It is delayed by H for a long period. As a result, the interval of the signal VD 'of the second field is 263H from the fall of the signal VD' of the first field to the fall of the signal VD 'of the second field, as shown in FIG. From the trailing edge to the trailing edge of the signal VD 'in the first field, 262H. The output signal VD 'from the delay circuit (1) 60 is supplied to the delay circuit (2) 61, and a signal VD1' (VD1 'in FIG. 9) which is at High level for a predetermined time from the fall of the signal VD' is output. It Further, the delay circuit (3) 62 delays for 1H period and outputs the signal VD2 '(VD2' in FIG. 9). These signals VD1 ', VD
The trailing time of 2'indicates the start position of the effective line when the image data obtained by converting the format of the HDTV signal is displayed on the display for NTSC signals. The period is about 30H. Delay circuit (2) 6
1 and the output signals VD1 'and VD2' from the delay circuit (3) 62 are supplied to the selector circuit 64, and the comparison circuit 1
With the output signal H from 0, for example, the signal VD2 'is selectively output while the signal H is at the high level, and the signal VD1' is selectively output while the signal H is at the low level. The signal VD1 'or VD2' selected and output from the selector circuit 64 is supplied to the pulse generation circuit (1) 65 and the pulse generation circuit (2) 66. In the pulse generation circuit (1) 65, the signal VD1 '
Alternatively, in synchronization with the falling edge of VD2 ′, the number of lines of the image data written in the memory, that is, the period of the number of lines of the NTSC signal corresponding to the number of lines after thinning out the data of the HDTV signal to 3/8 in the vertical direction is set to High. The signals RE (RE (1) and RE (2) in FIG. 9) that become the level are supplied to the memory 4 via the terminal 290 as a signal designating the reading period of the memory 4. At the same time, in the pulse generation circuit (1) 65, signals RST-R (RST-R (1), RST- in FIG. 9) that reset the read address of the memory 4 in synchronization with the falling of the signal VD1 'or VD2'.
R (2)) is supplied to the memory 4 via the terminal 300. The image data is read from the memory 4 by the signals RE and RST-R, but the signal H from the comparison circuit 10 is output.
The timing is adjusted by. Ie HDTV
When the fields of the signal and the NTSC signal are the same (Fig. 9)
F (1), H (1), RE (1), RST-R
In (1)), the image data of the line formed by performing the reduction processing on the image data of the line of the first field of the HDTV signal is the image data of the line of the first field of the NTSC signal, and the image data of the line of the second field of the HDTV signal. The image data of the line formed by reducing the image data of the line is the image data of the line of the second field of the NTSC signal, and the image data of the line at the same position from the beginning of each field is the same for each field. The image data of the line. And HDTV signal and N
When the field is different from the TSC signal (F in FIG. 9)
In (2), H (2), RE (2), and RST-R (2)), the image data of the line formed by the reduction processing from the image data of the line of the first field of the HDTV signal is NT.
Image data of the second field line of the SC signal,
The image data of the line formed by reducing the image data of the line of the second field of the HDTV signal is NTSC.
The image data of the line of the first field of the signal is read, and the image data of the line at the same position from the beginning of each field is read as the image data of one line before only the image data of the second field of the NTSC signal. At this time, the image data read from the memory 4 is HDT.
When the fields of the V signal and the NTSC signal are the same, the interline system as shown in the standard TV 1 of FIG. 11 is established, and the vertical relationship of the lines between the fields is normal. If the fields of the HDTV signal and the NTSC signal are different, the image data of the line formed from the image data of the line of the first field of the HDTV signal (for example, the white circle n + 1 of the standard TV 1 in FIG. 11) is of the second field. The image data of the line one line before (for example, the black circle n of the standard TV 2 in FIG. 11) is read at the timing, and the HDT
The image data of the line formed from the image data of the line of the second field of the V signal (for example, the black circle n of the standard TV 1 of FIG. 11) is the image data of the same line of the first field (the white circle of the standard TV 2 of FIG. 11, for example). Since the data is read at the timing of n), the vertical relationship of the lines between the fields becomes normal in this case as well.

Memory control circuit (2) described above
The image data read from the memory 4 by the control signals RE and RST-R from the synchronization signal adding circuit 5
Is supplied to the NTSC by a signal such as a vertical and horizontal synchronizing signal, a color subcarrier indicating a color signal phase, or a signal indicating a period in which the signal should be inserted from the standard TV signal synchronizing signal generating circuit 9. After the various synchronizing signals of the signals are added, the image data converted into the NTSC signal is output via the terminal 110.

In the above embodiment, when the fields of the HDTV signal and the NTSC signal are different, the image data is read from the memory 4 1H earlier than the case where the fields are the same only during the period of the second field of the NTSC signal. However, the present invention is not limited to this.
Even when the image data is read out from the memory 4 by 1H later than when the fields are the same only during the first field period of the TSC signal, the vertical relationship of the lines between the fields can be normally maintained and no effect can be obtained. It does not deviate from the gist of the present invention.

In addition, the above-described embodiment is based on the HDTV signal and the NTS.
The case where the C signal and the C signal are synchronized with each other at the field frequency and the predetermined phase has been described, but the present invention is not limited to this, and the present invention can be applied without depending on the phase relationship, and processing in field units can be performed. This is possible, and the capacity of the memory used is about half that of the conventional method.

In the above embodiment, the case where the HDTV signal of 1125 lines / frame is converted as the high definition television signal has been described, but the present invention is not limited to this, and the band compressed HDTV signal may be used. Further, it goes without saying that the present invention can be applied to the system conversion of a video signal having a larger number of lines per frame than a standard TV signal.

In the above embodiment, the system conversion is performed by performing the data amount reduction processing in the horizontal and vertical directions, but the present invention is not limited to this, and the method is performed only by the data amount reduction processing in the vertical direction. It is obvious that the present invention can be applied to conversion.

In the above embodiment, the number of lines of the HDTV signal is reduced and the aspect ratio of the HDTV signal is not changed and displayed on the display for the standard TV signal. However, the present invention is not limited to this. It is obvious that the present invention can also be applied to the case of displaying an HDTV signal with a reduced amount of data on the entire surface of the display for standard TV signals by changing the aspect ratio.

[0029]

As described above, according to the present invention, the HD
The TV signal is subjected to the data amount reduction processing in the horizontal and line directions in field units, and the reduced image data is written in the memory. When the image data is read from the memory, if the fields of the HDTV signal and the NTSC signal are different, the NTSC
The image data of the first field of the signal is read later by 1H, or the image data of the second field of the NTSC signal is read earlier by 1H than when the fields are the same. As a result, even when different fields are used, it is possible to maintain the vertical relationship of lines between fields and perform system conversion on a field-by-field basis. This reduces the amount of memory used and realizes a video signal system conversion device at a low price. It is possible to do so.

[Brief description of drawings]

FIG. 1 is a video signal format converter 1 to which the present invention is applied.
It is a block diagram which shows an Example.

FIG. 2 is a waveform diagram for explaining the operation of the conventional technique.

FIG. 3 is a block diagram showing an embodiment of the horizontal data amount reduction processing circuit of FIG.

FIG. 4 is a block diagram showing an embodiment of the vertical data amount reduction processing circuit of FIG.

FIG. 5 is a waveform chart of each part for explaining the processing operation of FIG.

FIG. 6 is a waveform chart of each part for explaining the processing operation of FIG.

7 is a block diagram showing an embodiment of the memory control circuit (1) of FIG. 1 and waveform diagrams of respective parts for explaining the operation.

8 is a block diagram showing one embodiment of the memory control circuit (2) of FIG. 1. FIG.

FIG. 9 is a waveform chart of each part for explaining the processing operation of FIG.

FIG. 10 is a waveform chart of each part for explaining the processing operation of FIG.

FIG. 11 is a waveform diagram showing a relationship between lines of an HDTV signal and a standard TV signal by system conversion.

[Explanation of symbols]

3 ... Vertical data amount reduction processing circuit, 4 ... Memory, 6 ...
Memory control circuit (1), 7 ... HDTV signal sync signal detection circuit, 8 ... Memory control circuit (2),
9 ... Standard TV signal sync signal generation circuit, 10 ... Field identification signal comparison circuit, 64 ... Selector circuit, 65 ... Pulse generation circuit (1), 66 ... Pulse generation circuit (2).

Claims (5)

[Claims] 1. A video signal format conversion device for converting a wideband first video signal into a narrower band second video signal than the video signal, wherein the data amount of the first video signal is reduced in field units. Means for writing the reduced image data from the reducing means to the memory at a first frequency based on the first video signal on a field-by-field basis, and means for identifying a field of the image data to be written to the memory, Means for comparing the identification field of the first video signal by the result of the identification means with a field of the second video signal that is constituted by the image data reduced by the reduction means; and based on the result of the comparison means, Means for reading the image data from the memory at a second frequency based on the second video signal, and the image data read from the memory The second
And a means for adding a synchronization signal based on the video signal of 1. 2. A means for reading out the image data from the memory based on the result of the comparing means reads out the image data from the memory after a first predetermined time delay from a field change point of the second video signal. The first reading means to start, and the first reading means from the time when the field of the second video signal changes.
Second, the image data reading from the memory is started after a delay of a period corresponding to one line from the predetermined time
When the same field is detected by the reading means and the comparing means, when the image data in which the data amount of the video signals of the first and second fields of the first video signal is reduced is read from the memory. If the different field is detected by the means for selecting either the first reading means or the second reading means and the comparing means, the first field of the second video signal is detected. When the image data having the reduced data amount is read from the memory by using the video signal of the second video signal as a constituent line, the second reading means is selected, and the video signal of the second field of the second video signal is used as the constituent line. And a means for selecting the first reading means when reading the image data having a reduced data amount from the memory. System conversion apparatus for image signals of claim 1, wherein. 3. The first video signal is a wide band high definition television signal, and the second video signal is a current standard television signal.
Alternatively, the video signal format conversion device described in 2. 4. The image data amount reducing means comprises image data thinning means by arithmetic processing between image data continuous on a time axis, and line thinning means by arithmetic processing between adjacent lines in the same field. 4. The video signal format conversion device according to claim 1, wherein 5. A means for phase-synchronizing the first and second video signals at a frequency equal to a vertical synchronizing signal, and the reduced image data from the reducing means for at least one field image of the second video signal. 5. The video signal format conversion apparatus according to claim 1, further comprising: a writing means for writing in a memory having a capacity corresponding to a data amount.