JPH11150682A - Image processor, image processing method and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To configure an image processing circuit that enables an image of a high image quality by using field memory. SOLUTION: This device is provided with a video signal processing part 8 which produces a 1st luminance signal and a color-difference signal from a 1st-input video signal and produces a 2nd luminance signal from a 2nd input video signal, a 1st compressing means 10 which compresses the 1st luminance signal into prescribed data quantity, a 2nd compressing means 14 which compresses the 2nd luminance signal into prescribed data quantity and a 3rd compressing means 12 that compresses the color-difference signal into prescribed data quantity, sets compression ratios of each of the means 10, 14 and 12 respectively so that the total of data quantity of each signal which is compressed by the means 10, 14 and 12 may be less than storage capacity of a memory means 16 and also increases information volume of the luminance signals by storing only one field about the color-difference signal in the means 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, an image processing method, and a storage medium, and more particularly, to an image processing apparatus suitable for performing a special effect process using a field memory.

[0002]

2. Description of the Related Art In recent years, home video cameras have a function of adding a pleasure at the time of shooting, such as displaying a still image, overlapping a still image from an image being shot, and changing scenes, and a CCD camera. Function to improve sensitivity by lengthening exposure time, S / N by removing noise included in image
A function for obtaining a good image has come to be mounted, and better image quality and higher functions have been realized by image processing.

In the future, solid-state imaging devices of the all-pixel readout type will be used, and high-quality image processing such as frame-free still image display without blurring, high-quality image processing of enlarged images, and multi-screen display of frame images will be used. The demand for is increasing.

An image processing circuit using a frame memory is required to meet such a demand for higher image quality. FIG. 4 shows a configuration example of a conventional image processing circuit using a frame memory. Control for performing four-screen multi-screen display will be described.

In FIG. 4, reference numeral 62 denotes LPF means for subjecting an input digital video signal to low-pass filtering, 64 denotes a thinning means for thinning out the output signal of the LPF means at a predetermined ratio, and 66 denotes an output signal of the thinning means 64. The first memory means for recording the odd-numbered line signals of the second memory means, the second memory means for recording the even-numbered lines of the output signal of the thinning means 64, and the first and second memory means 66, 68 A memory control means 72 for generating a control signal to be controlled is a switch means for switching and outputting an output signal of the first memory means 66 and an output signal of the second memory means 68 for each field.

Next, the operation of the image processing circuit of FIG. 4 will be described with reference to FIG. Each pixel constituting the input video signal is subjected to a low-pass filter process in the LPF unit 62 and then supplied to the thinning unit 64. Then, the thinning means 64 performs thinning processing according to the number of divisions of the multi-screen display.

For example, in the case of four-screen multi-screen display, one pixel is thinned out every two pixels in the horizontal direction. In the case of the nine-screen multi-screen display, a process of thinning out two pixels for every three pixels is performed, and the video signal after the thinning process is output to the first memory means 66 and the second memory means 68. You.

The video signal of the odd-numbered line of the video signal thinned in the horizontal direction is recorded in the first memory means 66, and the video signal of the even-numbered line is recorded in the second memory means 68. Therefore, a reduced image for odd field is recorded in the first memory means 66, and a reduced image for even field is recorded in the second memory means 68.

At the time of reading, a read address is controlled to read a video signal from the first memory means 66 and the second memory means 68, and at the switch means 72, from the first memory means 66 at the time of an odd field. At the time of the even field, the second memory means 6
By switching to output the signal from 8,
The image of the four-screen multi-screen becomes a frame signal, and a high-definition video with high vertical resolution is obtained.

[0010]

However, since a frame memory is required to display such a frame image, there is a problem that the price of the entire apparatus becomes high. Further, there is a problem that a large-scale circuit is required to perform the compression processing using DCT, and the apparatus becomes more and more expensive.

On the other hand, if a compression processing circuit is formed using a field memory, the cost of the apparatus can be reduced. However, when a still image is displayed using a field memory, there is a problem that the image quality deteriorates greatly.

An object of the present invention is to provide an image processing circuit capable of displaying a high-quality image using a field memory in view of the above-mentioned problems.

[0013]

According to the present invention, there is provided an image processing apparatus having a memory capable of recording a video signal for one field, comprising: a first luminance signal and a color difference signal from a first input video signal; Generate a signal,
Video signal processing means for generating a second luminance signal from a second input video signal; first compression means for compressing the first luminance signal to a predetermined data amount; A second compression means for compressing the color difference signal to a predetermined data amount, and a second compression means for compressing the color difference signal to a predetermined data amount. Each of the signals compressed by the first to third compression means is provided. The compression ratio of each compression unit is set so that the total of the data amount is smaller than the storage capacity of the memory unit.

Another feature of the image processing apparatus of the present invention is that the first and second luminance signals are compressed to 5 bits, and the color difference signals are compressed to 2 bits. .

Another feature of the image processing apparatus of the present invention is that the first input video signal and the second input video signal are video signals output from an image pickup apparatus of an all-pixel readout system. The first input video signal and the second input video signal form a frame signal without blur.

Another feature of the image processing apparatus of the present invention is that the second input video signal is the first video signal.
The input video signal is a video signal delayed by a predetermined time, and the memory means is controlled to write the compressed video signal intermittently.

Another feature of the image processing apparatus of the present invention is that a first compression means for compressing a luminance signal of the first input video signal to a predetermined data amount, and a second input video signal. A second compression means for compressing the luminance signal of the first input video signal into a predetermined data amount; a third compression means for compressing the color difference signal of the first input video signal to a predetermined data amount; Field memory means for recording an output signal, an output signal of the second compression means, and an output signal of the third compression means, and a first memory for expanding a compressed luminance signal read from the field memory means. And second decompression means; third decompression means for decompressing the compressed chrominance signal read from the field memory means; first luminance signal decompressed by the first decompression means; Extension by means of extension It is characterized in that a second switching means for switching and outputting a luminance signal for each field that was.

Further, according to the image processing method of the present invention, in a method of storing video signals for one field in a memory means, a first luminance signal and a color difference signal are generated from a first input video signal, and a second luminance signal and a color difference signal are generated. From the input video signal
Video signal processing for generating a first luminance signal, a first compression processing for compressing the first luminance signal to a predetermined data amount, and a second compression processing for compressing the second luminance signal to a predetermined data amount. And a third compression process for compressing the color difference signal into a predetermined data amount. The sum of the data amounts of the signals compressed by the first to third compression processes is stored in the memory means. The compression ratio in each of the compression processes is set so as to be smaller than the capacity.

Another feature of the image processing method of the present invention is that each of the first luminance signal and the second luminance signal is compressed to 5 bits, and the color difference signal is compressed to 2 bits. It is characterized by:

Another feature of the image processing method according to the present invention is that the first input video signal and the second input video signal are video signals output from an image pickup device of an all-pixel readout system. The first input video signal and the second input video signal form a frame signal without blur.

Another feature of the image processing method of the present invention is that the second input video signal is the first input video signal.
The input video signal is a video signal delayed by a predetermined time, and the memory means is controlled to write the compressed video signal intermittently.

Another feature of the image processing method of the present invention is that a first compression process for compressing a luminance signal of the first input video signal to a predetermined data amount and a second input video signal. A second compression process of compressing the luminance signal of the first input video signal to a predetermined data amount, a third compression process of compressing the color difference signal of the first input video signal to a predetermined data amount, and the first compression process. Field memory means for recording the performed luminance signal, the luminance signal subjected to the second compression processing, and the color difference signal subjected to the third compression processing, and read from the field memory means. A luminance signal decompression process for decompressing the compressed luminance signal, a color difference signal decompression process for decompressing the compressed chrominance signal read from the field memory means, and converting the first luminance signal and the second luminance signal for each field. Switch to It is characterized by sequentially performing the selection process of force.

Further, the storage medium of the present invention is characterized in that a program for causing a computer constituting each function of the image processing apparatus to function is stored.

Another feature of the storage medium of the present invention is that a program for causing a computer to execute the procedure of the image processing method is stored.

Since the present invention has the above-mentioned technical means, the color difference signal which is unlikely to cause image quality deterioration even if the information amount is reduced is stored in only one field in the memory means, so that the information amount of the luminance signal can be reduced. By increasing the number as much as possible, it is possible to perform high-quality image display using the field memory.

According to another feature of the present invention, the compression ratio of the luminance signal and the compression ratio of the chrominance signal can be made arbitrarily different from each other. Accordingly, the compression ratio of the luminance signal can be reduced, so that the image quality can be improved.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of an image processing apparatus, an image processing method, and a storage medium according to the present invention will be described with reference to FIG. In the first embodiment,
1 shows a configuration of a circuit that can perform an electronic zoom process, a still image display process, and the like based on a video signal output from an image pickup device of an all-pixel readout method.

In FIG. 1, reference numeral 2 denotes an all-pixel readout solid-state imaging device, and reference numerals 4 and 6 denote an AD for converting an analog output signal from the solid-state imaging device 2 into a digital signal.
The conversion means 8 is a camera process circuit that performs predetermined signal processing on the digitally converted output signal of the image sensor 2 and outputs a video video signal from two output terminals. The camera process circuit 8 constitutes a video signal processing unit.

Reference numeral 10 denotes first compression means for compressing a luminance signal of a first output signal of the camera process circuit 8, and reference numeral 12 denotes a third compression means for compressing a color difference signal of the first output signal of the camera process circuit 8. The compression means 14 is a first compression means 14 for compressing the luminance signal of the second output signal of the camera process circuit 8.

Reference numeral 16 denotes memory means for recording the output signal of the first compression means 10, the output signal of the first compression means 14, and the output signal of the third compression means. Reference numeral 18 denotes memory control means for controlling the memory means 16.

A switch circuit 11 selects either the output signal of the first compression means 10 or the signal passed through the first compression means 10.

Reference numeral 20 denotes first decompression means for decompressing the output signal of the first compression means 10 read from the memory means 16 to the original bit length, and reference numeral 24 denotes data read from the memory means 16. Second expansion means for expanding the output signal of the second compression means 14 to the original bit length,
2 is a third signal for expanding the output signal of the third compression means read from the memory means 16 to the original pit length.
Means for elongation.

Reference numeral 21 denotes a switch circuit for selecting one of the output signal of the first expanding means 20 and the signal passed through the first expanding means 20.

Reference numeral 26 denotes switch means for switching and outputting the output signal of the switch circuit 21 and the output signal of the switch circuit 25 for each field, and 28 modulates a color difference signal which is an output signal of the third expansion means. This is a modulation means for outputting the data.

Next, the operation of the image processing apparatus according to the present embodiment based on the above configuration will be described. The solid-state image pickup device 2 (hereinafter referred to as a CCD) of the all-pixel readout method has two output terminals, and outputs a CC signal every time corresponding to one field.
A signal corresponding to the odd line of D and a signal corresponding to the even line are output.

These signals are supplied to AD converters 4 and 6 and converted into digital signals. The digitally converted CCD output signal is input to a camera process circuit 8 and subjected to camera signal processing such as color separation processing and gamma processing, and then, as a first output signal and a second output signal, a subsequent circuit. Is output to The first output signal and the second output signal form a frame image.

As a compression method performed by the first compression means 10 for compressing the brightness signal of the first output signal output from the camera process circuit 8, a technique such as DPCM compression or DCT compression is considered. can do. In the present embodiment, an 8-bit input luminance signal is compressed to 5 bits by using DPCM compression which can be realized by a relatively small-scale circuit. Note that when the 8-bit input luminance signal is compressed to 4 bits, a level at which edge business, granular noise, and the like are concerned becomes a problem.

The color difference signal of the first output signal output from the camera process circuit 8 is applied to a third compression means 12 and compressed. Usually, since the color difference signal has a narrower signal band than the luminance signal, the sampling frequency is often set to 1/4 of the luminance signal, and the 8-bit color difference signal is stored in the memory in the upper 4 bits and lower 4 bits. The data is separated into bits and time multiplexed, and recorded as 4 bits.

On the other hand, the third compression means 12 in the present embodiment compresses the RY signal / BY signal of the color difference signal from 8 bits to 4 bits. Next, the compressed 4-bit RY signal / BY signal is separated into upper 2 bits and lower 2 bits and subjected to time multiplexing processing to be compressed into a 2-bit color difference signal. Then, the color difference signal compressed to 2 bits is recorded in the memory means 16.

The second compression means 14 compresses the luminance signal of the second output signal of the camera process circuit 8, and the second compression means 14 and the third compression means 1
2 has the same configuration as the first compression means 10.

The first to third compression means 10, 12, 1
The video signal compressed in 4 is recorded in the memory means 16. This memory means 16 has a capacity enough to record a video signal for one field.

Normally, an 8-bit luminance signal and a time-multiplexed 4-bit color difference signal are recorded in 12 bits. However, in the image processing method of the present embodiment, the first compression means is used. 10, a first luminance signal compressed to 5 bits by the second compression means 14, a second luminance signal compressed to 5 bits by the second compression means 14, and a first luminance signal compressed to 2 bits by the third compression means 12. Color difference signal is 5
It is recorded as a video signal of + 5 + 2 = 12 bits.

That is, in the case of the present embodiment, the color difference signal which does not easily cause the image quality deterioration even if the information amount is reduced is stored in the memory means for only one field, and the information amount of the luminance signal is reduced. By increasing the number as much as possible, high-quality image display can be performed using the field memory.

Since the compression ratio of the luminance signal and the compression ratio of the chrominance signal can be made arbitrarily different from each other, the compression ratio of the chrominance signal which does not easily deteriorate the image quality can be increased. To improve the image quality.

The memory control means 18 is provided with the memory means 1
A control signal is generated for controlling the read address 6 and the read address is controlled at the time of enlargement processing, and the write address is controlled at the time of still image display.

The output of the first compression means 10 is provided to a first input terminal of a switching circuit 11. A signal bypassing the first compression means 10 is input to a second input terminal of the switching circuit 11.

With the above-described configuration, in the case of the still image display mode, the first to third compression means 10, 12, and 14 are used.
Is selected, and in a normal mode, a video signal that bypasses the first compression unit 10 is selected.

The signal read from the memory means 16 is applied to a first decompression means 20, a second decompression means 24 and a third decompression means 22, respectively. , 12, and 14 are expanded to the original video signals.

That is, the first expanding means 20 and the second expanding means 22 expand the luminance signal compressed to 5 bits to 8 bits. Further, the third decompression means 22 separates the time-multiplexed and compressed 2-bit signal into 4 bits first, and further decompresses the 4-bit color difference signal into 8 bits.

The switch means 26 is connected to the first extension means 20.
The interlaced signal is generated and output by switching, for each field, the first luminance signal decompressed by the first luminance signal and the second luminance signal decompressed by the second decompression means 24.

Here, since the video signal read from the memory means 16 is a video signal output from the image pickup device 2 of the all-pixel reading system, the first luminance signal is an odd line (even line) of the frame video signal. And the second luminance signal is a signal of an even line (odd line). In the present embodiment, these video signals are switched for each field to generate an interlace signal.

On the other hand, the chrominance signal is not significantly degraded in picture quality even if the resolution in the vertical direction on the screen is lower than that of the luminance signal. Therefore, the chrominance signal for one field output from the third decompression means 22 is directly modulated. The means 28 performs a modulation process and then outputs it as a chroma signal.

In such a configuration, when the writing to the memory means 16 is prohibited and the signal recorded in the memory means 16 is controlled to be read continuously, the output from the image processing apparatus of the present embodiment is obtained. Since the luminance signal of the video signal is a frame signal without blur, a high-definition still image display image can be obtained.

As shown in FIG. 2, the enlargement processing means 30 is provided after the first expansion means 20 and the second expansion means 24.
Is provided, and enlargement processing means 32 is provided after the third decompression means 22. Enlargement processing is performed using the luminance signal output from the first decompression means 20 and the luminance signal output from the second decompression means 24. If this is done, interpolation processing can be performed using pixels with a narrow pixel interval in the vertical direction, so that a higher quality enlarged image can be obtained.

By the way, in the all-pixel image pickup device 2, one frame image is generated in one field period, but the recording device can record only one field of image data in one field period.

Therefore, in the normal moving image mode, only one of the first video signal and the second video signal is output, so that one field of image data is output in one field period. I have to.

That is, in the normal moving image mode, the first video signal passed through the first compression means 10 is selected by the switch circuit 11 and input to the memory means 16. In this case, the first video signal includes both the luminance signal and the color difference signal, and the video signal written into the memory means 16 is only the first video signal.

In the moving image mode, the memory means 16
The first video signal read from the first
0, which is directly supplied to one input terminal of the switch circuit 21 and the first video signal supplied to the one input terminal is selected and output to the next circuit via the switch means 26. You.

(Second Embodiment) Next, a second embodiment of the image processing apparatus of the present invention will be described with reference to FIG. The image processing apparatus according to the second embodiment has a circuit configuration for performing multi-screen display in which an input image is reduced to 、 or １ ／ and a plurality of images are displayed side by side. In FIG. 3, a switch circuit for selecting a signal in a normal mode is omitted.

In FIG. 3, reference numeral 42 denotes LPF means for subjecting the input digital video signal to low-pass filtering, 44 denotes first thinning means for thinning out the output signal of the LPF means 42 at a predetermined rate, and 46 denotes the LPF means. A delay means for delaying the output signal of the delay means by a predetermined time, for example, 1 to 4 horizontal synchronization periods, and a second thinning means for thinning out the output signal of the delay means at a predetermined rate. Since the configuration and operation of the circuits from the first compression unit 10 to the modulation unit 28 are the same as the configuration and operation of the circuit of FIG. 1 described above, detailed description is omitted here.

Next, each operation will be described.
Note that the input digital video signal is a digital signal such as a luminance signal or an RGB component signal, and is not particularly limited. Since the input digital signal is thinned out in the horizontal direction and the vertical direction, a low-pass filter process is performed in the LPF means 42 in advance to prevent aliasing noise from occurring.

The filtered signal is applied to first thinning means 44 and delay means 46. And
In the first thinning means 44, a first thinning process is performed. The thinning process performed here is a process of thinning out one pixel every two pixels in the horizontal direction in the case of four-screen multi-screen display. In the case of 9-screen multi-screen display, the process is to thin out 2 pixels every 3 pixels.

The signal decimated by the first decimation unit 44 is output to the memory unit 16 after the bit length of the luminance signal is compressed from 8 bits to 5 bits by the first compression unit 10. The color difference signal is compressed by the third compression unit 12 from 8 bits to 4 bits in length, then converted from 4 bits to 2 bits by time multiplexing, and output to the memory unit 16.

On the other hand, the signal given to the delay means 46 is
Here, the horizontal synchronization period is delayed by 1 to 4H. For example, the delay time varies depending on the display mode, such that the display time is delayed by 1H during the 4-screen multi-screen display and the 9-screen multi-screen display, and is delayed by 2H during the 16-screen multi-screen display.

The video signal delayed by the predetermined time by the delay means 46 is subjected to the process of thinning out the pixels of the video signal in the second thinning means 48 in the same manner as the first thinning means 44. The signal decimated by the second decimation unit 48 is output to the memory unit 16 after the bit length of the luminance signal is compressed from 8 bits to 5 bits by the second compression unit 14.

The 5-bit compressed luminance signal output from the first compression means 10, the 5-bit compressed luminance signal output from the second compression stage 14, and the 2-bit compressed luminance signal output from the third compression means. The bit compressed color difference signal is recorded as a 12-bit video signal in the memory unit 16 in synchronization with the thinning process.

The read control of the memory means 16 and the operation of the decompression means are the same as those in the first embodiment, and therefore detailed description is omitted. However, the luminance signal output from the first decompression means 20 and the second Since the luminance signal output from the expansion means 24 has a relationship of constituting a frame signal, a multi-screen display process with a high vertical resolution can be performed by outputting an interlace signal by switching every field.

(Other Embodiments of the Present Invention) The present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), but is also applicable to an apparatus composed of one device. You may.

Further, in order to realize various functions so as to realize the functions of the above-described embodiments, the functions of the above-described embodiments are realized by an apparatus connected to the various devices or a computer in a system. The present invention also includes a program that is implemented by supplying the program code of the software described above and operating the various devices according to a program stored in a computer (CPU or MPU) of the system or apparatus.

In this case, the program code of the software implements the functions of the above-described embodiment, and the program code itself and means for supplying the program code to the computer are provided.
For example, a storage medium storing such a program code constitutes the present invention. As a storage medium for storing such a program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM,
A magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the supplied program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) or other operating system running on the computer. It goes without saying that such program codes are also included in the embodiments of the present invention when the functions of the above-described embodiments are implemented in cooperation with application software and the like.

Further, after the supplied program code is stored in a memory provided in a function expansion board of a computer or a function expansion unit connected to the computer, the function expansion board or the function expansion unit is operated based on the instruction of the program code. It is needless to say that the present invention also includes a case where a CPU or the like provided in the first embodiment performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0073]

According to the present invention, as described above, according to the present invention, a first luminance signal and a color difference signal are generated from a first input video signal, and a second luminance signal and a color difference signal are generated from a second input video signal.
The first luminance signal, the color difference signal,
And when the second luminance signal is compressed by the compression means, the compression ratio of each compression means can be individually set so that the total data amount of each signal is smaller than the storage capacity of the memory means. Therefore, by storing only one field of the color difference signal in which the image quality is unlikely to be degraded even if the information amount is reduced, the information amount of the luminance signal can be increased as much as possible. It is possible to perform high-quality image display by using this.

According to another feature of the present invention, the compression ratio of the luminance signal and the compression ratio of the chrominance signal can be arbitrarily made different from each other. The compression ratio of the luminance signal can be reduced accordingly, and the image quality can be further improved.
As a result, a high-quality frame image with less distortion due to compression can be obtained using a relatively inexpensive compression circuit or an inexpensive field memory without using an expensive frame memory or an expensive compression circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a configuration of an image processing apparatus according to a first embodiment.

FIG. 2 is a configuration diagram illustrating a configuration of an enlargement processing circuit according to the first embodiment;

FIG. 3 is a configuration diagram illustrating a configuration of an image processing apparatus according to a second embodiment;

FIG. 4 is a configuration diagram illustrating a configuration of a conventional image processing circuit.

FIG. 5 is a diagram showing an operation state of a conventional multi-screen display.

[Explanation of symbols]

 Reference Signs List 2 solid-state imaging device 4 AD conversion means 6 AD conversion means 8 Camera process circuit 10 First compression means 12 Third compression means 14 Second compression means 16 Memory means 18 Memory control means 20 First decompression means 22 Third Expansion means 24 second expansion means 26 switch means 28 modulation means 42 LPF means 44 first thinning means 46 delay means 48 second thinning means 62 LPF means 64 thinning means 66 first memory means 68 second memory Means 70 Memory control means 72 Switching means

Claims (12)

[Claims] 1. An image processing apparatus having memory means capable of recording a video signal for one field, wherein a first luminance signal and a color difference signal are generated from a first input video signal, and a second input video signal is generated. Video signal processing means for generating a second luminance signal from the image signal; first compression means for compressing the first luminance signal to a predetermined data amount; and compressing the second luminance signal to a predetermined data amount. A second compression unit, and a third compression unit for compressing the color difference signal to a predetermined data amount, wherein a sum of data amounts of the respective signals compressed by the first to third compression units is An image processing apparatus, wherein a compression ratio of each compression unit is set so as to be smaller than a storage capacity of a memory unit. 2. The image processing apparatus according to claim 1, wherein the first and second luminance signals are compressed to 5 bits, and the color difference signal is compressed to 2 bits. 3. The image processing apparatus according to claim 1, wherein the first input video signal and the second input video signal are video signals output from an imaging device of an all-pixel readout method, and An image processing apparatus, wherein the first input video signal and the second input video signal form a frame signal without blur. 4. The image processing apparatus according to claim 1, wherein said second input video signal is a video signal obtained by delaying said first input video signal by a predetermined time, and said compressed video is stored in said memory means. An image processing apparatus for performing control to write a signal intermittently. 5. A first compression means for compressing a luminance signal of a first input video signal to a predetermined data amount, and a second compression means for compressing a luminance signal of a second input video signal to a predetermined data amount. Means, third compression means for compressing the color difference signal of the first input video signal to a predetermined data amount, output signal of the first compression means, output signal of the second compression means, Field memory means for recording the output signal of the third compression means, first and second decompression means for expanding the compressed luminance signal read from the field memory means, read from the field memory means Third expanding means for expanding the compressed chrominance signal thus obtained, a first luminance signal expanded by the first expanding means, and a second luminance signal expanded by the second expanding means. Switch and output every time An image processing apparatus comprising: 6. A method of storing a video signal for one field in a memory means, wherein a first luminance signal and a color difference signal are generated from a first input video signal, and a second luminance signal and a color difference signal are generated from a second input video signal. Video signal processing for generating a luminance signal; first compression processing for compressing the first luminance signal to a predetermined data amount; and second compression processing for compressing the second luminance signal to a predetermined data amount. And a third compression process for compressing the chrominance signal to a predetermined data amount. The sum of the data amounts of the signals compressed by the first to third compression processes is the storage capacity of the memory means. An image processing method, wherein a compression ratio in each of the compression processes is set so as to be smaller than the above. 7. The image processing method according to claim 6, wherein each of the first luminance signal and the second luminance signal is compressed to 5 bits, and the color difference signal is compressed to 2 bits. 8. The image processing method according to claim 6, wherein the first input video signal and the second input video signal are video signals output from an imaging device of an all-pixel readout method, and An image processing method, wherein the first input video signal and the second input video signal form a frame signal without blur. 9. The image processing method according to claim 6, wherein the second input video signal is a video signal obtained by delaying the first input video signal by a predetermined time, and the compressed video is stored in the memory unit. An image processing method characterized by performing control of writing a signal intermittently. 10. A first compression process for compressing a luminance signal of a first input video signal to a predetermined data amount, and a second compression process for compressing a luminance signal of a second input video signal to a predetermined data amount. Processing, a third compression processing for compressing the color difference signal of the first input video signal into a predetermined data amount, a luminance signal subjected to the first compression processing, and a second compression processing. Field memory means for recording the obtained luminance signal and the color difference signal subjected to the third compression processing; luminance signal decompression processing for decompressing the compressed luminance signal read from the field memory means; A color difference signal decompression process for decompressing the compressed color difference signal read from the memory means, and a selection process for switching and outputting the first luminance signal and the second luminance signal for each field. Image processing Method. 11. A storage medium storing a program for causing a computer to function as each of the means according to claim 1. Description: 12. A storage medium storing a program for causing a computer to execute the procedure of the image processing method according to claim 6. Description: