JPH1066095A - Method for converting non-interlacing/interlacing and picture input device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to convert a non-interlaced picture signal into an interlaced picture signal without using a frame memory by compositing picture signals read out from plural line memories for storing data by prescribed writing frequency and prescribed line order under a specific condition and converting the composite picture signal into a chrominance signal. SOLUTION: A picture signal outputted from an overall pixel reading type CCD 101 is A/D converted and the digital signal is temporarily stored in a line memory part 104 in each line. A switching part 106 switches the connection of signal lines between respective line memories 104a to 104d and a signal processing circuit 107 based on a selection signal outputted from a memory control part 105 and the circuit 107 executes various picture processing for inputted picture signals. In the case of composite picture signals read out from n line memories as a single signal and converting the composite output signal into a chrominance signal, FR=FW/n is formed when writing frequency is FW and reading frequency is FR.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-interlace / interlace conversion method and an image input apparatus, and more particularly to a non-interlace image signal picked up using a CCD of an all-pixel read-out method, via a memory. The present invention relates to a non-interlace / interlace conversion method for converting an image signal into an image signal and an image input device.

[0002]

2. Description of the Related Art Raster scan type display devices are roughly divided into scanning of even-numbered scanning lines (lines) in a first cycle, and scanning of odd-numbered scanning lines existing therebetween in the next cycle. There are an interlaced type (interlaced scanning type) in which scanning is performed, and a non-interlaced type (sequential scanning type) in which all scanning lines are sequentially scanned in one cycle. Specifically, for example, a monitor device compatible with the NTSC system (a general television or the like) as an interlace system, and a monitor device compatible with a VGA system (a display device of a personal computer or the like) as a non-interlace system. There is.

On the other hand, as an image input device for capturing an image of a subject using a CCD and converting the captured image of the subject into an image signal, a device using a CCD of a field storage readout system corresponding to the above-mentioned interlace system, One using an all-pixel readout CCD corresponding to the non-interlace method is provided.

[0004] In the CCD of the field storage readout system (interlace system), signal charges of two adjacent vertical pixels are mixed in the vertical CCD, and 262.5 TV lines are read per field (that is, with one exposure). Since the image input device is designed to output a signal, the image input device using the CCD has two lines consisting of 262.5TV scanning lines.
One field (one screen) is created by interlacing two fields 2: 1. Therefore, this CC
In the case of a still image, the vertical resolution in D is only 240 TV lines, which is insufficient for use in the fields of image measurement, image processing, and still image.

[0005] Further, the CCD of the all-pixel readout system (non-interlace system) reads out all pixels as they are without mixing signals in a vertical CCD, and one frame is read out in one field period (1/60 second). By reading image information of (one screen), a vertical resolution (480 TV lines) twice as high as that of the interlaced system is achieved. Therefore, a vertical resolution sufficient for use in the fields of image measurement, image processing, and still images can be obtained.

For this reason, an image input device using a CCD of the all-pixel readout type (non-interlace type) is used in the next stage device when it is necessary to perform various types of image processing on input image information. . For example, it is used in image input cameras of personal computers and digital cameras.

Further, as one of the image input devices using such an all-pixel readout (non-interlaced) CCD, a non-interlaced image signal input by the CCD is temporarily stored in a frame memory for one image (about one frame). 6
(M bits), then even (or odd)
There is provided an apparatus for converting a non-interlaced image signal into an interlaced image signal and reading out by thinning out and reading out the lines. This converts the non-interlaced image signal input using the all-pixel readout CCD into an interlaced image signal,
It can be output to a monitor device compatible with the C system.

[0008]

However, according to the above-mentioned prior art, since the thinning process is executed via the frame memory and the conversion from the non-interlaced image signal to the interlaced image signal is performed, one screen is required. Therefore, a frame memory having a memory capacity (approximately 6 Mbits) corresponding to the number of pixels is required, and there is a problem that the apparatus cost increases.

The present invention has been made in view of the above, and has as its object to reduce the apparatus cost by converting a non-interlaced image signal into an interlaced image signal without using a frame memory. And

[0010]

According to a first aspect of the present invention, there is provided a non-interlace / interlace conversion method, comprising the steps of storing a non-interlace image signal picked up using a CCD of an all-pixel readout method in a memory. In the non-interlace / interlace conversion method of converting to an interlaced image signal through an interlaced image signal, an image signal captured by using the all-pixel readout CCD is temporarily stored in an even number of line memories at a predetermined writing frequency and in line order. A first step of simultaneously reading image signals from a plurality of line memories of the even number of line memories at a predetermined read frequency different from the write frequency; and a step of reading image signals read from the plurality of line memories. A second step of combining into a single signal, and the second step The output signal, and a third step of converting the output signal to a color signal, the predetermined write frequency F _W, the predetermined read frequency F _R, the plurality in the case of n , F _R = F _W / n.

According to a second aspect of the present invention, there is provided an image input apparatus for capturing an image of an object using a CCD of an all-pixel readout system and converting the image of the imaged object into an image signal. Drive control means for controlling the A / D conversion, an A / D conversion means for converting an analog image signal from the CCD into a digital image signal, and a plurality of means for temporarily storing the digital image signal converted by the A / D conversion means in line units. Memory control means for controlling writing and reading of the digital image signal to and from the plurality of line memories in cooperation with the CCD drive control means; and at least two lines of the plurality of line memories Digital image signals are simultaneously inputted from the memory, and the digital image signals of the at least two line memories are used. A first signal processing means for performing RGB color separation and data interpolation and synthesizing and outputting as an output signal for one line, and an output signal of the first signal processing means, and converting the output signal into a color signal A second signal processing unit, wherein the memory control unit controls writing and reading of the digital image signal by changing a writing frequency and a reading frequency for the plurality of line memories.

According to a third aspect of the present invention, in the image input apparatus according to the second aspect, the plurality of line memories include four line memories, and the first signal processing means includes two line memories. Digital image signals are simultaneously input from the line memories.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a non-interlace / interlace conversion method and an image input apparatus according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic block diagram of an image input apparatus according to the present embodiment.
1, a timing generating circuit 102 as a CCD drive control means for controlling the driving of the CCD 101, generating a clock for operation timing and a synchronizing signal and outputting the generated signal to each section of the device, and converting an analog image signal from the CCD 101 into a digital image signal. A / D as A / D conversion means for conversion
A line memory unit 10 having a D converter 103 and a plurality of line memories 104a to 104d for temporarily storing the digital image signals converted by the A / D converter 103 in line units.
4 and a memory control unit 105 that controls writing and reading of digital image signals to and from the line memories 104a to 104d in conjunction with the timing generation circuit 102.
And the line memories 104a to 104d and the next-stage signal processing circuit 1 based on a selection signal from the memory control unit 105.
A switching unit 106 that switches the connection of the signal line to the switching unit 07 and a signal processing circuit 107 that performs various image processing on the digital image signal input via the switching unit 106.

The signal processing circuit 107 simultaneously receives digital image signals from two of the line memories 104a to 104d in accordance with the connection of the signal lines by the switching unit 106, as shown in FIG. A pre-signal processing circuit 10 as first signal processing means for performing RGB color separation and data interpolation using a digital image signal of a line memory and synthesizing and outputting as an output signal for one line
8, a post-signal processing circuit 109 as a second signal processing means for inputting an output signal of the pre-signal processing circuit 108 and converting the output signal into a color signal, and for performing compression processing and decompression processing of an image signal. Image compression / decompression circuit 110.

Further, the memory control unit 105 and the switching unit 1
06 constitutes the memory control means of the present invention. Although details will be described later, the memory control unit 105 controls the writing and reading of the digital image signal by making the writing frequency and the reading frequency for the line memories 104a to 104d different.

Here, an example is shown in which the line memory unit 104 is composed of four line memories 104a to 104d, but the present invention is not particularly limited to this.

FIG. 2 shows a pre-signal processing circuit 1 according to this embodiment.
08 and a block diagram of the post-signal processing circuit 109.

The pre-signal processing circuit 108 includes a color separation / interpolation circuit 201, a gain 202, a gain 203, and a γ correction unit 204.

In the color separation interpolation circuit 201, two lines of CCs read from the line memories 104a to 104d are read.
The R, G, and B signals are separated from the D data (digital image signal), and the R, G, and B signals are separated for every pixel (for example, 310,000 pixels).
・ The G / B data is interpolated to determine the R signal in pixel units,
A G signal and a B signal are generated. The gains 202 and 203 receive the R signal or the B signal output from the color separation / interpolation circuit 201, and adjust the white balance corresponding to the color temperature of the light source of the subject with respect to the R signal or the B signal.
The γ correction unit 204 performs TV γ curve correction on each of the R, G, and B signals.

Although not shown, the CDS data OB pedestal adjustment circuit arranged before the color separation / interpolation circuit 201 converts the input image signal (CDS 10-bit data) into the black area OB of the CCD.
(Optical Black) Obtained by averaging the level, OB
The level shall be clamped by subtraction. As a result, the phenomenon of black level floating in the analog circuit can be suppressed.

The post signal processing circuit 109 includes a matrix circuit 205, an aperture correction circuit 206, a line memory 206a, gains 207 and 208, LPFs (low-pass filters) 209 and 210, and gains 211 to 2
13, an encoder 214, and a D / A converter 215.

The matrix circuit 205 converts the RGB signal into a YUV signal for DCT compression using a linear fixed matrix. Further, the following matrix operation is performed from the RGB signals to obtain a color difference signal. Y = 0.299R + 0.587G + 0.114B R−Y = 0.701R−0.587G−0.114B BY = −0.299R−0.587G + 0.886B The luminance signal (Y) obtained here and the color difference Signal (RY, B
-Y), the luminance signal (Y) is passed through the LPF to remove high-frequency components. Further, the color difference signals (RY, B-
Y) LPF on Saturday (LPF with a band of about 1.5 MHz)
To remove high frequency components. Incidentally, since the color difference signals R-Y C _R, a color difference signal B-Y to as C _B.

The aperture correction circuit 206 enhances the resolution of the image by enhancing the outline of the image. First,
An aperture component is extracted from the luminance signal output from the matrix circuit 205 by the HPF, and the aperture component is added to the input luminance signal to perform aperture correction. Note that the data is delayed by several pixels in the horizontal direction, and the contour components are extracted by the line memory 206a in the vertical direction.

In the gains 207 and 208, UV gain adjustment is performed. That is, gain adjustment is performed on the UV signal of the YUV signal converted by the matrix circuit 205 to adjust the color density. The UV signal after gain adjustment is
The LPFs 209 and 210 respectively (1,4,11,1
5, 11, 4, 1).

In the gains 211 to 213, the luminance signal Y output from the aperture correction circuit 206 and the LPF
Gain adjustment is performed on the color difference signals C _R and C _B passed through 209 and 210.

[0027] In the encoder circuit 214, preceding the signal processed color difference signals C _R, a C _B was balanced modulation with 3.58 MHz, and outputs a modulated chroma signal.

The D / A converter 215 converts the digitally encoded signal into an analog signal and outputs it. D /
Output as an analog signal by the A converter 215,
The output signal of the luminance signal Y and one of the modulated chroma signals is
Images can be viewed on a television screen by connecting to a C-type monitor TV (not shown).

On the other hand, the luminance signal Y and the color difference signals C _R and C _B that have passed through the gains 211 to 213 are taken into the image compression / expansion circuit 110 and subjected to signal image compression to perform recording on a recording medium (not shown) such as a memory card. ), An image can be taken with a digital camera or the like.

FIG. 3 shows a CCD 10 of an all-pixel reading system.
FIG. 2 is an explanatory diagram showing an example of the arrangement of color filters for each pixel in FIG. Here, an array called a Bayer array is used as an example of the color filter array of the CCD 101. As shown in the drawing, in such an arrangement of pixel filters, by simultaneously reading out two lines as in the present embodiment, the input pixel (2 pixels) at a certain time and the previous pixel (2 pixels) are combined. R, G, B in the signal processing circuit 107
Can be read at the same time.

Next, referring to FIG.
1 to read out the image signals from the line memories 104a-1
Synchronization signal and line memory 1 until writing to 04d
The synchronization signals after 04a to 104d will be described. In this embodiment, the vertical synchronization signal of the image signal is 1
/ 60 seconds. Here, only the horizontal synchronization signal will be described.

In the reading of the CCD 101, 480 lines are read in 1/60 seconds (that is, 1/60 seconds of the vertical synchronizing signal). Therefore, the horizontal synchronization signal is 32 μS
(1/60 sec / 480 lines / 32 μS). In the present embodiment, as shown in FIG.
1 is converted into a digital image signal by the A / D converter 103, and a horizontal synchronization signal from the time of writing to the line memory unit 104 of the line memory unit 104 is 32.
μS.

On the other hand, the horizontal synchronizing signal for reading the image signal from the line memories 104a to 104d of the line memory unit 104 and the horizontal synchronizing signal in the subsequent signal processing are converted into the image signal processed horizontal synchronizing signal of FIG. As shown, it is 64 μS.

FIG. 4B is an explanatory diagram showing the timing of writing and reading image signals to and from each line memory of the line memory section. A read signal (digital image signal after passing through the A / D converter 103) from the CCD 101 is sequentially written into the four line memories 104a to 104d. The writing frequency at this time is 24.54.
Write in MHz.

For example, at the timing of the horizontal synchronizing signal shown in FIG. 4A, as shown in FIG. 4B, the line memory 104a has a write frequency of 24.54 MHz.
The image signal for one line is written in the line memory 104b, and the image signal for one line is written in the line memory 104b at the next timing.
Image signals for one line are written into 4c and 104d.

On the other hand, reading of image signals from the line memories 104a to 104d is performed by using two line memories (10
4a, 104b and two 104c, 104d)
Are read out at the same time, and the image signals read out here are input to the pre-signal processing circuit 108 two pixels at a time.
The read frequency at this time is 1 which is half of the write frequency.
2.27 MHz.

For example, at the timing of the horizontal synchronizing signal shown in FIG. 4A, as shown in FIG.
Image signals are simultaneously read from two lines c and 104c, and image signals are simultaneously read from two line memories 104a and 104b at the next timing. The image signals read in two lines from the line memory unit 104 at the same time are input to the pre-signal processing circuit 108 at 12.27 MHz via the signal lines switched and connected by the switching unit 106.

As shown in FIG. 4B, by writing and reading image signals to and from each of the line memories 104a to 104d of the line memory unit 104, C
The image signal of 480 lines from the CD 101 is 1/60
It can be read in seconds (ie, 1/60 second vertical synchronization signal). In the signal processing circuit 107, 1/6
During 0 seconds, image signals for 240 lines are processed,
Is output.

In this embodiment, the write frequency is 24.54 MHz and the read frequency is 12.27 MH.
Although it is set to z, the present invention is not particularly limited to this. If the write frequency is F _W , the read frequency is F _R , and the number of line memories in the line memory unit 104 is n, then F _R = F _W / n It is only necessary to establish a relationship.

The operation of the above configuration will be described. The CCD 101 of the all-pixel readout method uses the vertical synchronizing signal (1/60 second) and the horizontal synchronizing signal (32 μS) from the timing generation circuit 102 and the clock of the CCD reading frequency (24.54 MHz) to capture the image of the subject. An image (analog image signal) is line-sequentially A /
Output to the D converter 103.

The A / D converter 103 has a frequency of 24.54 MHz.
The input analog image signal is converted into a digital image signal based on the clock of
Output to 4.

The memory control unit 105 includes the A / D converter 10
3 is temporarily stored in the line memories 104a to 104d at the writing frequency (24.54 MHz) and in line order based on the vertical synchronizing signal (1/60 second) and the horizontal synchronizing signal (32 μS). Remember. At the same time, based on the vertical synchronizing signal (1/60 second) and the horizontal synchronizing signal (64 μS), the line memories 104 a to 104 are read at the read frequency (12.27 MHz).
Digital image signals are simultaneously read from two line memories out of the line memories d and transferred to the signal processing circuit 107 via the switching unit 106 (first step of the present invention).

The digital image signal sent to the signal processing circuit 107 is first input to the pre-signal processing circuit 108.
In the pre-signal processing circuit 108, the color separation interpolation circuit 201
RGB color separation and data interpolation are performed using the CCD data for one line (digital image signals read from two line memories), and the output signal for one line (RG
(B signal) are combined and output (second step of the present invention).

Subsequently, the white balance is adjusted by the gains 202 and 203, the γ correction unit 204 performs the γ curve correction of the TV for each of the R, G, and B signals. An output signal (RGB signal) for one line is output to the signal processing circuit 109.

The post signal processing circuit 109 includes a matrix circuit 205, an aperture correction circuit 206, a line memory 206a, gains 207 and 208, and LPFs 209 and 2.
10, the gain signals 211 to 213, the encoder 214, and the D / A converter 215 convert the output signal (RGB signal) into a color signal (luminance signal Y, color difference signals C _R and C _B ) ( Third step of the present invention).

As described above, according to the present embodiment, 480 vertical signals are read out from the CCD 101 of the all-pixels reading method in 1/60 second, and the line memories 104a to
104d and temporarily store them in the line memories 104a to 104d.
4d, two lines (two lines) are simultaneously read out, synthesized and output as an output signal (R, G, B signal) for one line by the pre-signal processing circuit 108, and further output by the post-signal processing circuit 109. G, B signals) are converted to color signals (luminance signals Y,
Since they are converted into color difference signals C _R and C _B ), 240 processed color signals are output in 1/60 second. In other words, since 480 non-interlaced image signals are converted into 240 interlaced image signals and output, the image can be confirmed by taking 240 color signals into an interlaced monitor TV.

That is, without using the frame memory,
Conversion from a non-interlaced image signal to an interlaced image signal can be performed, and the cost of the apparatus can be reduced.

[0048]

As described above, the non-interlace / interlace conversion method of the present invention (claim 1)
In a non-interlace / interlace conversion method for converting a non-interlaced image signal captured using an all-pixel readout CCD to an interlaced image signal via a memory, an image signal captured using an all-pixel readout CCD is A first method of temporarily storing image signals in an even number of line memories at a predetermined write frequency and in line order and simultaneously reading image signals from a plurality of line memories of the even number of line memories at a predetermined read frequency different from the write frequency. A second step of combining image signals read from a plurality of line memories into a single signal; and inputting an output signal of the second step.
And a third step of converting the output signal into a color signal. When a predetermined writing frequency is F _W , a predetermined reading frequency is F _R , and a plurality is n, a relationship of F _R = F _W / n Is satisfied, the conversion from the non-interlaced image signal to the interlaced image signal can be performed without using the frame memory, and the apparatus cost can be reduced.

An image input device according to the present invention (claim 2)
Is a CCD drive control means for controlling the drive of the CCD in an image input device for capturing an image of a subject using an all-pixel readout CCD and converting the image of the captured subject into an image signal, and an analog image from the CCD. A / D conversion means for converting a signal into a digital image signal, a plurality of line memories for temporarily storing the digital image signal converted by the A / D conversion means on a line-by-line basis, and a plurality of A memory control means for controlling writing and reading of a digital image signal to and from a line memory;
A first signal processing means for performing RGB color separation and data interpolation using digital image signals of the line memories and synthesizing and outputting as an output signal for one line, and an output signal of the first signal processing means. And a second signal processing means for converting the output signal into a color signal.
In order to control writing and reading of digital image signals by making the writing frequency and reading frequency for a plurality of line memories different, it is possible to convert non-interlaced image signals to interlaced image signals without using a frame memory. It is possible to reduce the apparatus cost.

An image input device according to the present invention (claim 3)
In the image input device according to the second aspect, the plurality of line memories are composed of four line memories, and the first signal processing means simultaneously inputs digital image signals from the two line memories. The conversion from the non-interlaced image signal to the interlaced image signal can be efficiently performed by the line memory, and the apparatus cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an image input device according to an embodiment.

FIG. 2 is a block diagram of a pre-signal processing circuit and a post-signal processing circuit of the present embodiment.

FIG. 3 is an explanatory diagram showing an example of the arrangement of color filters for each pixel in a CCD of the all-pixel readout method.

FIG. 4A is an explanatory diagram showing a synchronization signal from reading an image signal from a CCD to writing it into a line memory, and a synchronization signal in signal processing after the line memory;
FIG. 2B is an explanatory diagram showing the timing of writing and reading of an image signal to and from each line memory of the line memory unit.

[Explanation of symbols]

 Reference Signs List 101 CCD 102 Timing generation circuit 103 A / D converter 104 Line memory unit 104 a to 104 d Line memory 105 Memory control unit 106 Switching unit 107 Signal processing circuit 108 Pre-signal processing circuit 109 Post-signal processing circuit 110 Image compression / expansion circuit 201 Color separation Interpolation circuit 202, 203 gain 204 gamma correction unit 205 matrix circuit 206 aperture correction circuit 206a line memory 207, 208 gain 209, 210 LPF (low-pass filter) 211-213 gain 214 encoder 215 D / A converter

Claims (3)

[Claims] 1. A non-interlaced / interlaced conversion method for converting a non-interlaced image signal picked up by using an all-pixel readout CCD to an interlaced image signal via a memory, using the all-pixel readout CCD. The captured image signal is temporarily stored in an even number of line memories at a predetermined writing frequency and in line order, and a plurality of line memories of the even number of line memories are stored at a predetermined reading frequency different from the writing frequency. A first step of reading image signals from the plurality of line memories at the same time, a second step of combining image signals read from the plurality of line memories into a single signal,
A third step of receiving the output signal of the second step and converting the output signal into a color signal, wherein the predetermined writing frequency is F _W , the predetermined reading frequency is F _R , A non-interlace / interlace conversion method, wherein the relationship of F _R = F _W / n holds when n is n. 2. An image input apparatus for capturing an image of a subject using a CCD of an all-pixel readout system and converting the image of the captured subject into an image signal, a CCD drive control means for controlling the drive of the CCD, A / D conversion means for converting an analog image signal from a CCD into a digital image signal, a plurality of line memories for temporarily storing the digital image signal converted by the A / D conversion means in line units, and the CCD drive control means Memory control means for controlling writing and reading of the digital image signal to and from the plurality of line memories; and simultaneously inputting digital image signals from at least two line memories of the plurality of line memories, RGB color separation and data interpolation are performed using the digital image signals of the at least two line memories. First signal processing means for combining and outputting as an output signal for one line, second signal processing means for receiving an output signal of the first signal processing means, and converting the output signal into a color signal; An image input apparatus, wherein the memory control means controls writing and reading of the digital image signal by making a writing frequency and a reading frequency for the plurality of line memories different from each other. 3. The image input device according to claim 2, wherein
The image input device, wherein the plurality of line memories include four line memories, and the first signal processing means simultaneously inputs digital image signals from the two line memories.