JP3849230B2 - Signal processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing apparatus suitable for use in an electronic still camera for digital recording, for example.
[0002]
[Prior art]
Recently, digital electronic still cameras are becoming popular. In the case of a digital electronic still camera, a monitor for displaying a photographed image, for example, a liquid crystal monitor is often provided in order to focus at the time of photographing or adjust the camera angle at the time of photographing. In the Japanese Patent Application No. 8-82035, the applicant of the present application has also realized a digital electronic still camera that does not require a VRAM (video RAM) by using an image pickup device of an all-pixel readout method.
[0003]
In Japanese Patent Application No. 8-82035, in a camera signal processing circuit, component signals can be multiplexed by changing clock frequencies, and the bit width of a data bus arranged for subsequent signal processing. One of the effects is that the signal degradation such as crosstalk can be suppressed, the memory size can be reduced, and the power consumption of the memory can be reduced.
[0004]
FIG. 12 shows an example of the configuration of a signal processing device that exhibits this effect, for example, a multiplexer. The multiplexer includes an input selector 151 that selects one of the luminance signal Y and the color signal C, a shift register 152 to which the input selector 151 is supplied as a serial input, a register 153 to which a parallel output of the shift register 152 is loaded, and a register An output selector 154 that sequentially selects data loaded in the output 153 and a register 155 connected to the output selector 154. Each register is 8 bits wide.
[0005]
FIG. 13 is a timing chart showing the operation of the multiplexer described above. 3MCK is a clock three times the frequency of the clock MCK. The luminance signal Y and the color signal C are synchronized with the clock MCK. Since it is a component signal of (411) system, luminance data of 4 samples (for example, Y ₀ , Y ₁ , Y ₂ , Y _Three ) For one sample of red color difference data (eg Cr ₀ ) And one sample of blue color difference data (for example, Cb) ₀ ) Corresponds.
[0006]
The input selector 151 is controlled so that luminance data is selected at the high level of the select pulse and color data is selected at the low level. The shift register 152 is supplied with 3/2 MCK as a clock, takes in data selected by the input selector 151, and shifts in series. Output Q of the first stage register of the shift register 152 ₀ Is Y as shown in the figure _-1 , Y ₀ , Cr ₀ , Y ₁ , Y ₂ , Cb ₀ , Y _Three , ... and changes.
[0007]
The output of the shift register 152 is loaded into the register 153 in parallel with a 1/4 MCK clock timing. The quarter MCK clock period is six times the 3/2 MCK period. The phase of the 1/4 MCK clock is selected so that a total of 6 samples of luminance data and color difference data related to each other are transferred from the shift register 152 to the register 153.
[0008]
The output selector 154 sequentially selects the earliest sample in the register 153 in synchronization with the clock (3 / 2MCK), and the register 155 takes in the selected sample. Therefore, a component signal multiplexed so as to have an order of (Y, Cr, Y, Y, Cb, Y) is generated from the register 155.
[0009]
[Problems to be solved by the invention]
However, in this multiplexer, the timing at which a signal synchronized with the clock frequency MCK is captured at 3/2 MCK is the luminance data Y. ₀ In this case, there is a problem that the margin for the data delay is small because the timing is delayed by 1/3 period of the clock signal having the clock frequency MCK from the sample switching. That is, if the luminance signal Y and the color signal C have a delay with respect to the clock signal with the clock frequency MCK, the data sampled with the 3/2 MCK clock signal is Y ₀ Not necessarily Y _-1 It may occur.
[0010]
In addition, since the output signal from the multiplexer is not output until 6 clocks have elapsed after the data is input, there is a problem that the system delay is large. Furthermore, in order to configure this multiplexer, twelve flip-flops are required, and there is a problem that the circuit scale becomes large.
[0011]
Accordingly, in view of these problems, an object of the present invention is to provide a signal processing apparatus that can reliably capture data when data is transferred to a clock frequency that is 3/2 times the original clock frequency. It is to provide.
[0012]
[Means for Solving the Problems]
According to the first aspect of the present invention, the first sample sequence synchronized with the first clock signal having the first frequency, and (1/2) of the first sample sequence synchronized with the first clock signal. A second sample series having a sampling rate, and an output obtained by synthesizing the first and second sample series synchronized with a second clock signal having a second frequency (3/2) times the first frequency. In a signal processing apparatus configured to generate a sample sequence, a first sample sequence is captured by a second clock signal, a plurality of first registers to be held, and a second sample sequence are captured by a second clock signal A plurality of second registers to be held, outputs from the plurality of first and second registers, an output selector for generating an output sample series, and a selection signal for controlling the output selector. Of the three types of phase relationships between the first clock signal and the second clock signal, excluding the unstable phase relationships of the first and second sample sequences. The signal processing apparatus is characterized in that the sample taken in is selected as an output sample series.
[0013]
The input luminance signal Y and color signal C are supplied to a multiplexer that operates at a clock frequency of 3 / 2MCK. The multiplexer outputs a signal multiplexed from a signal having a clock frequency MCK at a clock frequency 3/2 times that frequency. At this time, there are three types of phase relationships between the clock frequencies MCK and 3 / 2MCK. The three types of phase relationships are those in which the rising edge of 3/2 MCK is after the rising edge of clock frequency MCK (first phase relationship), and the rising edge of 3/2 MCK is the rising edge of clock frequency MCK. The phase relationship almost coincides with the edge (second phase relationship), and the phase relationship in which the rising edge of 3/2 MCK precedes the rising edge of the clock frequency MCK (third phase relationship). In the first phase relationship among these three types of phase relationships, it is a timing at which data becomes uncertain. Therefore, by capturing data in the second and third phase relationships excluding the first phase relationship, the capture margin is increased, and power supply voltage, process variation, load condition of clock frequency MCK, etc. Becomes resistant to changing conditions. Further, the delay difference between the input signal and the output signal can be reduced, and the circuit scale can be reduced.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an overall configuration of an embodiment to which the present invention is applied. Reference numeral 101 denotes a solid-state image sensor, for example, a CCD image sensor. The CCD image sensor 101 is a single-plate imager having three primary color filters, a complementary color filter, and the like. As will be described in detail later, the CCD image pickup device 101 has an operation mode (first image pickup mode) for reading out all pixels and a line thinning-out operation mode for outputting a signal with a reduced number of lines (first image pickup mode). The second imaging mode) can be switched. Subject light is incident on the image sensor 101 via the lens system 100.
[0015]
An output signal of the image sensor 101 is supplied to the sample hold / AGC circuit 102. In the full frame reading mode, the time for reading one image is 1/30 seconds, and in the line thinning mode, this is 1/60 seconds. The sample-and-hold is configured as a correlated double sampling circuit, and noise removal, waveform shaping, and defective pixel compensation are performed. The AGC controls the gain according to the brightness of the subject, and the gain is also controlled for automatic aperture adjustment. The output signal of the sample hold / AGC circuit 102 is supplied to the A / D converter 103. The A / D converter 103 generates a digital imaging signal in which one sample is 10 bits.
[0016]
The digitized imaging signal is supplied to the camera signal processing circuit 104 having an IC circuit configuration. The signal processing circuit 104 includes a digital clamp circuit, a luminance signal processing circuit, a color signal processing circuit, a contour correction circuit, a defect compensation circuit, an automatic iris control circuit, an automatic focus control circuit, an automatic white balance correction circuit, and a component signal (Y: A luminance signal, Cr, Cb: a digital video signal in which color difference signals are sampled at a sampling frequency of a ratio of 4: 1: 1), a synchronization signal generation circuit, a timing generator, an interface with a microcomputer, and the like. A more specific configuration of the signal processing circuit 104 will be described later. The component signal is converted into multiplexed data by the multiplexer.
[0017]
A microcomputer 105 controls signal processing. A control signal from the microcomputer 105 is supplied to the lens system 100, the electronic volume 106, the camera signal processing circuit 104, and the timing controller 107. The timing controller 107 includes a timing generator 108 and a CCD driving circuit 109. The electronic volume 106 generates a gain control signal for the sample hold and AGC circuit 102.
[0018]
The camera signal processing circuit 104 and the timing controller 107 are supplied with a clock 3MCK having a frequency three times that of the clock MCK. As an example, the number of horizontal pixels of the image sensor 101 is 780, and MCK = 780 fh (fh: horizontal scanning frequency of the image sensor 101) = 12.3 MHz. Further, the horizontal synchronization signal H and the vertical synchronization signal V generated in the camera signal processing circuit 104 are supplied to the timing controller 107. A drive pulse generated by the CCD drive circuit 109 of the timing controller 107 is supplied to the image sensor 101. The drive pulse includes a vertical drive pulse, a horizontal drive pulse, a read pulse, and the like.
[0019]
FIG. 2 shows an example of the camera signal processing circuit 104. Here, a configuration in the case of including an automatic aperture control circuit is shown. For simplicity, the defect compensation circuit, automatic focus control circuit, and automatic white balance correction circuit are not shown. A 10-bit width digital imaging signal from the A / D converter 103 is supplied to the arithmetic circuit 112 via the digital clamp circuit 111. When the image sensor has a three primary color filter, the arithmetic circuit 112 adds or subtracts the three primary color signals to generate a luminance signal component and a color difference signal component.
[0020]
The luminance signal component is supplied to the luminance signal processing circuit 113 and the contour correction circuit 114, and the color difference signal component is supplied to the color signal processing circuit 116. The luminance signal processing circuit 113 includes a γ correction circuit and the like. The contour correction signal generated by the contour correction circuit 114 is added to the output signal of the luminance signal processing circuit 113 by the addition circuit 115. A luminance signal Y is obtained from the adder circuit 115. The color signal processing circuit 113 includes a γ correction circuit, a white balance correction circuit, and the like. Color difference signals Cr and Cb are generated from the color signal processing circuit 113. A component signal composed of Y, Cr, and Cb is supplied to the multiplexer 117. The multiplexer 117 combines these signals as described later, and a multiplexed component signal is generated at the output.
[0021]
A timing / synchronization signal generation circuit 118 is provided, and a horizontal synchronization signal H, a vertical synchronization signal V, a clock, and a timing signal are generated from this circuit 118 from a 3MCK clock. Reference numeral 119 denotes a serial IO for an interface between the microcomputer 105 and the camera signal processing circuit 104, and reference numeral 120 denotes a detection / accumulation circuit. The luminance signal component formed by the arithmetic circuit 112 is detected and supplied to the accumulation circuit 120. In the case of aperture control, the imaging screen is divided into a plurality of areas, and imaging signals are accumulated for each area. The accumulated data of each area is detected and output from the accumulation circuit 120 to the serial IO 119.
[0022]
The microcomputer 105 receives the accumulated data through the serial IO 119, and the microcomputer 105 performs a weighting operation on the accumulated data, an operation for obtaining a sum of weighted data in each area, generation of an aperture control signal, and the like. A drive motor for the aperture control ring of the lens system 100 is driven by the generated aperture control signal, and the timing controller 107 and the electronic volume 106 are controlled. An electronic shutter (exposure time) is controlled by the timing controller 107, and a gain is controlled by the electronic volume 106. In addition, a control signal is supplied from the microcomputer 105 to the detection and accumulation circuit 120 through the serial IO 119, and the pattern of area division is controlled.
[0023]
The multiplexer 117 for multiplexing component signals of the (411) method will be described in more detail. As shown in FIG. 3, the multiplexer 117 receives an 8-bit width luminance signal Y and a color difference signal C synchronized with the clock MCK and is synchronized with 3 / 2MCK (a clock having a frequency 3/2 times that of the clock MCK). An 8-bit wide multiplexed component signal is generated. The present invention particularly relates to multiplexer 117.
[0024]
FIG. 4 shows an embodiment of the present invention. The multiplexer 117 includes a shift register 121 to which the luminance signal Y (first sample series) and the color signal C (second sample series) are supplied, an output selector 122 that sequentially selects the output of the shift register 121, and an output selector. The selection pulse generation circuit 123 controls the switching of 122 and the register 124 connected to the output selector 122. Each register is 8 bits wide. Further, the shift register 121 _Y1 Output signal S0 is output from the shift register 121. _Y2 Output signal S1 is output from the shift register 121. _C3 Output signal S2 is output from the shift register 121. _C5 To output an output signal S3.
[0025]
FIG. 5 is a timing chart showing the operation of the multiplexer 117 described above. 3MCK is a clock that is three times the clock frequency MCK. The luminance signal Y and the color signal C are synchronized with the clock frequency MCK. Since it is a component signal of (411) system, luminance data of 4 samples (for example, Y ₀ , Y ₁ , Y ₂ , Y _Three ) For one sample of red color difference data (eg Cr ₀ ) And one sample of blue color difference data (for example, Cb) ₀ ) Corresponds.
[0026]
At this time, as indicated by Delay Y and Delay C in FIG. 5, since the clock frequency MCK is connected to more ICs than the 3/2 MCK as a whole system, the load is heavy and the clock frequency MCK is increased. The synchronized signal is delayed. Therefore, the output signals S0, S1, S2, S3 and the shift register 121 _C1 Output signal Q from _C See Y _-1 / Y ₀ Or C _r0 / C _b0 As described above, at this timing, there is a high possibility that the timing at which the data is switched is taken in depending on the load condition of the clock frequency MCK, the power supply voltage, and the process variation condition.
[0027]
In this embodiment, two types of phase relationships between the clock frequencies MCK and 3 / 2MCK are excluded except for a phase relationship in which the samples of the luminance signal Y and the color signal C are unstable. Data is taken in with the phase relationship. The three types of phase relationships are those in which the rising edge of 3/2 MCK is after the rising edge of clock frequency MCK (first phase relationship), and the rising edge of 3/2 MCK is the rising edge of clock frequency MCK. The phase relationship almost coincides with the edge (second phase relationship), and the phase relationship in which the rising edge of 3/2 MCK precedes the rising edge of the clock frequency MCK (third phase relationship). The first phase relationship among the three types of phase relationships is the timing at which the data becomes uncertain when the above-described data (sample) is delayed. Therefore, data is captured in the second and third phase relationships excluding the first phase relationship.
[0028]
Therefore, a selection signal (SP) is supplied from the selection pulse generation circuit 123 to the output selector 122 as a control signal that does not select the data switching timing (first phase relationship). A signal (SS) selected from the output selector 122 in accordance with the selection signal (SP) is output. The output signal is taken into the register 124. Synchronized from register 124 to 3/2 MCK (Y ₀ , Y ₁ , Y ₂ , Y _Three , Cr ₀ , Cb ₀ ) To generate component signals (output sample sequences) that are multiplexed so as to have the order of
[0029]
The multiplexer 117 converts the data sampling clock frequency from MCK to 3/2 MCK of 1.5 times the frequency, thereby converting the data into an 8-bit width multiplexed component signal. In the case where the multiplexer 117 is not provided, the camera signal processing circuit 104 outputs (8 × 2 = 16 bits) width data (luminance signal Y and color signal C). In that case, crosstalk between two data buses occurs, crosstalk increases due to an increase in the substrate wiring area, memory size increases due to an increase in the memory data width, Various problems such as an increase in power consumption of the memory occur. By providing the multiplexer 117 described above on the output side of the signal processing circuit 104, the occurrence of these problems can be prevented.
[0030]
Although not shown, it is possible to change the mode by providing a change-over switch before the input of the multiplexer 117. In the above description, the mode in which the luminance signal Y and the color signal C are multiplexed by the multiplexer 117 has been described. However, the luminance signal Y and the color signal C may be directly output without passing through the multiplexer 117.
[0031]
Returning to FIG. 1, an embodiment to which the present invention can be applied will be further described. The component signals multiplexed as described above from the camera signal processing circuit 104 are supplied to the data switcher 130. The data switcher 130 is connected to the output point a connected to the output of the camera signal processing circuit 104, the input point b connected to the conversion circuit 134 for converting the component signal into the three primary color signals, and the recording / reproducing data bus 140. And an input / output point c. The state of the data switcher 130 is controlled by mode switching signals 131, 132, 133 generated based on user key operations and the like. The microcomputer 105 in FIG. 1 is provided mainly for controlling the camera unit. Although not shown, the microcomputer 105 is provided for controlling the recording / reproducing operation and for controlling the entire apparatus. Communication between microcomputers is performed.
[0032]
The three primary color signals R, G, and B generated by the conversion circuit 134 are supplied to a television display device such as a liquid crystal display 135, and a captured image is displayed on the liquid crystal display 135. The liquid crystal display 135 displays a color image using a non-interlace method with a 1/60 second period. A random accessible memory such as a DRAM (Dynamic Random Access Memory) 141 and a data compression encoder / decoder such as a JPEG (Joint Photographic Experts Group) encoder / decoder 142 are connected to the recording / reproducing data bus 140. High efficiency encoding other than JPEG may be used. A recording medium such as a flash memory 143 and an interface 144 are connected to the encoder / decoder 142. The operation of the DRAM 141 is controlled by an address signal and a control signal supplied from the memory controller 145.
[0033]
The encoder / decoder 142 compresses the data amount to about 1/10 by encoding of JPEG, that is, adaptive DCT (Discrete Cosine Transform). A DRAM 141 is provided for processing such as blocking in JPEG. The flash memory 143 is a semiconductor memory that retains stored contents even when the power is turned off, and can be erased and rewritten electrically collectively for the entire memory or for each divided area. As the recording medium, a medium such as a semiconductor memory other than the flash memory may be used. Further, an interface may be provided to supply the compressed still image data to a personal computer as necessary. In one embodiment of the present invention, recording refers to encoding an imaging signal and writing it to the flash memory 143, and reproduction refers to reading data in the flash memory 143 and decoding read data. .
[0034]
The data switcher 130 described above can perform five types of operations depending on the connection state. This includes a monitoring mode, a first recording mode, a second recording mode, a first reproduction mode, and a second reproduction mode. These modes are set by mode switching signals 131, 132, 133. The mode switching signals 131, 132, 133 are generated from a recording / reproducing system control microcomputer (not shown). A mode switching signal may be generated by the microcomputer 105. In the monitoring mode, the imaging screen is displayed on the liquid crystal display 135. In the first recording mode, a desired captured image is written into the DRAM 141. In the second recording mode, the image data stored in the DRAM 141 is compressed and written to the flash memory 143. In the first reproduction mode, the data stored in the flash memory 143 is read, and the read data is decoded and written into the DRAM 141. In the second reproduction mode, data in the DRAM 141 is read and displayed on the liquid crystal display 135.
[0035]
The monitoring mode is set when the output point a and the input point b of the data switcher 130 are connected and the mode switching signal 131 becomes active. In this monitoring mode, the microcomputer 105 controls the CCD drive circuit 109 of the timing controller 107 to operate the image sensor 101 in the line thinning mode. A line which is not read out is generated from the image pickup element 101, and an image pickup signal is read out at a period of 1/60 second. In the monitoring mode, the output signal of the signal processing circuit 104 is supplied to the conversion circuit 134 via the data switcher 130, and the three primary color signals output from the conversion circuit 134 are supplied to the liquid crystal display 135 and displayed. Since the image sensor 101 operates in the line thinning mode, the liquid crystal display 135 can perform non-interlaced display with a 1/60 second period. By looking at the display on the liquid crystal display 135, the angle of view can be adjusted and the still image to be recorded can be determined.
[0036]
The first recording mode is set when a still image is recorded, that is, when the output point a and the input / output point c of the data switcher 130 are connected and the mode switching signal 132 becomes active. In the first recording mode, the microcomputer 105 controls the CCD drive circuit 109 of the timing controller 107 to operate the image sensor 101 in the full frame reading mode. From the image sensor 101, all pixels, for example, 320,000 pixels are read out, and an image pickup signal is read out at a 1/30 second period.
[0037]
The imaging signal is processed by the camera signal processing circuit 104 and written to the DRAM 141 through the output point a and the input / output point c of the data switcher 130 and the recording / reproducing data bus 140. The memory controller 145 sets the DRAM 141 to a write state and supplies a write address to the DRAM 141. The memory controller 145 is controlled by a recording / reproducing system control microcomputer (not shown). One still image data is written in the DRAM 141. In the first recording mode in which 1/30 second image data is written, an image cannot be displayed on the liquid crystal display 135. In order to minimize the time during which no image is displayed, when writing is completed, the process proceeds to the next second recording mode.
[0038]
When the writing of one image data to the DRAM 141 is completed, the data switcher 130 enters the second recording mode in which the output point a and the input point b are connected. The second recording mode is set when the mode switching signal 131 becomes active. In this mode, image data is read from the DRAM 141. The read data is supplied to the encoder / decoder 142 via the bus 140. The encoder / decoder 142 compresses data read from the DRAM 141 by, for example, JPEG. In addition, the compressed data is written into the flash memory 143. In this way, the captured image is compressed and recorded.
[0039]
In the second recording mode, the image sensor 101 is operated in the line thinning mode, and the signal read from the image sensor 101 at a high speed is processed by the camera signal processing circuit 104 in the same manner as in the monitoring mode. The signal is supplied to the liquid crystal display 135 through the data switcher 130 and the conversion circuit 134, and an image is displayed. As a result, the time during which the image display disappears during recording can be minimized.
[0040]
In the reproduction mode, the image data written in the flash memory 143 is reproduced and displayed on the liquid crystal display 135. The first reproduction mode is set when the output point a and the input point b of the data switcher 130 are connected and the mode switching signal 131 becomes active. In this mode, data is read from the flash memory 143 and the read data is supplied to the encoder / decoder 142.
[0041]
Data is decoded by the encoder / decoder 142 to generate image data. The DRAM 141 is controlled to write this image data. In this case, the memory controller 145 controls the write address of the DRAM 141 so that the decoded data is written to the DRAM 141 with the same data arrangement as that in the first recording mode. A similar data array may be realized by address control at the time of reading. This relationship is because when the digital image signal read from the DRAM 141 is supplied to the liquid crystal display 135 via the conversion circuit 134 and displayed on the liquid crystal display 135, the same configuration as that used in the monitoring mode is used. Is necessary for. In the first reproduction mode, the image sensor 101 is driven in the line thinning mode, and a captured image of the image sensor 101 is displayed on the liquid crystal display 135.
[0042]
When the decoded data is written to the DRAM 141, the second reproduction mode is set. The second reproduction mode is set when the input / output point c and the input point b of the data switcher 130 are connected and the mode switching signal 133 becomes active. The DRAM 141 is set in a read state. Then, read data of the DRAM 141 is supplied to the liquid crystal display 135 via the recording / reproducing data bus 140, the data switcher 130, and the conversion circuit 134. Therefore, an image corresponding to the data recorded in the flash memory 143 can be viewed on the liquid crystal display 135. In this case, the data recorded in the flash memory 143 is not full-line data but full-frame data. Therefore, line thinning similar to the case where the image sensor 101 is driven in the line thinning mode is realized by address control by the memory controller 145. Thereby, the read data of the DRAM 141 can be reproduced by the liquid crystal display 135. In this way, the still image data stored in the flash memory 143 can be reproduced and viewed on the liquid crystal display 135.
[0043]
An example of the solid-state image sensor 101 described above will be described below. FIG. 6 shows an outline of an example of a solid-state image sensor, for example, a CCD image sensor 1. In this example, an interline method is adopted, and a signal charge from the photosensor 2 provided between the photosensors (for example, photodiodes) 2 two-dimensionally arranged in the image area and the photosensor 2 is horizontal CCD (horizontal). A vertical CCD (vertical transfer unit) 3 for transferring to a transfer unit 4, and a buffer amplifier 5 connected to the horizontal CCD 4. Imaging light that has passed through an array of color filters, which will be described later, is incident on the photosensor 2. One photosensor 2 and one bit in the vertical CCD 3 correspond to each other, and signal charges from the photosensor 2 are read to the vertical CCD 3 without mixing, and signals of all pixels are sequentially transferred to the horizontal CCD 4. It is possible. Then, by driving the horizontal CCD 4, the signal is transferred to the floating diffusion area, sequentially converted into a voltage, and output through the buffer amplifier 5.
[0044]
A plan view of a unit pixel of the image sensor 1 is shown in FIG. 7, and a structure of the vertical CCD 3 is shown in FIG. The vertical CCD 3 has, for example, a three-layer electrode three-phase drive configuration. In FIG. 7, 6 is a transfer channel of the vertical CCD 3, 7 is a channel stopper for separating pixels and between the pixel and the transfer channel, and 8, 9 and 10 are transfer gates of the vertical CCD 3, respectively. The transfer gate 9 also serves as a read gate. In FIG. 7, illustration of the light shielding film and the like is omitted. Transfer gates 8, 9, and 10 are formed by processing the first, second, and third polycrystalline silicon electrodes, as shown in FIG. For these transfer gates 8, 9, 10 a vertical drive pulse φV ₁ , ΦV ₂ , ΦV _Three Are applied respectively.
[0045]
When reading a signal from the photosensor 2 to the vertical CCD 3, a vertical transfer clock φV is supplied to a transfer gate adjacent to the photosensor 2, that is, a transfer gate 9 also serving as a read gate. ₂ A bias voltage higher than the high level (referred to as a read pulse) is applied. When a read pulse is supplied to the gate 9, one pixel corresponds to one bit of the vertical CCD 3, so that signal charges are read from all the photosensors 2 to the vertical CCD 3. The horizontal CCD 5 has a transfer clock φH ₁ , ΦH ₂ To output data for one line. As the horizontal CCD 5, for example, a composite channel horizontal CCD structure can be adopted. In that case, the output unit has a two-channel configuration.
[0046]
The CCD image pickup device described above is suitable for electronic still cameras and image capture because it can sequentially output signals of all pixels. However, the output time of one screen (from the upper end to the lower end of the screen) is doubled compared to an image sensor for video cameras having the same number of pixels that performs interlaced output. In this example, as described above, as a monitor signal and an imaging signal for automatic control such as automatic focus control, the number of horizontal lines is reduced to output an imaging signal for one screen at high speed. In addition, in the case of this line thinning, the color sequence in the vertical direction defined by the color filter arrangement is not disturbed. On the other hand, when a captured image is taken into the flash memory, a full frame imaging signal (an imaging signal in which the number of lines is not thinned) is output. Even in the case of line thinning, since the color sequence is the same as that in the case of a full frame, the problem that the signal processing circuit becomes complicated can be avoided.
[0047]
In the above-described image pickup device capable of reading out all pixels, in order to thin out the number of lines, two wirings for the transfer gate (second polycrystalline silicon) 9 contributing to reading out signal charges from the photosensor 2 are used. It is possible by dividing. The repetition period of the color sequence is represented by N. FIG. 9 is an example in the case of (N = 2).
[0048]
As the arrangement of the color filters of the single-plate CCD image sensor, R (filter that passes red), G (filter that passes green), and B (filter that passes blue) are arranged as shown in FIG. 10A (Bayer method) )It has been known. A high-sensitivity G filter is arranged in half of the pixels. Further, a complementary color checkered color filter shown in FIG. 10B is also known. In FIG. 10B, Ye, Cy, and Mg are yellow, cyan, and magenta filters, respectively. The complementary color filter shown in FIG. 10B can be increased in resolution as compared with the primary color filter, and is therefore often used in video cameras. On the other hand, the primary color filter shown in FIG. 10A is excellent in terms of color reproducibility and is often employed in electronic still cameras.
[0049]
As the image sensor in the present invention, any of a single-plate image sensor having a primary color filter and a single-plate image sensor having a complementary color filter may be used. Further, although not shown in the drawing, the image pickup device includes an image pickup device having a G filter and an image pickup device having an array of R and B filters, and the positional relationship between the two image pickup devices is a pixel in the horizontal direction or the horizontal and vertical directions. You may use the image pick-up element (what is called a space picture element shift system) of the system shifted only 1/2 of the pitch.
[0050]
In the arrangement of FIG. 10A, the repetition period N of the color sequence in the vertical direction is (N = 2), and the arrangement of FIG. 10B is (N = 4). FIG. 9 is a schematic diagram showing (N = 2) the photo wirings of one column in the vertical direction, the vertical CCD 3 and the bus wiring of the gates of the vertical CCD 3 with respect to a part of one column. Among the photosensors 2, the one provided with a hatched portion in the upper left corner corresponds to one color filter, for example, a G filter, and the one not provided with the hatched portion corresponds to another color filter, for example, a B filter. As described above, the vertical CCD 3 is of the three-layer electrode, three-phase drive type, and has a 3-bit gate adjacent to the aperture pixel of the image sensor. The vertical CCD 3 includes a repeating unit A and a repeating unit B. The repeating unit A includes gates 21, 22, and 23, and the repeating unit B includes gates 31, 32, and 33. Gates 22 and 32 are transfer and read gates. Reference numerals 41, 42, 42 'and 43 denote vertical transfer drive pulses φV. ₁ , ΦV ₂ , ΦV ₂ ', ΦV _Three Are the bus lines supplied.
[0051]
Gates 21 and 31 are connected to bus line 41, and gates 23 and 33 are connected to bus line 43. These bus lines 41 and 43 have a drive pulse φV, respectively. ₁ , ΦV _Three Is supplied. Drive pulse φV ₂ For this, two buses 42 and 42 'are provided. The repeat unit A indicates that the transfer / read gate 22 is connected to the bus 42, and the repeat unit B indicates that the transfer / read gate 32 is connected to the bus 42 '. In FIG. 9, for simplification, the bus line is drawn only on one side, but it is normal to arrange the bus line on both sides and drive on both sides.
[0052]
In the above-described imaging device, for line thinning, a range of A × m (bits) in which repeating units A are arranged m (m = 1, 2, 3,...) And repeating units B are arranged N × a. A range of B × N × a (bits) is alternately formed in the vertical direction. The example shown in FIG. 9 is a case of (N = 2, m = 3, a = 2). Although the values of m and a can be arbitrarily selected, even if m and a are large values, it is necessary that (m + N × a) is smaller than the number of effective pixels.
[0053]
In the imaging device described above, in the first operation mode, that is, in the full frame operation in which the signals of all the pixels are read, signals are read from the photosensor 2 to both the repeating units A and B of the vertical CCD 3. For this purpose, a read pulse is applied to both gates 22 and 32 through bus lines 42 and 42 '. In this case, color signals are output in a color sequence corresponding to the order of arrangement of the color filters, for example, a sequence of G, B, G, B,.
[0054]
On the other hand, in the second operation mode, that is, in the line thinning operation, a read pulse is applied only to the gate 22 of the repeating unit A through the bus wiring 42. Therefore, a signal is read from the range of A × m (bit), and no signal is read from the range of B × N × a (bit). In the example of FIG. 9, a signal is generated from the (m = 3) line, and no signal is generated from the (N × a = 4) line. Since the number of lines to be thinned is an integer multiple of N, the color sequence corresponding to the order of the color signals of the imaging output in the case of line thinning is kept in the same relationship as in full frame reading.
[0055]
FIG. 11 shows the timing when driving the image sensor, and FIG. 11A shows the timing when full frame reading is performed. In each horizontal blanking period, three-phase drive pulse φV ₁ , ΦV ₂ , ΦV ₂ ', ΦV _Three Are supplied to the gates 21, 22 and 23 of the repeating unit A and the gates 31, 32 and 33 of the repeating unit B, respectively. A read pulse is also applied to both gates 22 and 32. Thereby, signal charges are read out from all the photosensors to the vertical CCD 3. As shown in the detailed timing chart of FIG. 11B, the drive pulse φV generated within the horizontal blanking period. ₁ , ΦV ₂ , ΦV ₂ ', ΦV _Three Are three-phase, and one line shift is performed according to the line shift period. During full frame reading, one line shift is performed within each horizontal blanking period.
[0056]
On the other hand, in the case of line thinning readout, a readout pulse is applied only to the gate 22 of the repeating unit A, as shown in FIG. 11C. Thereby, the signal charge is read out only from the photosensor adjacent to the repeating unit A. In the case of line thinning, the signal charge is not read out on the thinned line, and no signal is generated. This non-signal period can be removed by repeating the line shift operation a plurality of times, as will be described later.
[0057]
The specific configuration of the image sensor in the embodiment described above is an example, and the present invention can use other solid-state image sensors. For example, the vertical CCD may have a structure of a two-layer electrode four-phase drive, an image sensor other than the interline system, and a solid-state image sensor using other than the CCD. Further, as a mode for driving the solid-state imaging device, the readout pulse φV ₂ 'And read pulse φV ₂ A third operation mode in which no voltage is applied may be set.
[0058]
In addition, the present invention is not limited to the image sensor having the above-described structure, and an image sensor that can select an all-pixel readout mode and a mode in which the number of readout pixels is reduced can be used.
[0059]
【The invention's effect】
As described above, according to the present invention, the capture margin when a clock frequency MCK signal is captured in synchronism with 3/2 MCK is increased, and the power supply voltage, process variation, load condition of the clock frequency MCK, etc. Since it is resistant to fluctuations in conditions, data can be captured reliably.
[0060]
According to the present invention, since the system delay of the multiplexer output signal is shortened, the delay difference between the signal in the mode in which the multiplexer input signal is output as it is and the output signal of the multiplexer is reduced. The same sync signal (such as HD) can be easily used.
[0061]
Furthermore, according to the present invention, the circuit scale of the multiplexer can be halved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an example of a digital electronic imaging apparatus to which the present invention is applied.
FIG. 2 is a block diagram of an example of a camera signal processing circuit to which the present invention is applied.
FIG. 3 is a block diagram of a multiplexer portion in the camera signal processing circuit of the present invention.
FIG. 4 is a block diagram of an embodiment of a multiplexer of the present invention.
FIG. 5 is a timing chart showing an embodiment of the operation of the multiplexer of the present invention.
FIG. 6 is a schematic diagram illustrating a schematic configuration of an example of an image sensor that can be used in the present invention.
FIG. 7 is an enlarged plan view of one pixel portion of an example of an image sensor.
FIG. 8 is a schematic diagram illustrating a structure of a vertical CCD as an example of an image sensor.
FIG. 9 is a schematic diagram illustrating a vertical line of bus wiring of an example of an image sensor;
FIG. 10 is a schematic diagram illustrating an example of an arrangement of color filters used in an example of an image sensor and another example.
FIG. 11 is a timing chart of drive pulses for driving an example of an image sensor.
FIG. 12 is a block diagram of a conventional multiplexer.
FIG. 13 is a timing chart showing the operation of a conventional multiplexer.
[Explanation of symbols]
2 ... Photosensor, 3 ... Vertical CCD, 4 ... Horizontal CCD, 6 ... Channel of vertical CCD, 101 ... Image sensor, 104 ... Camera signal processing circuit, 105 ... Microcomputer, 107 ... Timing controller, 130 ... Data switcher, 135 ... Liquid crystal display, 141 ... DRAM, 142 ... Encoder / decoder, 143 ... Flash memory

Claims (3)

A first sample series synchronized with a first clock signal having a first frequency, and a second sample having a sampling rate of (1/2) of the first sample series synchronized with the first clock signal. And an output sample sequence is generated by synthesizing the first and second sample sequences synchronized with a second clock signal having a second frequency (3/2) times the first frequency. In the signal processing apparatus as described above,
A plurality of first registers for capturing and holding the first sample series by the second clock signal;
A plurality of second registers for capturing and holding the second sample series by the second clock signal;
An output selector for selecting outputs of the plurality of first and second registers and generating the output sample series;
Comprising selection signal forming means for forming a selection signal for controlling the output selector,
Of the three types of phase relationships between the first clock signal and the second clock signal, samples taken in a phase relationship excluding the unstable phase relationship of the first and second sample series A signal processing apparatus that selects the output sample series. The signal processing device according to claim 1,
The above three types of phase relationships are
A first phase relationship in which a rising edge of the second clock signal is after a rising edge of the first clock signal;
A second phase relationship in which a rising edge of the second clock signal substantially coincides with a rising edge of the first clock signal;
The rising edge of the second clock signal consists of a third phase relationship before the rising edge of the first clock signal;
A signal processing apparatus characterized in that samples in the first and second sample sequences fetched in the second and third phase relationships are output as the output sample sequence. The signal processing device according to claim 1,
The above output sample series is
Based on the selection signal synchronized with the second clock signal, after selecting four samples from the first sample series, two samples are selected from the second sample series. A signal processing device.

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