JPH10341448A - Signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processor capable of surely fetching data by selecting a sample fetched in a phase relation except for the unstable phase relation of first and second sample groups among three types of phase relations between a first clock signal and a second clock signal as an output sample group. SOLUTION: Output signals S0, S1, S2 and S3 are outputted from the shift registers 121Y1 , 121Y2 , 121C3 and 121C5 of eight bits, which supply the luminance signal Y (first sample group) and the chrominance signal C (second sample group) of a multiplexer. A selection signal which does not select a case when the rise edge of 3/2MCK in the first phase relation where data becomes uncertain is behind the rise edge of a clock frequency MCK is supplied from a selection pulse generation circuit 123 to an output selector 122. The output signal of the output selector 122 is taken into a register 124 and a component signal having the order of (Y0 , Y1 , Y2 , Y3 , Cr0 and Cb0 ) synchronized with 3/2MCK is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus suitable for use, for example, in an electronic still camera for digital recording.

[0002]

2. Description of the Related Art Recently, digital electronic still cameras have become widespread. In the case of a digital electronic still camera, a monitor that displays a captured image, for example, a liquid crystal monitor, is often provided in order to focus on the image or adjust the camera angle during the image capturing. Applicant also filed Japanese Patent Application No. 8-
No. 82035 realizes a digital electronic still camera that does not require an additional VRAM (video RAM) by using an image sensor of an all-pixel readout method.

In Japanese Patent Application No. 8-82035, a component signal can be multiplexed by changing a clock frequency in a camera signal processing circuit, and a data bus provided for subsequent signal processing is provided. One of the effects is that the signal width such as crosstalk can be suppressed, and the memory size can be reduced and the power consumption of the memory can be reduced. ing.

FIG. 12 shows an example of the configuration of a signal processing device having such an effect, for example, a multiplexer. The multiplexer includes an input selector 151 for selecting one of the luminance signal Y and the chrominance signal C, a shift register 152 to which the input selector 151 is supplied as a serial input, and a register 153 to which the parallel output of the shift register 152 is loaded.
It comprises an output selector 154 for sequentially selecting data loaded in the register 153, and a register 155 connected to the output selector 154. Each register is 8 bits wide.

FIG. 13 is a timing chart showing the operation of the multiplexer described above. 3MCK is a clock three times the frequency of the clock MCK. The luminance signal Y and the chrominance signal C are synchronized with the clock MCK. (4
11) Since this is a component signal of the system, four samples of luminance data (for example, Y ₀ , Y ₁ , Y ₂ , Y ₃ ) have one sample of red color difference data (for example, Cr ₀ ) and one sample of blue. (For example, Cb ₀ ).

The input selector 151 is controlled so that luminance data is selected at the high level of the select pulse and color data is selected at the low level. The shift register 152 receives 3 / 2MCK as a clock, takes in the data selected by the input selector 151, and shifts in series. As shown in the figure, the output Q ₀ of the first-stage register of the shift register 152 is Y ₋₁ ,
Y ₀ , Cr ₀ , Y ₁ , Y ₂ , Cb ₀ , Y ₃ ,...

The shift register 152 is supplied to the register 153 at a timing of 1/4 MCK clock.
Are loaded in parallel. The cycle of the 1/4 MCK clock is six times the cycle of the 3/2 MCK. Also, 1
The phase of the / 4MCK clock is selected such that a total of six samples of the associated luminance and chrominance data are transferred from shift register 152 to register 153.

The output selector 154 outputs a clock (3/2)
MCK), the sample is sequentially selected from the earliest sample in the register 153, and the selected sample is stored in the register 155.
Captures. Therefore, from the register 155, (Y, C
(r, Y, Y, Cb, Y).

[0009]

However, in this multiplexer, the timing at which a signal synchronized with the clock frequency MCK is taken in at 3/2 MCK is determined by the luminance data Y.
_{If 0,} the clock frequency M
Since the timing is delayed by １ ／ cycle of the clock signal of CK, there is a problem that a margin for data delay is small. That is, if the luminance signal Y and the color signal C have a delay with respect to the clock signal of the clock frequency MCK,
Data sampled by the clock signal of 3 / 2MCK occurs even if the Y _-1 is not limited to Y _0.

Further, since the output signal from the multiplexer is not output until six clocks have elapsed since the data was input, there was a problem that the system delay was large. Furthermore, in order to configure this multiplexer,
Since 12 flip-flops are required, there is a problem that the circuit scale becomes large.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a signal which can reliably capture data when the data is switched to a clock frequency which is 3/2 times the original clock frequency in view of these problems. An object of the present invention is to provide a processing device.

[0012]

According to the first aspect of the present invention, there is provided a first clock synchronous with a first clock signal having a first frequency.
In synchronization with the sample sequence of
And a second sample sequence at a sampling rate of (1/2) of the sample sequence at
2) In a signal processing apparatus configured to generate an output sample sequence obtained by synthesizing first and second sample sequences synchronized with a second clock signal having a second frequency twice as high,
Sampled by the second clock signal,
A plurality of first registers to be held and a second sample sequence are fetched by a second clock signal, and a plurality of second registers to be held and outputs of the plurality of first and second registers are selected and output. An output selector for generating a sample sequence, and selection signal forming means for forming a selection signal for controlling the output selector, wherein three types of phase relationships between the first clock signal and the second clock signal are provided. A signal sampler which selects a sample taken in a phase relationship excluding an unstable phase relationship between the first and second sample sequences as an output sample sequence.

When the input luminance signal Y and color signal C are 3
/ 2MCK clock frequency. This multiplexer outputs a signal multiplexed from a signal of the clock frequency MCK at a clock frequency 3/2 times the frequency. At this time, there are three types of phase relationships between the clock frequencies MCK and 3 / 2MCK. The three types of phase relationships are those in which the rising edge of 3/2 MCK is after the rising edge of clock frequency MCK (first phase relationship).
When the rising edge of 2MCK is almost the same as the rising edge of the clock frequency MCK (second phase relationship), when the rising edge of 3 / 2MCK is before the rising edge of the clock frequency MCK (Third phase relationship). In the case of the first phase relationship among these three types of phase relationships, it is the timing at which the data becomes indeterminate. Therefore, by taking in data in the second and third phase relationships excluding the first phase relationship, the taking margin is increased, and the power supply voltage, process variation, clock frequency MC
It is resistant to fluctuations in conditions such as the load condition of K. Further, the delay difference between the input signal and the output signal can be reduced, and the circuit scale can be reduced.

[0014]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an overall configuration of an embodiment to which the present invention is applied. 101 is
It is a solid-state image sensor, for example, a CCD image sensor. The CCD image sensor 101 is a single-plate imager having three primary color filters, complementary color filters, and the like. CCD image sensor 101
Is a full-frame read operation mode for reading all pixels (first imaging mode), as described in detail later.
And a thinning-out operation mode (second imaging mode) for outputting a signal with a reduced number of lines. Subject light enters the image sensor 101 via the lens system 100.

An output signal of the image pickup device 101 is supplied to a sample hold and AGC circuit 102. In the full frame read mode, the time for reading one image is 1/3.
0 seconds, which is 1/60 in the line thinning mode.
Seconds. The sample and hold is configured as a correlated double sampling circuit, and performs noise removal, waveform shaping, and compensation for defective pixels. The AGC controls the gain according to the brightness of the subject, and also controls the gain for automatic aperture adjustment. The output signal of the sample-hold and AGC circuit 102 is supplied to the A / D converter 103.
The A / D converter 103 generates a digital imaging signal in which one sample has 10 bits.

The digitized image signal is supplied to a camera signal processing circuit 104 having an IC circuit. The signal processing circuit 104 includes a digital clamp circuit, a luminance signal processing circuit, a color signal processing circuit, a contour correction circuit, a defect compensation circuit, an automatic aperture control circuit, an automatic focus control circuit, an automatic white balance correction circuit, and a component signal (Y: A multiplexer of a luminance signal, a digital video signal obtained by sampling a Cr, Cb: color difference signal at a sampling frequency of 4: 1: 1), a synchronizing signal generating circuit, a timing generator, an interface with a microcomputer, and the like are included. A more specific configuration of the signal processing circuit 104 will be described later. The multiplexer converts the component signal into multiplexed data.

Reference numeral 105 denotes a microcomputer for controlling signal processing. A control signal from the microcomputer 105 is supplied to the lens system 100, the electronic volume 106, the camera signal processing circuit 104, and the timing controller 107. Timing controller 1
Reference numeral 07 includes a timing generator 108 and a CCD drive circuit 109. The electronic volume 106 generates a sample and hold and a gain control signal for the AGC circuit 102.

A clock 3MCK having a frequency three times the frequency of the clock MCK is supplied to the camera signal processing circuit 104 and the timing controller 107. As an example,
The number of horizontal pixels of the image sensor 101 is 780, and MCK =
780fh (fh: horizontal scanning frequency of the image sensor 101) =
It is 12.3 MHz. Further, the horizontal synchronization signal H and the vertical synchronization signal V generated in the camera signal processing circuit 104 are supplied to the timing controller 107.
CCD drive circuit 109 of timing controller 107
Are supplied to the image sensor 101.
The drive pulse includes a vertical drive pulse, a horizontal drive pulse, a readout pulse, and the like.

FIG. 2 shows an example of the camera signal processing circuit 104. Here, a configuration including an automatic aperture control circuit is shown. For simplicity, illustration of a defect compensation circuit, an automatic focus control circuit, and an automatic white balance correction circuit is omitted. A 10-bit digital imaging signal from the A / D converter 103 is supplied to the arithmetic circuit 112 via the digital clamp circuit 111. When the image sensor has three primary color filters, the arithmetic circuit 112 adds or subtracts the three primary color signals to generate a luminance signal component and a color difference signal component.

The luminance signal component is supplied to a luminance signal processing circuit 113 and a contour correction circuit 114, and the color difference signal component is supplied to a color signal processing circuit 116. Luminance signal processing circuit 1
13 includes a gamma correction circuit and the like. Contour correction circuit 11
4 is a luminance signal processing circuit 1
13 are added by the adding circuit 115 to the 13 output signals. The luminance signal Y is obtained from the adding circuit 115. The color signal processing circuit 113 includes a γ correction circuit, a white balance correction circuit, and the like. The color signal processing circuit 113 generates color difference signals Cr and Cb. A component signal including Y, Cr, and Cb is supplied to the multiplexer 117.
The multiplexer 117 combines these signals as described below, and generates a multiplexed component signal at the output.

A timing and synchronization signal generation circuit 118 is provided, and a horizontal synchronization signal H, a vertical synchronization signal V, a clock, and a timing signal are generated from the 3MCK clock. 119 is a serial IO for an interface between the microcomputer 105 and the camera signal processing circuit 104, and 120 is a detection /
It is an accumulation circuit. The luminance signal component formed by the arithmetic circuit 112 is supplied to the detection and accumulation circuit 120. In the case of aperture control, the imaging screen is divided into a plurality of areas, and imaging signals are accumulated for each area. Then, the accumulated data of each area is detected and output from the accumulation circuit 120 to the serial IO 119.

The microcomputer 105 receives the accumulated data through the serial IO 119, and performs a weighting operation on the accumulated data, an operation for obtaining the sum of the data in each of the weighted areas, a generation of the aperture control signal, and the like. The drive motor of the aperture control ring of the lens system 100 is driven by the generated aperture control signal, and the timing controller 107 and the electronic volume 106 are controlled. An electronic shutter (exposure time) is controlled by the timing controller 107,
The gain is controlled by the electronic volume 106. Also, a control signal is supplied from the microcomputer 105 to the accumulation circuit 120 through the serial IO 119, and the pattern of the area division is controlled.

The multiplexer 117 for multiplexing the component signals of the (411) system will be described in more detail. As shown in FIG.
Receives an 8-bit width luminance signal Y and a color difference signal C synchronized with the clock MCK, and receives 3/2 MCK (clock M
A multiplexed component signal having an 8-bit width synchronized with a clock having a frequency 3/2 times the frequency of CK is generated. The invention particularly relates to the multiplexer 117.

FIG. 4 shows an embodiment of the present invention.
The multiplexer 117 includes a shift register 121 to which a luminance signal Y (first sample sequence) and a chrominance signal C (second sample sequence) are supplied, an output selector 122 for sequentially selecting outputs of the shift register 121, and an output selector. Selection pulse generation circuit 12 for controlling switching
3 and the register 124 connected to the output selector 122
Consists of Each register is 8 bits wide.
Further, the output is an output signal S0 from the shift register 121 _Y1 is output the output signal S1 from the shift register 121 _Y2 are output output signal S2 from the shift register 121 _C3, the output signal S3 is outputted from the shift register 121 _C5 .

FIG. 5 is a timing chart showing the operation of the multiplexer 117 described above. 3MCK is a clock three times the clock frequency MCK. Luminance signal Y
The color signal C is synchronized with the clock frequency MCK. Since it is a (411) system component signal,
Four samples of luminance data (for example, Y ₀ , Y ₁ , Y ₂ , Y
₃ ), one sample of red color difference data (for example, C
r ₀ ) and one sample of blue color difference data (for example, Cb ₀ )
And correspond.

At this time, Delay Y and Delay Y in FIG.
As shown in C, the clock frequency MCK is connected to more ICs than the 3/2 MCK in the entire system, so the load is heavy and the signal synchronized with the clock frequency MCK tends to be delayed. Therefore, the output signal S
0, S1, S2, S3 and looking at the output signal Q _C from the shift register 121 _C1, Y _-1 / Y ₀ or C _r0 / C
_As indicated by _b0 , at this timing, there is a high possibility that the data switching timing is just taken in depending on the load condition of the clock frequency MCK, the power supply voltage, and the process variation condition.

In this embodiment, the clock frequency M
Data is taken in two kinds of phase relations between the CK and the 3/2 MCK except for a state in which the sample of the luminance signal Y and the sample of the chrominance signal C become unstable. The three types of phase relationships are 3 / 2MCK
Is a phase relationship in which the rising edge of the clock frequency is after the rising edge of the clock frequency MCK (first phase relationship), and the phase relationship in which the rising edge of the 3/2 MCK substantially matches the rising edge of the clock frequency MCK ( The second phase relationship) is a phase relationship in which the rising edge of 3 / 2MCK is before the rising edge of the clock frequency MCK (third phase relationship). The first phase relationship among the three types of phase relationships is the timing at which the data becomes indefinite when the data (sample) described above is delayed. Therefore, data is fetched in the second and third phase relationships excluding the first phase relationship.

Therefore, a selection signal (SP) is supplied from the selection pulse generation circuit 123 to the output selector 122 as a control signal that does not select the data switching timing (first phase relationship). The signal (SS) selected from the output selector 122 according to the selection signal (SP)
Is output. The output signal is taken into the register 124. The register 124 generates a component signal (output sample sequence) multiplexed so as to have an order of (Y ₀ , Y ₁ , Y ₂ , Y ₃ , Cr ₀ , Cb ₀ ) synchronized with 3 / 2MCK.

The multiplexer 117 converts the data sampling clock frequency from MCK to 3/2 MCK, which is 1.5 times the frequency of MCK, thereby converting the data into an 8-bit width multiplexed component signal. When the multiplexer 117 is not provided, the camera signal processing circuit 10
4 to (8 × 2 = 16 bits) data (luminance signal Y
And a color signal C) are output. In that case, crosstalk between two data buses occurs, crosstalk increases due to an increase in the board wiring area,
An increase in the data width of the memory causes various problems such as an increase in the size of the memory and an increase in power consumption of the memory. Multiplexer 117 described above
At the output side of the signal processing circuit 104,
These problems can be prevented from occurring.

Although not shown, the multiplexer 11
By providing a changeover switch at the stage preceding the input of No. 7, the mode can be changed over.
In the above, the mode in which the luminance signal Y and the chrominance signal C are multiplexed by the multiplexer 117 has been described. However, a mode in which the luminance signal Y and the chrominance signal C are directly output without passing through the multiplexer 117 may be provided.

Returning to FIG. 1, one embodiment to which the present invention can be applied will be further described. The component signals multiplexed as described above from the camera signal processing circuit 104 are supplied to the data switcher 130. The data switcher 130 has an output point a connected to an output of the camera signal processing circuit 104, and an input point b connected to a conversion circuit 134 for converting a component signal into a three primary color signal.
And an input / output point c connected to the recording / reproducing data bus 140
And The state of the data switcher 130 is determined by the mode switching signal 1 generated based on a key operation or the like by the user.
31, 132, and 133. The microcomputer 105 in FIG. 1 is provided mainly for controlling the camera unit. Although not shown, microcomputers are provided for controlling recording / reproducing operations and controlling the entire apparatus, respectively. Communication between the microcomputers is performed.

The three primary color signals R, G, and B generated by the conversion circuit 134 are supplied to a television display device, for example, a liquid crystal display 135, and a captured image is displayed on the liquid crystal display 135. The liquid crystal display 135 has 1
A color image is displayed by a non-interlace method with a period of / 60 seconds. For the recording / reproducing data bus 140,
Randomly accessible memory such as DRAM (Dynamic
Random Access Memory (141) and an encoder / decoder for data compression such as JPEG (Joint Photographi)
c Experts Group) encoder / decoder 142 is connected. High-efficiency coding other than JPEG may be used. A recording medium such as a flash memory 143 and an interface 1 for the encoder / decoder 142;
44 are connected. The operation of the DRAM 141 is controlled by an address signal and a control signal supplied from the memory controller 145.

The encoder / decoder 142 is a JPE
G, that is, adaptive DCT (Discrete Cosine Transfor
The data amount is reduced to about 1/10 by the encoding of m).
For processing such as blocking in JPEG, DRA
M141 is provided. The flash memory 143 is
The semiconductor memory retains its stored contents even when the power is turned off, and can be electrically erased and rewritten collectively for the entire memory or for each divided area. As a recording medium, a medium such as a semiconductor memory other than the flash memory may be used. Further, an interface may be provided to supply the compressed still image data to a personal computer as needed. In one embodiment of the present invention, recording means encoding an imaging signal to flash memory 1.
43, and the reproduction means the flash memory 1
43 is to read the data and decode the read data.

The above-described data switcher 130 can operate in five types depending on the connection state. This consists of a monitoring mode, a first recording mode, a second recording mode, a first reproduction mode, and a second reproduction mode. These modes include a mode switching signal 131,
132 and 133. The mode switching signals 131, 132, and 133 are generated from a recording / reproducing system control microcomputer (not shown). A mode switching signal may be generated by the microcomputer 105. In the monitoring mode, the imaging screen is displayed on the liquid crystal display 135. In the first recording mode, a desired captured image is written to the DRAM 141. In the second recording mode, image data stored in the DRAM 141 is compressed and written to the flash memory 143. In the first reproduction mode, data stored in the flash memory 143 is read, and the read data is decoded to
Write to 1. In the second reproduction mode, data in the DRAM 141 is read and displayed on the liquid crystal display 135.

The monitoring mode is set when the output point a and the input point b of the data switcher 130 are connected and the mode switching signal 131 becomes active. In this monitoring mode, the microcomputer 105 controls the CCD of the timing controller 107
The driving circuit 109 is controlled to operate the image sensor 101 in the line thinning mode. A line from which no reading is performed occurs from the imaging element 101, and an imaging signal is read in a 1/60 second cycle. In the monitoring mode, the signal processing circuit 1
The output signal of 04 is supplied to the conversion circuit 134 via the data switcher 130, and the three primary color signals output from the conversion circuit 134 are supplied to the liquid crystal display 135 for display. Since the image sensor 101 operates in the line thinning mode, the liquid crystal display 135 can perform non-interlace display with a period of 1/60 second. The still image to be recorded can be determined by adjusting the angle of view while viewing the display on the liquid crystal display 135.

The first recording mode is a mode for recording a still image, that is, set when the output point a and the input / output point c of the data switcher 130 are connected and the mode switching signal 132 becomes active. You.
In the first recording mode, the microcomputer 10
5 controls the CCD drive circuit 109 of the timing controller 107 to operate the image sensor 101 in the full frame read mode. From the image sensor 101, all pixels, for example, 320,000 pixels are read, and an image signal is read in a 1/30 second cycle.

The image signal is processed in the camera signal processing circuit 104, and is written to the DRAM 141 through the output point a and the input / output point c of the data switcher 130 and the recording / reproducing data bus 140. Memory controller 1
Numeral 45 sets the DRAM 141 in a write state, and supplies a write address to the DRAM 141. The memory controller 145 is controlled by a microcomputer (not shown) for controlling a recording / reproducing system. One still image data is written into the DRAM 141. In the first recording mode in which image data of 1/30 second is written, an image cannot be displayed on the liquid crystal display 135. In order to minimize the time during which an image is not displayed, when writing is completed, the process shifts to the next second recording mode.

When the writing of one image data to the DRAM 141 is completed, the data switcher 130
The second recording mode is established in which the output point a and the input point b are connected. The second recording mode is a mode switching signal 13
1 is set by becoming active. In this mode, image data is read from DRAM 141. The read data is supplied to the encoder / decoder 142 via the bus 140. The encoder / decoder 142 compresses data read from the DRAM 141 by, for example, JPEG. Further, the compressed data is written to the flash memory 143. In this way,
The captured image is compressed and recorded.

In the second recording mode, the image pickup device 1
01 operates in the line thinning mode, and similarly to the monitoring mode, a signal read from the image sensor 101 at high speed is processed by the camera signal processing circuit 104, and the image signal is transmitted through the data switcher 130 and the conversion circuit 134. Is supplied to the liquid crystal display 135 to display an image. Thereby, the time during which the display of the image disappears during recording can be minimized.

In the reproduction mode, the image data written in the flash memory 143 is reproduced and displayed on the liquid crystal display 135. In the first reproduction mode, the output point a and the input point b of the data switcher 130 are connected,
It is set by the mode switching signal 131 becoming active. In this mode, the flash memory 1
Data is read from 43, and the read data is supplied to the encoder / decoder 142.

Data is decoded by the encoder / decoder 142 to generate image data. The DRAM 141 is controlled to write the image data. In this case, the memory controller 145 controls the write address of the DRAM 141 so that the decoded data is written to the DRAM 141 with the same data arrangement as in the first recording mode. A similar data arrangement may be realized by address control at the time of reading. This relationship is based on DRAM1
The conversion circuit 134 converts the digital image signal read from the
Is necessary to use the same configuration as that used in the monitoring mode when the image data is supplied to the liquid crystal display 135 via the liquid crystal display 135 and displayed on the liquid crystal display 135. In the first reproduction mode, the image sensor 101 is driven in the line thinning mode, and a captured image of the image sensor 101 is displayed on the liquid crystal display 135.

When the decoded data is written to the DRAM 141, the second reproduction mode is set. The second reproduction mode is set when the input / output point c and the input point b of the data switcher 130 are connected, and the mode switching signal 133 becomes active. DRAM 141 is set to the read state. Then, the DRA is transmitted via the recording / reproducing data bus 140, the data switcher 130, and the conversion circuit 134.
The read data of M141 is supplied to the liquid crystal display 135. Therefore, an image corresponding to the data recorded in the flash memory 143 is displayed on the liquid crystal display 135.
Can be seen. In this case, the data recorded in the flash memory 143 is full-frame data instead of line thinning data. Therefore,
The address control by the memory controller 145 realizes the same line thinning as when the image sensor 101 is driven in the line thinning mode. Thereby,
The read data of the DRAM 141 is transferred to the liquid crystal display 13.
5 can be reproduced. In this way, the still image data stored in the flash memory 143 can be reproduced and viewed on the liquid crystal display 135.

An example of the above-described solid-state imaging device 101 will be described below. FIG. 6 shows a solid-state imaging device such as a CCD.
The outline of an example of the image sensor 1 is shown. In this example, an interline system is adopted, and a photosensor (for example, a photodiode) 2 two-dimensionally arranged in an image area is provided between the photosensors 2 and signal charges from the photosensor 2 are transferred to a horizontal CCD (horizontal CCD). It has a vertical CCD (vertical transfer unit) 3 for transferring data to a transfer unit 4, and a buffer amplifier 5 connected to the horizontal CCD 4. The photo sensor 2 includes
Imaging light that has passed through a color filter having an arrangement as described below enters. One photosensor 2 and one bit in the vertical CCD 3 are configured to correspond to each other, and the signal charges from the photosensor 2 are read out to the vertical CCD 3 without mixing,
The signals of all the pixels can be sequentially transferred to the horizontal CCD 4. Then, by driving the horizontal CCD 4, the signals are transferred to the floating diffusion area, sequentially converted into voltages, and output through the buffer amplifier 5.

FIG. 7 shows a plan view of a unit pixel of the image pickup device 1 and FIG. 8 shows a structure of the vertical CCD 3. Vertical CCD3
Has a three-layer electrode, three-phase drive configuration, for example. FIG.
, 6 is a transfer channel of the vertical CCD 3, 7
Are channel stoppers for separating pixels and between pixels and transfer channels, 8, 9 and 10
Each is a transfer gate of the vertical CCD 3. The transfer gate 9 also serves as a read gate. In FIG. 7, illustration of a light shielding film and the like is omitted. As shown in FIG. 8, the transfer gates 8, 9, and 10 are formed by processing first, second, and third polycrystalline silicon electrodes.
Vertical drive pulses φV ₁ , φV ₂ and φV ₃ are applied to these transfer gates 8, 9 and 10, respectively.

When a signal is read from the photo sensor 2 to the vertical CCD 3, a transfer gate adjacent to the photo sensor 2
That is, to the transfer gate 9 also serving as a read gate, to apply a high bias voltage from the vertical transfer clock .phi.V ₂ at a high level (referred to as a read pulse). When a read pulse is supplied to the gate 9, since one pixel corresponds to one bit of the vertical CCD 3, signal charges are read from all the photosensors 2 to the vertical CCD 3.
The horizontal CCD 5 outputs one line of data according to the transfer clocks φH ₁ and φH ₂ . In addition, horizontal CCD
As 5, for example, a composite channel horizontal CCD structure can be adopted. In that case, the output unit has a two-channel configuration.

The above-described CCD image pickup device can sequentially output signals of all pixels, so that an electronic still camera,
Suitable for capturing images. However, the output time of one screen (from the upper end to the lower end of the screen) is twice as long as that of a video camera image sensor having the same number of pixels that performs interlaced output. In this example, as described above, the image signal for one screen is output at high speed by reducing the number of horizontal lines as a signal for monitoring and an image signal for automatic control such as automatic focus control. In addition, in the case of this line thinning, the vertical color sequence defined by the arrangement of the color filters is not broken. On the other hand, when capturing a captured image into the flash memory, a full-frame imaging signal (an imaging signal in which the number of lines is not thinned out) is output. Even in the case of line thinning, since the color sequence is the same as in the case of full frame, the problem that the signal processing circuit becomes complicated can be avoided.

In the above-described image sensor capable of reading all pixels, in order to reduce the number of lines, the wiring to the transfer gate (second polycrystalline silicon) 9 which contributes to the reading of the signal charges from the photosensor 2 is formed. It is possible by dividing into two. The repetition period of the color sequence is represented by N. FIG. 9 is an example of the case of (N = 2).

The arrangement of the color filters of the single-chip CCD image pickup device is such that R (filter passing red), G (filter passing green), and B (filter passing blue) are arranged as shown in FIG. 10A. (Bayer method) is known. A high-sensitivity G filter is arranged in half of the pixels. Further, a color filter having a complementary checkerboard arrangement shown in FIG. 10B is also known. In FIG. 10B, Ye, Cy, Mg
Are yellow, cyan, and magenta filters, respectively. The complementary color filter shown in FIG. 10B can be increased in resolution as compared with the primary color filter, and thus is often used in a video camera. On the other hand, the primary color filter shown in FIG. 10A is excellent in color reproducibility, and is often used in an electronic still camera.

Either a single-chip image sensor having a primary color filter or a single-chip image sensor having a complementary color filter may be used as the image sensor in the present invention. Further, although not shown, an image sensor having a G filter,
An image sensor having an array of R and B filters, wherein the positional relationship between the two image sensors is shifted in the horizontal direction or in the horizontal and vertical directions by half the pixel pitch (so-called space Picture element shifting method) may be used.

In the arrangement of FIG. 10A, the repetition period N of the vertical color sequence is (N = 2), and in the arrangement of FIG. 10B, it is (N = 4). FIG. 9 is a schematic diagram showing (N = 2) and a part of one row of the photo sensor 2, the vertical CCD 3, and the bus wiring of the gate of the vertical CCD 3 in one column in the vertical direction. Among the photosensors 2, the one provided with a diagonal line at the upper left corner corresponds to one color filter, for example, a G filter, and the one without the diagonal line corresponds to another color filter, for example, a B filter. The vertical CCD 3 is of a three-layer electrode three-phase drive type as described above, and has a 3-bit gate adjacent to the aperture pixel of the image sensor. The vertical CCD 3 has a repeating unit A,
Contains repeating unit B. Repeating unit A is gate 2
1, 22, and 23, and the repeating unit B is a gate 3
1, 32, and 33. Gates 22 and 32 are transfer and readout gates. 41, 42, 42 ', 43
Are driving pulses φV ₁ , φV ₂ , φV for vertical transfer.
₂ ′ and φV ₃ are bus wirings to be supplied respectively.

Gates 21 and 31 are connected to bus line 41, and gates 23 and 33 are connected to bus line 43. Drive pulses φV ₁ and φV ₃ are supplied to these bus lines 41 and 43, respectively. Drive pulse φV ₂
, Two buses 42 and 42 'are provided.
The repetition unit A refers to a unit in which the transfer / read gate 22 is connected to the bus 42, and the repetition unit B refers to a unit in which the transfer / read gate 32 is connected to the bus 42 '. In FIG. 9, for simplicity, only one side of the bus line is drawn, but it is usual to arrange the bus line on both sides and drive both sides.

In the above-described image pickup device, for the purpose of line thinning, the range of A × m (bits) in which repetition units A are arranged in m (m = 1, 2, 3,...) And the repetition units B are N ×
A range of B × N × a (bits) is alternately formed in the vertical direction. The example shown in FIG. 9 is (N = 2, m = 3,
a = 2). Although the values of m and a can be arbitrarily selected, even if m and a are large values,
It is necessary that (m + N × a) is smaller than the number of vertical pixels of the number of effective pixels.

In the above-described image pickup device, in the first operation mode, that is, in the full frame operation for reading out the signals of all the pixels, the repetition units A and B of the vertical CCD 3 are used.
A signal is read from the photo sensor 2 to both of them. For this purpose, the gate 2 is connected through the bus lines 42 and 42 '.
A read pulse is applied to both 2 and 32. In this case, color signals are output in a color sequence corresponding to the order of arrangement of the color filters, for example, a sequence of G, B, G, B,.

On the other hand, in the second operation mode, that is, at the time of the line thinning operation, a read pulse is applied to only the gate 22 of the repeating unit A via the bus wiring 42.
Therefore, a signal is read from the range of A × m (bit), and no signal is read from the range of B × N × a (bit). In the example of FIG. 9, a signal is generated from the (m = 3) line, and no signal is generated from the (N × a = 4) line.
Since the number of lines to be thinned is an integral multiple of N, the color sequence corresponding to the order of the color signals of the imaging output in the case of line thinning is maintained in the same relationship as in full frame readout.

FIG. 11 shows the timing for driving the image sensor, and FIG. 11A shows the timing for reading a full frame. In each horizontal blanking period, three-phase drive pulses φV ₁ , φV ₂ , φV ₂ ′,
φV ₃ is the gate 21 of the repeating unit A of the vertical CCD ₃ ,
22 and 23, and gates 31 and 32 of the repeating unit B
And 33 respectively. A read pulse is also applied to both gates 22 and 32. Thereby, signal charges are read out from all the photo sensors to the vertical CCD 3. As shown in the detailed timing chart of FIG. 11B, drive pulses φV ₁ , φV ₂ , φV ₂ ′ generated within the horizontal blanking period,
φV ₃ has three phases, and one line shift is performed depending on the line shift period. At the time of reading a full frame, one line shift is performed within each horizontal blanking period.

On the other hand, in the case of line thinning-out reading, as shown in FIG.
2, the read pulse is applied. Thereby,
The signal charge is read only from the photosensor adjacent to the repeating unit A. In the case of line thinning, signal charges are not read from the thinned line, and no signal is output. This non-signal period can be removed by repeating the line shift operation a plurality of times, as described later.

The specific configuration of the image pickup device according to the above-described embodiment is merely an example, and the present invention can use other solid-state image pickup devices. For example, the vertical CCD may have a two-layer electrode, four-phase drive structure, an image sensor of a system other than the interline system,
A solid-state imaging device using a device other than D may be used. Further, as a mode for driving the solid-state imaging device, a third operation mode in which the readout pulse φV ₂ ′ is applied and the readout pulse φV ₂ is not applied may be set.

Further, the present invention is not limited to the image pickup device having the above-described structure, and can use an image pickup device capable of selecting an all-pixel read mode or a mode in which the number of read pixels is reduced.

[0059]

As described above, according to the present invention, the capture margin when capturing the signal of the clock frequency MCK in synchronization with 3/2 MCK is increased, and the power supply voltage, the process variation, and the clock frequency MCK are further increased. This makes it more resistant to fluctuations in conditions such as the load conditions, so that data can be reliably captured.

Further, according to the present invention, since the system delay of the output signal of the multiplexer is reduced, the delay difference between the signal in the mode in which the input signal of the multiplexer is output as it is and the output signal of the multiplexer is reduced. In both modes, the same synchronization signal (HD
Etc.) can be made easier to use.

Further, according to the present invention, the circuit scale of the multiplexer can be reduced to about half.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an example of a digital electronic imaging device to which the present invention has been applied.

FIG. 2 is a block diagram of an example of a camera signal processing circuit to which the present invention has been applied.

FIG. 3 is a block diagram of a multiplexer part in the camera signal processing circuit of the present invention.

FIG. 4 is a block diagram of an embodiment of a multiplexer according to the present invention.

FIG. 5 is a timing chart showing one embodiment of the operation of the multiplexer of the present invention.

FIG. 6 is a schematic diagram illustrating a schematic configuration of an example of an image sensor that can be used in the present invention.

FIG. 7 is an enlarged plan view of a portion of one pixel of an example of an image sensor.

FIG. 8 is a schematic diagram illustrating a structure of a vertical CCD as an example of an imaging element.

FIG. 9 is a schematic diagram illustrating bus lines in one vertical column of an example of an image sensor.

FIG. 10 is a schematic diagram illustrating an example of an arrangement of color filters used in an example of an image sensor and another example.

FIG. 11 is a timing chart of a driving pulse for driving an example of an image sensor.

FIG. 12 is a block diagram of a conventional multiplexer.

FIG. 13 is a timing chart showing the operation of a conventional multiplexer.

[Explanation of symbols]

2 ... Photo sensor, 3 ... Vertical CCD, 4 ...
Horizontal CCD, 6 ... Channel of vertical CCD, 101
... image sensor, 104 ... camera signal processing circuit, 1
05: microcomputer, 107: timing controller, 130: data switcher, 1
35: liquid crystal display, 141: DRAM,
142: encoder / decoder, 143: flash memory

Claims (3)

[Claims] 1. A first sample sequence synchronized with a first clock signal of a first frequency, and a sampling rate of (１ ／) of the first sample sequence synchronized with the first clock signal. And a second sample sequence of (3/2) times the first frequency and synchronized with the second clock signal of the second frequency, and the combined output of the first and second sample sequences is output. In a signal processing device configured to generate a sample sequence, a plurality of first registers that capture and hold the first sample sequence by the second clock signal, and that store the second sample sequence in the second register Selecting a plurality of second registers to be captured and held by a clock signal; and selecting outputs of the plurality of first and second registers;
An output selector for generating the output sample sequence; and a selection signal forming means for forming a selection signal for controlling the output selector, wherein the first clock signal and the second clock signal A signal processing apparatus which selects, as the output sample sequence, a sample taken in a phase relationship excluding the unstable phase relationship between the first and second sample sequences among the three types of phase relationships. 2. The signal processing device according to claim 1, wherein the three types of phase relationships are such that a rising edge of the second clock signal is the first edge.
A first phase relationship after a rising edge of the clock signal of the second clock signal;
A second phase relationship substantially coincident with the rising edge of the clock signal, and the rising edge of the second clock signal is
And the third phase relationship before the rising edge of the clock signal
And a sample in the second sample sequence is output as the output sample sequence. 3. The signal processing device according to claim 1, wherein the output sample sequence selects four samples from the first sample sequence based on the selection signal synchronized with the second clock signal. And after that, two samples are selected from the second sample sequence.