JP4195148B2 - Solid-state imaging device and signal readout method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device and a signal reading method thereof, and in particular, for example, a plurality of light receiving elements are formed in a row direction and a column direction to receive light, and the obtained signal charges are adjacent to the light receiving elements in the row direction. The solid-state imaging device using a charge-coupled device having a transfer gate for transferring to a vertical transfer path in which a vertical transfer electrode is formed at the position, and suitable for use in reading the signal charge.
[0002]
[Prior art]
In a digital still camera or the like having a solid-state electronic image pickup device such as a charge coupled device (CCD) as an image pickup means, it is only necessary to obtain high-quality image data when recording on a recording medium. During automatic exposure metering (AE), AF (automatic focus) metering, and when shooting a subject, the digital still camera has a high-quality image of the subject image at the time of shooting. It is not necessary to display with.
[0003]
When the number of pixels of the solid-state electronic image sensor is not relatively large, approximately 640 x 480, regardless of whether it is AE, AF, shooting the subject, recording the video signal representing the subject image on the recording medium, etc. It is good to drive by the same drive system as used so far. For example, a digital camera to which a solid-state imaging device is applied, for example, is comparable to a silver salt photograph, and the number of pixels is increasing in response to a user's request for higher image quality.
[0004]
In addition, as the number of pixels of solid-state image pickup devices increases, signal processing such as AE, AF, and display of subject images on the display device is processed quickly within a predetermined time when the solid-state image pickup device is always driven with the same drive method. I can't do it. For this reason, the image data representing the subject image cannot be quickly recorded on the recording medium, and a desired photo opportunity may be missed because this processing is performed.
[0005]
In order to cope with such an increase in the number of pixels, a high-resolution, high-reliability imaging method that does not use a new optical system is used to improve the dimensional specification and yield reduction during manufacturing. Proposed in the Gazette. The proposed imaging method using a four-phase drive frame transfer type solid-state imaging device forms a potential well under one specific electrode for each field and performs imaging and readout of the signal. An image of one frame is formed and the signal accumulation time is controlled according to the difference in the effective area of the transfer electrode.
[0006]
Japanese Patent No. 2660592 also discloses a high-definition still image that enables monitoring so that an image can be captured at a desired shutter chance by setting the angle of view while viewing the subject even for a still image, as with a video such as a VTR. A camera has been proposed.
[0007]
For this purpose, Japanese Patent No. 2660594 proposes an electronic still camera that performs four-field readout as in Japanese Patent No. 2660592. Since this camera performs a blank readout in one field scan readout period after exposure and then performs a field scan readout of the pixel signal, it can eliminate smear components and shift the field after the completion of this blank readout. Since the pixel signals corresponding to the remaining fields are sequentially scanned and read out from the scanning readout for the non-fields, the influence of the dark current on the pixel signals in each field can be made uniform, and due to unevenness in luminance for each field during image reproduction The occurrence of flicker can be prevented.
[0008]
In the solid-state imaging device driving method and the solid-state imaging device disclosed in Japanese Patent No. 2721603, when there is a large vertical resolution difference between the imaging device and the monitor device that displays the captured image, for example, Flicker occurs in the direction, the dynamic resolution is lowered, processing time is long, and power loss is a problem. Charges from only two types of photoelectric conversion elements are read alternately during monitoring, one screen is read out in a 2V period to increase dynamic resolution and prevent vertical jitter, and charges from one type of photoelectric conversion elements are used during image reproduction. Is used to avoid the need to increase the drive voltage by using the same saturation charge as that at the time of still image capturing, thereby preventing power loss.
[0009]
Thus, the signal charge is read out from the solid-state imaging device, and the signal charge is thinned out and read out by AE, AF, monitor display of the subject, and the like.
[0010]
[Problems to be solved by the invention]
However, the imaging method disclosed in Japanese Patent Publication No. 60-6148 is always the same four-phase driving. For example, when a Bayer color filter is used for color imaging, all three primary colors R, G, and B are not aligned in one field readout. If thinning processing is performed under these conditions, color display cannot be performed well. Further, in this imaging method, driving is limited to four-phase driving as described above.
[0011]
Both the high-definition still image camera of Japanese Patent No. 2660592 and the electronic still image camera of Japanese Patent No. 2660592 read out four fields from a high-pixel imaging device (that is, configure one screen). When monitoring the scene to be photographed, the image data uses half of this readout, that is, two fields. However, reading of the image data used for this monitoring actually requires four fields. Although speeding up of processing is required as in the case of AE / AF metering, it takes the same time as the normal reading time, so it can be seen that it does not contribute to speeding up of processing.
[0012]
The last solid-state imaging device disclosed in Japanese Patent No. 2721603 performs a thinning process of reading out only the signal charges in the two fields and discarding the signal charges in the other two fields among the four fields of signal readout. The maximum possible decimation in this configuration is 1/4. In this configuration, even if the number of pixels is further increased, high-speed signal readout is limited by this maximum thinning.
[0013]
In this way, various methods have been studied to reduce the amount of the video signal output from the solid-state imaging device by thinning out the video signal output from the imaging unit of the solid-state imaging device and to speed up the signal processing. It is difficult to increase the degree of thinning.
[0014]
It is an object of the present invention to provide a solid-state imaging device and a signal readout method that can eliminate the drawbacks of the prior art and can increase the degree of one-layer thinning over the conventional thinning-out.
[0015]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides a plurality of light receiving elements formed in the row direction and the column direction, a vertical transfer path formed adjacent to the light receiving elements in the row direction, and formed with vertical transfer electrodes. And a transfer gate that is arranged between the light receiving element and the vertical transfer path and reads the signal charges accumulated in the light receiving element from the light receiving element to the vertical transfer path. The first transfer gate group disposed adjacent to the light receiving elements in the N + 1th, N + 5th, and N + 13th rows (N is an integer), and the N + 2th row among the light receiving elements Second transfer gate group disposed adjacent to the light receiving element, and among the light receiving elements, the light receiving elements of the (N + 3) th row, the (N + 7) th row, the (N + 11) th row, and the (N + 15) th row And a third transfer gate group disposed adjacent to the light receiving elements, and among the light receiving elements, the light receiving elements of the (N + 4) th row, the (N + 8) th row, the (N + 12) th row, and the (N + 16) th row And a fourth transfer gate group disposed adjacent to the first and second light receiving elements of the light receiving elements disposed adjacent to the light receiving elements of the (N + 6) th row, the (N + 10) th row, and the (N + 14) th row. For applying gate pulses to simultaneously apply gate pulses respectively supplied to five transfer gate groups and a sixth transfer gate group disposed adjacent to the light receiving elements of the (N + 9) th row among the light receiving elements. A signal line is connected.
[0016]
Here, in the solid-state imaging device, the above-described variable N is a value corresponding to a case where the start position where the signal charge is read is shifted. In the solid-state imaging device, the first gate to which the gate pulse to the transfer gate corresponding to the odd-numbered light receiving elements and the gate pulse to the transfer gate corresponding to the even-numbered light receiving elements are applied in different fields among the light receiving elements. It is preferable to further include a pulse output means. In this way, by applying the gate pulse to the transfer gate for the odd-numbered or even-numbered photodiodes, thinning is performed so that the data amount becomes 1/2. Interlacing is performed by alternately applying gate pulses to the transfer gates formed adjacent to the odd-numbered photodiodes and the even-numbered photodiodes.
[0017]
The apparatus further includes second gate pulse output means for simultaneously applying gate pulses to the transfer gates, and the second gate pulse output means includes the (m + 1) th row, the (m + 2) th row, the A gate pulse is simultaneously applied to the transfer gates formed adjacent to the light receiving elements in the second row among the light receiving elements in the m + 3th row and the m + 4th row (m is an integer), and the continuous pulse is applied in the even field. Of the four rows of light receiving elements, it is desirable to simultaneously apply a gate pulse to a transfer gate different from the row transfer gate applied in the odd field. In this way, even if a gate pulse is applied, the data amount can be reduced to half.
[0018]
The apparatus further includes third gate pulse output means for applying a transfer gate to a single row or simultaneously applying gate pulses to a plurality of rows, and the third gate pulse output means is continuous in each field. It is desirable to apply a gate pulse to the transfer gates of the light receiving elements in the four rows. As a result, the data amount can be reduced to 1/4.
[0019]
The apparatus may further include fourth gate pulse output means for simultaneously applying a gate pulse to transfer gates formed adjacent to the light receiving elements of the (N + 2) th row and the (N + 9) th row. By applying a gate pulse from this means, the data volume can be reduced to 1/8.
[0020]
In the solid-state imaging device according to the present invention, the transfer gates included in the same group of the first transfer gate group to the sixth transfer gate group are connected in common via the gate pulse applying signal line, thereby transferring the transfer gate. The signal charges are read out from a desired light receiving element by applying the respective gate pulses to.
[0021]
The present invention also provides a plurality of light receiving elements formed in the row direction and the column direction, a vertical transfer path formed adjacent to the light receiving elements in the row direction and formed with vertical transfer electrodes, and a vertical transfer with the light receiving elements. A signal reading method using a solid-state imaging device provided with a transfer gate disposed between the light receiving element and transferring the signal charge accumulated in the light receiving element to the vertical transfer path, and reading out the signal charge obtained by the light receiving element In this method, the first transfer gate group disposed adjacent to the light receiving elements of the (N + 1) th row, the (N + 5) th row, and the (N + 13) th row (N is an integer) among the light receiving devices. A gate pulse is applied simultaneously, and a gate pulse is simultaneously applied to a second transfer gate group disposed adjacent to the light receiving elements in the (N + 2) th row among the light receiving elements. Arranged adjacent to the light receiving elements in the 3rd, N + 7th, N + 11th and N + 15th rows A gate pulse is simultaneously applied to the third transfer gate group, and among the light receiving elements, adjacent to the light receiving elements in the (N + 4) th row, the (N + 8) th row, the (N + 12) th row, and the (N + 16) th row. A gate pulse is simultaneously applied to the fourth transfer gate group arranged in this manner, and the light receiving elements are arranged adjacent to the light receiving elements in the N + 6th row, the N + 10th row, and the N + 14th row. The gate pulse is simultaneously applied to the fifth transfer gate group, and the gate pulse is simultaneously applied to the sixth transfer gate group disposed adjacent to the light receiving elements of the (N + 9) th row among the light receiving elements. A combination of timings is supplied, and signal charges obtained are sequentially read out.
[0022]
In the signal reading method according to the present invention, a signal is read out by applying a gate pulse to the first transfer gate group to the sixth transfer gate group, so that the signal is thinned out by one layer more than the conventional thinning out. Has increased.
[0023]
Further, according to the present invention, a plurality of light receiving elements that convert incident light into electric signals by photoelectric conversion are arranged in a row direction and a column direction, and a vertical signal signal that is read in the column direction is transferred adjacent to the plurality of light receiving elements. A transfer path is arranged, and a transfer gate is formed between the vertical transfer path and each light receiving element to transfer the signal charge accumulated in each light receiving element to the vertical transfer path at a predetermined timing. A vertical drive signal including a transfer gate pulse that operates a transfer gate at a predetermined timing is supplied from a drive signal generation unit that generates a vertical drive signal to be transferred toward a horizontal transfer path to be transferred, and a signal charge is read and transferred. In a solid-state imaging device that has an imaging unit that sequentially transfers and outputs the signal charge that has reached the horizontal transfer path to the output side, and the solid-state imaging device that captures an image of the object field, this device is connected to the vertical transfer path of the imaging unit. Two vertical transfer elements for preventing mixing of the read signal charges when the signal charges accumulated in the optical element are read out are formed on each light receiving element, and the drive signal generating means is characterized when viewed in the row direction. From a predetermined light receiving element of the same color as the first color (2 ^{i + 1} −1) The signal charge accumulated in the light receiving element is read at a line interval (a variable i is a natural number), and is read from a predetermined light receiving element having the same color as the second color as seen in the row direction ( ^{i + 1} −1) It is characterized in that a vertical drive signal for reading out signal charges accumulated in the light receiving elements at row intervals is regularly generated, and signal lines for supplying the generated vertical drive signals at intervals are wired.
[0024]
Here, it is preferable that the drive signal generation unit performs vertical transfer in eight phases and generates 12 types of vertical drive signals in consideration of the supply position of the transfer gate. With this setting and signal supply, a thinning process of 1/4 or more can be performed.
[0025]
Among the 12 types of vertical drive signals supplied from the drive signal generation means, the signal line includes a first vertical drive signal to a third vertical drive signal, a fifth vertical drive signal to a seventh vertical drive signal, A transfer gate pulse is supplied at a predetermined timing with respect to the ninth vertical drive signal and the eleventh vertical drive signal, and a vertical drive signal having a signal level indicating an input of the transfer gate pulse is supplied. 1 + 16j rows of signal lines for supplying drive signals (variable j is an integer), 6 + 8j rows of signal lines for supplying sixth vertical drive signals, and 9 + 16j for supplying third vertical drive signals Each of the row signal lines is preferably connected in common. With this connection, the field signal is thinned out by a quarter (corresponding to pattern A in FIG. 50).
[0026]
Among the 12 types of vertical drive signals supplied from the drive signal generation means, the signal line includes a first vertical drive signal to a third vertical drive signal, a fifth vertical drive signal to a seventh vertical drive signal, The transfer gate pulse is supplied at a predetermined timing to the ninth vertical drive signal and the eleventh vertical drive signal, and a vertical drive signal having a signal level indicating the input of the transfer gate pulse is supplied. 1 + 16j rows of signal lines supplying vertical drive signals (variable j is an integer), 2 + 16j rows of signal lines supplying fifth vertical drive signals, and 9+ supplying third vertical drive signals It is desirable that the 16j-row signal lines and the 10 + 16j-row signal lines for supplying the seventh vertical drive signal are connected in common. By this connection, the field signal is thinned by 1/4 (corresponding to pattern B in FIG. 50).
[0027]
Among the 12 types of vertical drive signals supplied from the drive signal generation means, the signal line includes a first vertical drive signal to a third vertical drive signal, a fifth vertical drive signal to a seventh vertical drive signal, The transfer gate pulse is supplied at a predetermined timing to the ninth vertical drive signal and the eleventh vertical drive signal, and a vertical drive signal having a signal level indicating the input of the transfer gate pulse is supplied. It is preferable that the 5 + 8j row (variable j is an integer) signal line for supplying the vertical drive signal and the 6 + 8j row signal line for supplying the sixth vertical drive signal are connected in common. By this connection, the field signal is decimated 1/4 (corresponding to pattern C in FIG. 50).
[0028]
Among the 12 types of vertical drive signals supplied from the drive signal generation means, the signal line includes a first vertical drive signal to a third vertical drive signal, a fifth vertical drive signal to a seventh vertical drive signal, A transfer gate pulse is supplied at a predetermined timing with respect to the ninth vertical drive signal and the eleventh vertical drive signal, and a vertical drive signal having a signal level indicating an input of the transfer gate pulse is supplied. 1 + 16j rows of signal lines for supplying drive signals (variable j is an integer), 2 + 16j rows of signal lines for supplying fifth vertical drive signals, and 9 + 16j for supplying third vertical drive signals A row signal line, a 10 + 16j row signal line for supplying a seventh vertical drive signal, a 5 + 8j row signal line for supplying a second vertical drive signal, and a sixth vertical drive signal are supplied. Each of the 6 + 8j rows of signal lines to be connected is made common connection, and the first, third, and fifth Preliminary seventh and vertical drive signals and the vertical drive signal of the second and sixth is advantageously fed alternately every field. This connection realizes 2: 1 interlace scanning while scanning the vertical drive signal for each field and thinning each field signal by 1/4.
[0029]
Among the 12 types of vertical drive signals supplied from the drive signal generation means, the signal line includes a first vertical drive signal to a third vertical drive signal, a fifth vertical drive signal to a seventh vertical drive signal, A transfer gate pulse is supplied at a predetermined timing with respect to the ninth vertical drive signal and the eleventh vertical drive signal, and a vertical drive signal having a signal level indicating an input of the transfer gate pulse is supplied. It is preferable that a signal line of 1 + 16j rows (variable j is an integer) for supplying a drive signal and a signal line of 2 + 16j rows for supplying a fifth vertical drive signal are connected in common. With this connection, the field signal is thinned by 1/8 (corresponding to pattern D in FIG. 50).
[0030]
Among the 12 types of vertical drive signals supplied from the drive signal generation means, the signal line includes a first vertical drive signal to a third vertical drive signal, a fifth vertical drive signal to a seventh vertical drive signal, A transfer gate pulse is supplied at a predetermined timing with respect to the ninth vertical drive signal and the eleventh vertical drive signal, and a vertical drive signal having a signal level indicating the input of the transfer gate pulse is supplied. It is preferable that the 9 + 16j line (variable j is an integer) signal line for supplying the drive signal and the 10 + 16j line signal line for supplying the seventh vertical drive signal are connected in common. With this connection, the field signal is thinned by 1/8 (corresponding to pattern E in FIG. 50).
[0031]
Among the 12 types of vertical drive signals supplied from the drive signal generation means, the signal line includes a first vertical drive signal to a third vertical drive signal, a fifth vertical drive signal to a seventh vertical drive signal, A transfer gate pulse is supplied at a predetermined timing with respect to the ninth vertical drive signal and the eleventh vertical drive signal, and a vertical drive signal having a signal level indicating an input of the transfer gate pulse is supplied. It is desirable that the signal lines of 1 + 16j rows (variable j is an integer) for supplying the drive signal and the signal lines of 10 + 16j row for supplying the seventh vertical drive signal are connected in common. With this connection, the field signal is thinned by 1/8 (corresponding to pattern F in FIG. 50).
[0032]
Among the 12 types of vertical drive signals supplied from the drive signal generation means, the signal line includes a first vertical drive signal to a third vertical drive signal, a fifth vertical drive signal to a seventh vertical drive signal, A transfer gate pulse is supplied at a predetermined timing with respect to the ninth vertical drive signal and the eleventh vertical drive signal, and a vertical drive signal having a signal level indicating an input of the transfer gate pulse is supplied. 1 + 16j rows of signal lines for supplying drive signals (variable j is an integer), 2 + 16j rows of signal lines for supplying fifth vertical drive signals, and 9 + 16j for supplying third vertical drive signals Each of the row signal lines and the 10 + 16j row signal lines for supplying the seventh vertical drive signal are connected in common, and the first and fifth vertical drive signals are connected to the third and seventh rows. The vertical drive signal may be supplied alternately for each field. This connection realizes 2: 1 interlaced scanning while scanning the vertical drive signal for each field and decimating each field signal by 1/8.
[0033]
The signal line commonly connects the signal line of 1 + 16j row (the variable j is an integer) that supplies the first vertical drive signal and the signal line of 9 + 16j row that supplies the third vertical drive signal. It is preferable that a signal line of 2 + 16j rows supplying 5 vertical drive signals and a signal line of 10 + 16j rows supplying a seventh vertical drive signal are connected in common. By this connection, this device is limited to 1/4 thinning out so as to satisfy the miniaturization of the device.
[0034]
The signal line commonly connects a signal line of 2 + 16j line (variable j is an integer) that supplies the second vertical drive signal and a signal line of 9 + 16j line that supplies the third vertical drive signal. The 6 + 16j rows of signal lines that supply 6 vertical drive signals and the 10 + 16j rows of signal lines that supply the seventh vertical drive signal may be connected in common. As a result, this device cannot perform 1/4 decimation but can perform 1/8 decimation.
[0035]
The signal line commonly connects a signal line of 5 + 8j rows (variable j is an integer) that supplies the second vertical drive signal and a signal line of 9 + 16j rows that supplies the third vertical drive signal. The signal lines of 2 + 16j rows that supply 5 vertical drive signals and the signal lines of 6 + 8j rows that supply the sixth vertical drive signal may be connected in common. In this case, too, this device cannot perform 1/4 thinning, but can perform 1/8 thinning.
[0036]
When the variable i is 1 or more, the drive signal generation means 2 ^-i A minimum of 2 that includes the sum of the number of driving to be distinguished from the number of phases to be driven. ^{i + 1} The vertical drive signal may be supplied as a set. Thereby, the rule of the thinning process becomes clear.
[0037]
In the solid-state imaging device according to the present invention, two vertical transfer elements for preventing mixing of the read signal charges are provided for each light receiving element, and the first color that is characteristic when viewed in the row direction from the drive signal generation unit is provided. For example, from a light receiving element at a predetermined reading start position of color B and the same color as this color (2 ^{i + 1} −1) The second color that is characteristic when viewed in the row direction is set to, for example, color R at a line interval (variable i is a natural number) from the light receiving element at a predetermined readout start position of the same color as this color (2 ^{i + 1} −1) A vertical drive signal for regularly reading out signal charges at a row interval is generated, and a signal line for supplying the generated vertical drive signal at this interval is wired so that the field signal is 1/4, 1 / It is easy to read out the signal charge that reads out only 8 lines and thins out the remaining lines. When i = 2, decimate every 7 lines. When i = 3, 1/8 thinning is performed every 15 lines.
[0038]
In the present invention, a plurality of light receiving elements that convert incident light into electric signals by photoelectric conversion are arranged in the row direction and the column direction, and a vertical signal charge that is read in the column direction adjacent to the plurality of light receiving elements is transferred. A transfer path is arranged, and a transfer gate is formed between the vertical transfer path and each light receiving element to transfer the signal charge accumulated in each light receiving element to the vertical transfer path at a predetermined timing. A vertical drive signal including a transfer gate pulse that operates a transfer gate at a predetermined timing is supplied from a drive signal generation unit that generates a vertical drive signal to be transferred toward a horizontal transfer path to be transferred, and a signal charge is read and transferred. In this signal reading method, an image pickup means for sequentially transferring and outputting the signal charge reaching the horizontal transfer path to the output side is output, and the signal charge obtained by picking up an image of the object scene is read from the image pickup means. In this method, two vertical transfer elements for preventing mixing of the signal charges read when the signal charges accumulated in the light receiving elements are read in the vertical transfer path of the image pickup means are formed on each light receiving element in two rows. (2) from a predetermined light receiving element of the same color as the first color that is characteristic ^{i + 1} −1) Based on the line spacing (i is a natural number) and a predetermined light receiving element of the same color as the second color that is characteristic in the row direction (2 ^{i + 1} −1) An image pickup means provided with a signal line for supplying a vertical drive signal indicating an input of a transfer gate pulse at a row interval is connected to (2 ^{i + 1} −1) The accumulated signal charges are read out by regularly applying vertical drive signals corresponding to the first color and the second color to the row interval.
[0039]
Here, it is preferable that the vertical drive signals are generated in 12 phases in consideration of the supply positions of the transfer gates, as well as the vertical direction transfer signals having eight phases.
[0040]
Among the 12 types of vertical drive signals, the first vertical drive signal through the third vertical drive signal, the fifth vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal. The transfer gate pulse is supplied at a predetermined timing to the signal level indicating the input of the transfer gate pulse, and the first vertical drive signal and the signal line in the signal line 1 + 16j row (the variable j is an integer) Preferably, the sixth vertical drive signal is supplied to the 6 + 8j rows and the third vertical drive signal is supplied simultaneously to the signal lines 9 + 16j for each field. By this driving, the field signal is thinned by 1/4 (corresponding to pattern A in FIG. 50).
[0041]
Among the 12 types of vertical drive signals, the first vertical drive signal through the third vertical drive signal, the fifth vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal. The transfer gate pulse is supplied at a predetermined timing to the signal level indicating the input of the transfer gate pulse, and the first vertical drive signal and the signal line in the signal line 1 + 16j row (the variable j is an integer) Supply the fifth vertical drive signal to the 2 + 16j row, the third vertical drive signal to the signal line 9 + 16j row, and the seventh vertical drive signal to the signal line 10 + 16j row simultaneously for each field. Is desirable. By this driving, the field signal is thinned by 1/4 (corresponding to pattern B in FIG. 50).
[0042]
Among the 12 types of vertical drive signals, the first vertical drive signal through the third vertical drive signal, the fifth vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal. The transfer gate pulse is supplied at a predetermined timing to the signal level indicating the input of the transfer gate pulse, and the second vertical drive signal is supplied to the signal line 5 + 8j row (variable j is an integer); It is preferable that the sixth vertical drive signal is simultaneously supplied to the signal lines 6 + 8j for each field. By this driving, the field signal is thinned by 1/4 (corresponding to pattern C in FIG. 50).
[0043]
Among the 12 types of vertical drive signals, the signal lines include a first vertical drive signal through a third vertical drive signal, a fifth vertical drive signal through a seventh vertical drive signal, a ninth vertical drive signal, A transfer gate pulse is supplied to 11 vertical drive signals at a predetermined timing, the signal level indicates the input of this transfer gate pulse, and the first vertical drive is performed on signal line 1 + 16j rows (variable j is an integer). A signal, a fifth vertical drive signal on signal line 2 + 16j, a third vertical drive signal on signal line 9 + 16j, a seventh vertical drive signal on signal line 10 + 16j, and a signal line The second vertical drive signal is supplied to the 5 + 8j row and the sixth vertical drive signal is supplied to the signal line 6 + 8j row. The vertical drive signals are supplied to the first, third, fifth and fifth lines, respectively. It is desirable to supply the seventh vertical drive signal and the second and sixth vertical drive signals alternately for each field. By this driving, 2: 1 interlaced scanning can be performed with 1/4 decimation as a field signal (interlaced scanning of patterns B and C in FIG. 50).
[0044]
Among the 12 types of vertical drive signals, the first vertical drive signal through the third vertical drive signal, the fifth vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal. The transfer gate pulse is supplied at a predetermined timing to the signal level indicating the input of the transfer gate pulse, and the first vertical drive signal and the signal are sent to the signal line 1 + 16j rows (the variable j is an integer) It is preferable that the fifth vertical drive signal is simultaneously supplied to the line 2 + 16j for each field. By this driving, the field signal is thinned by 1/8 (corresponding to pattern D in FIG. 50).
[0045]
Among the 12 types of vertical drive signals, the first vertical drive signal through the third vertical drive signal, the fifth vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal. The transfer gate pulse is supplied at a predetermined timing to the signal level indicating the input of the transfer gate pulse, the third vertical drive signal and the signal are sent to the signal line 9 + 16j rows (variable j is an integer), It is preferable to supply the seventh vertical drive signal to the line 10 + 16j row simultaneously for each field. By this driving, the field signal is thinned by 1/8 (corresponding to pattern E in FIG. 50).
[0046]
Among the 12 types of vertical drive signals, the first vertical drive signal through the third vertical drive signal, the fifth vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal. The transfer gate pulse is supplied at a predetermined timing to the signal level indicating the input of the transfer gate pulse, and the first vertical drive signal and the signal line in the signal line 1 + 16j row (the variable j is an integer) It is preferable to supply the seventh vertical drive signal to the 10 + 16j rows simultaneously for each field. By this driving, the field signal is thinned by 1/8 (corresponding to pattern F in FIG. 50).
[0047]
Among the 12 types of vertical drive signals, the first vertical drive signal through the third vertical drive signal, the fifth vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal. A transfer gate pulse is supplied at a predetermined timing to a signal level indicating the input of the transfer gate pulse, and a first vertical drive signal and a signal are sent to a signal line 1 + 16j row (variable j is an integer), A fifth vertical drive signal is supplied to the line 2 + 16j, a third vertical drive signal is supplied to the signal line 9 + 16j, and a seventh vertical drive signal is supplied to the signal line 10 + 16j. It is advantageous if the signal is supplied alternately with the first and fifth vertical drive signals and the third and seventh vertical drive signals for each field. By this driving, 2: 1 interlaced scanning can be performed with 1/8 decimation as a field signal (interlaced scanning of patterns D and E in FIG. 50).
[0048]
The first vertical drive signal and the third vertical drive signal are regarded as the same vertical drive signal and are supplied to the signal line 1 + 16j row (variable j is an integer) and the signal line 9 + 16j row, and the fifth vertical drive signal is supplied. The drive signal and the seventh vertical drive signal are preferably regarded as the same vertical drive signal and supplied to the signal line 2 + 16j and the signal line 10 + 16j. By this drive, the type of drive signal can be reduced from 12 to 10.
[0049]
First 5 The vertical drive signal and the third vertical drive signal are regarded as the same vertical drive signal and are supplied to the signal line 2 + 16j row (the variable j is an integer) and the signal line 9 + 16j row, and the sixth vertical drive signal And the seventh vertical drive signal are preferably regarded as the same vertical synchronizing signal and supplied to the signal line 6 + 16j and the signal line 10 + 16j. By this drive, the type of drive signal can be reduced from 12 to 10.
[0050]
The second vertical drive signal and the third vertical drive signal are regarded as the same vertical drive signal and supplied to the signal line 5 + 8j row (variable j is an integer) and the signal line 9 + 16j row, and the fifth vertical drive signal is supplied. It is preferable that the drive signal and the sixth vertical drive signal are regarded as the same vertical drive signal and supplied to the signal lines 2 + 16j and the signal lines 6 + 8j. This drive can also reduce the type of drive signal from 12 to 10.
[0051]
In the signal readout method according to the present invention, two vertical transfer elements for preventing mixing of signal charges are formed on each light receiving element, and the first color (color B) that is characteristic when viewed in the row direction is formed. (2) from the light receiving element placed at the predetermined signal charge readout start position of the same color ^{i + 1} −1) A light receiving element arranged at a predetermined signal charge read start position different from the previous position of the same color as the second color (color R), which is characteristic when viewed in the row direction, and the row interval (i is a natural number). Based on (2 ^{i + 1} −1) Using image pickup means in which a signal line for supplying a vertical drive signal indicating the input of the transfer gate pulse at a row interval is wired (2) ^{i + 1} -1) By thinning out 1/8 thinning, which was difficult with conventional readout, by reading out the stored signal charge by regularly applying vertical drive signals corresponding to the first and second colors to the row spacing. Enable reading.
[0052]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of a solid-state imaging device and a signal readout method according to the present invention will be described in detail with reference to the accompanying drawings.
[0053]
A case where the solid-state imaging device of the present invention is applied to a digital still camera 10 will be described with reference to FIGS.
[0054]
As shown in FIG. 1, the digital still camera 10 includes an imaging system 10A, a signal processing system 10B, a drive signal generation unit 10C, a signal output system 10D, a mode designation unit 10E, and a system control unit 12.
[0055]
The imaging system 10A includes an imaging lens 102, an imaging unit 104, an AF adjustment unit 106 including a focus adjustment mechanism, and an AE adjustment unit 108 including a diaphragm mechanism. In addition, although not shown, a shutter mechanism may be included on the incident light side of the imaging unit 104 in order to completely block the incident light. The imaging lens 102 is an optical system that condenses incident light from the object field so as to focus on the light receiving surface of the imaging unit 104.
[0056]
The imaging unit 104 is two-dimensionally arranged in the row direction and the column direction so that a light receiving surface is formed by a light receiving element 104a that photoelectrically converts supplied incident light (see the pixel array in FIG. 2). In the imaging unit 104, a color filter that separates incident light from the light receiving element 104a to the incident light side is integrally formed with a single plate as a color separation filter CF corresponding to each of the light receiving elements 104a. With the arrangement of the color separation filter CF, incident light that has been color-separated so as to have the respective color attributes of the three primary colors RGB, for example, enters the light receiving element 104a. Since this relationship is formed integrally, the color selected for transmission in the frame indicating the light receiving (or sensitivity) region of each light receiving element 104a is represented by symbols R, G, and B. Further, the arrangement of the color filters R, G, and B in FIG. 2 is a pattern called a Bayer arrangement.
[0057]
Here, a schematic configuration of the imaging unit 104 and signal charge transfer will be briefly described. The imaging unit 104 responds to drive signals output from drive signal generation units 10C described later. Each light receiving element 104a is constituted by a charge coupled device (hereinafter referred to as CCD). As shown in FIG. 2, the light receiving element 104a is a transfer gate that reads a signal so as not to leak signal charges received and converted between the transfer element adjacent to the light receiving element, that is, a vertical transfer element. 104b is formed. The transfer gate 104b transfers the signal charge from the light receiving element 104a to the vertical transfer path 104c by a transfer gate pulse (or field shift pulse) TG supplied through the electrodes. The vertical transfer path 104c sequentially transfers the read signal charges in the column direction, that is, in the vertical direction toward the horizontal transfer path 104d. The signal charge obtained by the vertical transfer is supplied to the horizontal transfer path 104d that transfers the signal charge in the row direction. The horizontal transfer path 104d receives a drive signal (φH _n The signal charge is output to the signal processing system 10B via the amplifier 104e.
[0058]
As is apparent from FIG. 2, the image pickup unit 104 of the present embodiment has vertical transfer paths 104c formed in units of eight. Therefore, the vertical drive of the imaging unit 104 is performed in eight phases. And the vertical drive signal is φV _1a , φV _1b , φV ₂ , φV _3a , φV _3b , φV _Four ~ ΦV ₈ In total, 10 types of signals are supplied. Since these vertical drive signals are supplied separately, it can be seen that 10 types of electrodes are formed. With this configuration, all-pixel readout can be normally performed. A more specific connection configuration of the imaging unit 104 will be described in detail later.
[0059]
The AF adjustment unit 106 adjusts this position so that the imaging lens 102 is placed at an optimum position according to information obtained by measuring the distance between the subject and the camera 10 by a focus adjustment mechanism (not shown). Has the function to perform. At this time, the calculation of the distance measurement information and the control amount from the distance measurement information are processed by the system control unit 12. As a result, the AF adjustment unit 106 drives the focus adjustment mechanism in accordance with the supplied control signal. The imaging lens 102 is moved by driving the focus adjustment mechanism.
[0060]
The AE adjustment unit 108 displaces the aperture position of the aperture mechanism under the control of an exposure control unit (not shown) provided in the system control unit 12 that calculates the photometric value of the object scene including the subject. As a result, it has a function of adjusting the amount of incident light flux. Photometry uses part of the image signal. Also in this case, the exposure amount is calculated based on the photometric value by the system control unit 12, and a control signal for controlling the aperture value and the shutter speed value so as to be the exposure amount is supplied to the AE adjustment unit 108. The AE adjustment unit 108 adjusts the aperture mechanism and the shutter mechanism in accordance with this control signal. This adjustment can optimize the exposure. The imaging unit 104 outputs the obtained imaging signal to the signal processing system 10B. Further, the digital still camera 10 can perform strobe photography, and for this purpose, a strobe device (not shown) driven by the drive signal generation unit 10C is included.
[0061]
The signal processing system 10B includes a preprocessing unit 110, an A / D conversion unit 112, a signal processing unit 114, a buffer unit 116, and a compression / decompression processing unit 118. For example, the preprocessing unit 110 performs correlated double sampling (CDS) processing on the supplied signal charge to reduce noise, or performs gamma conversion processing (gamma correction) on the signal and amplifies this signal. And output to the A / D converter 112. The preprocessing unit 110 performs a series of these analog signal processing.
[0062]
The A / D conversion unit 112 samples and quantizes an analog signal supplied from the imaging unit 104 using a clock signal from the signal generation unit 120 that generates a control signal, a timing signal, and the like from the system control unit 12 Therefore, it has a function of converting into a digital signal. The converted digital signal is supplied to the signal processing unit 114.
[0063]
The signal processing unit 114 has a function of performing signal processing according to each of the two modes after performing automatic aperture adjustment (AE), white balance adjustment (AWB), aperture correction, and the like on the obtained signal. That is, the mode here indicates a mode set by a release shutter 128 of a mode designating unit 10E described later. This mode includes, for example, a still image shooting mode in which the obtained still image is taken into the recording / reproducing unit 126 of the signal output system 10D and a photometric control mode in AF of the imaging system 10A. The gamma correction processing may be performed here or may be performed at a later stage.
[0064]
In the digital still camera 10, which mode is currently selected is controlled by a control signal from the system control unit 12. Under the control of the system control unit 12, the signal after the above-described signal processing is subjected to signal processing accompanying predetermined digital in the still image shooting mode, for example, a higher band of a luminance signal. On the other hand, in the photometric control mode, taking into account that the supplied signal is digital, the system controller 12 reads out the signal from the imaging unit 104 faster than, for example, the conventional readout speed and its processing. Is done. In addition to this, vertical thinning processing or the like is also performed so that the imaging signal is displayed on the display unit 124 of the signal output system 10D. The image data obtained by this vertical thinning, which is a feature of the present invention, is supplied to the display unit 124 to read out signals corresponding to the increase in pixels. The signal processing unit 114 converts the image pickup signal from the image pickup unit 104 into a recordable video signal by signal processing in the still image shooting mode. Then, the signal processing unit 114 outputs the signal of the mode selected for display / recording to the buffer unit 116. The signal processing unit 114 may generate luminance data Y and color data C, that is, color difference data (BY) and (RY), from the supplied image data.
[0065]
The buffer unit 116 amplifies the video signal supplied from the signal processing unit 114 described above to a predetermined amplitude, and also has a function of time adjustment at the time of recording. The buffer unit 116 outputs an image to the signal output system 10D or the compression / expansion signal unit 118 under the control of a recording control unit (not shown) disposed in the system control unit 12.
[0066]
When recording an image, the compression / decompression signal unit 118 is supplied to the system control unit 12 by an image signal. The supplied image signal is subjected to compression processing based on, for example, JPEG (Joint Photographic coding Experts Group) standard. Further, when the recorded signal is read from the recording / reproducing unit 126 and reproduced, the original image signal is reproduced by performing signal processing such as inverse conversion of the compression processing described above and output to the display unit 124.
[0067]
The drive signal generation unit 10C includes a signal generation unit 120 and a driver unit 122. For example, the signal generator 120 generates a synchronization signal based on the original oscillation clock generated so that the digital still camera 10 is driven by the current broadcasting system (NTSC / PAL), and supplies it to the signal processor 114. . In the signal generation unit 120, signals are supplied to the preprocessing unit 110, the A / D conversion unit 112, the buffer unit 116, and the compression / decompression processing unit 118 as clocks for sampling signals and write / read signals.
[0068]
The signal generation unit 120 includes an oscillator and a timing generation unit (not shown), generates a synchronization signal from the original oscillation clock, and has a function of generating various timing signals using these signals. Yes. The generated timing signal includes a timing signal used for reading the signal charge obtained by the imaging unit 104, for example, a vertical timing signal for supplying driving timing for the vertical transfer path, and a horizontal timing for supplying driving timing for the horizontal transfer path. There are signals, timing signals for field shifting and line shifting. Further, the signals from the signal generator 120 are also used when controlling the operations of the AF adjustment unit 106 and the AE adjustment unit 108 (signal lines are not shown in FIG. 1). As described above, various signals are output to the above-described units, and the signal generation unit 120 supplies a vertical timing signal and a horizontal timing signal to the driver unit 122. Among these, when the control signal of the photometry control mode is supplied from the system control unit 12 to the signal generation unit 120, the signal generation unit 120, for example, if necessary (for example, in the photometry control mode) A signal for increasing the substrate voltage, that is, the overflow drain voltage, to the light receiving elements of the colors R and B is also supplied. By supplying this signal, the same state as that in which no signal charge is generated can be formed in the light receiving elements of colors R and B. In the photometric control mode, the signal generator 120 generates a transfer gate pulse so as to read out the signal charge of only the color G 1. When the photometric control mode is selected, the signal generator 120 selectively switches the generation of the timing signal by the control signal 12A from the system controller 12. The driver unit 122 generates a drive signal at each supplied timing. In general, in order to change the speed at which a signal is read, a vertical drive signal output from the driver unit 122 is supplied to the imaging unit 104 in accordance with the mode, and for example, driving the entire screen, selective driving of colors, colors and regions The speed is changed by driving with designation.
[0069]
The driver unit 122 is supplied with a driving signal corresponding to the mode, particularly when the mode is set to the photometry control mode or the display mode, and for example, driving the entire screen, selective driving of colors, color and area are selected. The speed is changed by the designated driving.
[0070]
The driver unit 122 outputs a driving signal corresponding to the mode when the mode is set to the photometry control mode or the display mode. When the drive signal level is changed in the mode, a level change switch is provided for switching. Generally, the voltage level to be set includes, for example, 1V, 5V, 8V, and 12V. The driver unit 122 generates drive signals in accordance with various timing signals (vertical drive timing signal, horizontal timing drive signal, transfer gate pulse, etc.) supplied from the signal generation unit 120. The driver unit 122 uses a vertical timing signal and a transfer gate pulse, for example, to generate a ternary vertical drive signal φV. _n (See FIG. 3).
[0071]
The signal output system 10D is provided with a display unit 124 and a recording / reproducing unit 126. The display unit 124 includes, for example, a VGA (Video Graphics Array) standard liquid crystal display monitor with digital RGB input or a display monitor for displaying YC data. The display unit 124 is supplied with not only the image data read from the buffer unit 116 but also the image data expanded from the recording / reproducing unit 126 via the compression / decompression processing unit 118. The display unit 124 displays a subject image obtained by imaging on the screen. Here, in particular, when a captured image is directly displayed, a thinned image is supplied.
[0072]
The recording / reproducing unit 126 has a configuration for recording a video signal supplied to a magnetic recording medium, a semiconductor memory used for a memory card or the like, an optical recording medium, or a magneto-optical recording medium. In addition, the recording / reproducing unit 126 has a function of reading the recorded video signal, and can display the read image data on the display unit 124. When the recording / reproducing unit 126 can detach the recording medium, only the recording medium may be removed and a video signal recorded by an external device may be reproduced and displayed or an image may be printed.
[0073]
The mode designating unit 10E is provided with a release shutter 128 and a key switch 130. In this embodiment, the release shutter 128 has a two-step push function. That is, in the first-stage half-pressed state, the photometry control mode is designated and a signal indicating that this mode setting has been made is supplied as a signal to the system control unit 12, and in the second-stage fully pressed state, an image is captured. The timing is provided to the system control unit 12, and this operation supplies the system control unit 12 with a signal that image recording setting (still image shooting mode) has been performed. Further, when the release shutter 128 is in a power-on state and an image monitor display switch (not shown) is turned on, the system control unit 12 controls the display unit 124 to display a moving image in the movie mode. . The key switch 130 is used to select an item / image by moving the cursor in the screen displayed on the screen of the display unit 124 up / down / left / right with the cross key. The selected information is also sent to the system control unit 12.
[0074]
The system control unit 12 is a controller that controls the operation of the entire camera. The system control unit 12 includes a central processing unit (CPU). The system control unit 12 determines which mode is selected based on the input signal from the release shutter 128. Further, the system control unit 12 controls the processing for the image signal of the camera and the like based on the selection information from the key switch 130. Based on the supplied information, the system control unit 12 controls the operation of the drive signal generation unit 10C based on the determination result. Although not shown, the system control unit 12 is provided with a recording control unit. The recording control unit controls the operation of the buffer unit 116 and the recording / reproducing unit 126 of the signal output system 10D according to the timing control signal from the system control unit 12.
[0075]
Here, a connection relationship (represented by a supply destination) between a drive signal supplied to the imaging unit 104 and a signal line that supplies the drive signal will be described with reference to FIG. In the imaging unit 104, photodiodes that are light receiving elements 104a are formed at predetermined intervals in the row direction and the column direction. Color filters CF are arranged on the light receiving surfaces of these light receiving elements 104a. For these color filter arrays, a so-called Bayer array in which the array of the next row is arranged as “... RGRGRG. The filter array is not limited to this array.
[0076]
As described above, the vertical transfer paths 104c for transferring signal charges are formed adjacent to the light receiving elements 104a and corresponding to the number of columns formed by the light receiving elements 104a. The vertical transfer path 104c forms two vertical transfer CCDs between the light receiving elements 104a. Between the light receiving element 104a and the vertical transfer path 104c, there is formed a transfer gate 104b that transfers the signal charge accumulated in each light receiving element 104a to the vertical transfer path 104c. In the vertical transfer path 104c, a vertical transfer electrode for transferring the signal charge transferred from the light receiving element 104a in the column direction is formed. The vertical transfer electrode is provided in each of two CCDs formed corresponding to one light receiving element 104a (one light receiving element 104a corresponds to one pixel). Vertical drive signal φV to vertical transfer electrode _n , The signal charges are transferred in the column direction in the vertical transfer path 104c.
[0077]
The correspondence between the light receiving element and the vertical transfer electrode is as follows. Where N is an integer. That is,
The light receiving elements 104a in the (N + 1) th row—vertical transfer electrodes E1b, E2,
N + 2th row light receiving element 104a-vertical transfer electrodes E3a, E4,
N + 3th row light receiving element 104a-vertical transfer electrodes E5, E6,
N + 4th row light receiving element 104a-vertical transfer electrodes E7, E8,
N + 5th row light receiving element 104a-vertical transfer electrodes E1b, E2,
N + 6th row light receiving element 104a-vertical transfer electrodes E3b, E4,
N + 7th row light receiving element 104a-vertical transfer electrodes E5, E6,
N + 8th row light receiving element 104a-vertical transfer electrodes E7, E8,
N + 9th row light receiving element 104a-vertical transfer electrodes E1a, E2,
N + 10th row light receiving element 104a-vertical transfer electrodes E3b, E4,
N + 11th row light receiving element 104a-vertical transfer electrodes E5, E6,
N + 12th row light receiving element 104a-vertical transfer electrodes E7, E8,
N + 13th row light receiving element 104a-vertical transfer electrodes E1b, E2,
N + 14th row light receiving element 104a-vertical transfer electrodes E3b, E4,
N + 15th row light receiving element 104a-vertical transfer electrodes E5, E6, and
The light receiving elements 104a in the (N + 16) th row—vertical transfer electrodes E7 and E8 are formed. in this way
The electrodes of the vertical transfer path 104c for the light receiving elements 104a from the (N + 1) th row to the (N + 16) th row are periodically configured. The electrodes denoted by the same reference numerals for the vertical transfer electrodes indicate that signal lines for supplying vertical drive signals are commonly connected.
[0078]
For this electrode configuration, the vertical drive signal φV from the driver 122 of the drive signal generator 10C _n And horizontal drive signal φH _n Is formed. Signal line is vertical drive signal φV _1b , φV ₂ , φV _3a , φV _Four , φV _Five , φV ₆ , φV ₇ , φV ₈ , φV _3b And φV _1a Are provided to the vertical transfer electrodes E1b, E2, E3a, E4, E5, E6, E7, E8, E3b and E1a, respectively.
[0079]
More specifically, the transfer gate pulse TG is simultaneously applied to the transfer gate 104b formed adjacent to the light receiving elements 104a in the (N + 1) th row, the (N + 5) th row, and the (N + 13) th row. _1b Is applied. These vertical transfer paths 104c have a vertical drive signal φV. _1b Are wired so as to be supplied. Common transfer gate pulse TG _1b For example, the line number of the light receiving element supplied with _n , Next connected line number L _{n + 1} Recursion formula, that is, line number L _n And the first term a = 4, 4.2 with a common ratio of 2 ^n-2 Expressed as the sum of the geometric series of (L _{n + 1} = L _n +4 ・ 2 ^n-2 ). Where the subscript n is an integer and the first term L ₀ Is zero. As a result, it is understood that the line numbers to be connected are 1, 5, and 13 in 16 lines.
[0080]
The vertical transfer electrode E2 of the vertical transfer path 104c between the (N + 1) th row and the second row forms a common connection for every 2 + 8n vertical transfer elements. This electrode has a vertical drive signal φV ₂ Is supplied. It is formed under the vertical transfer electrode at a position separated by the fourth row from the formed pixel line. In this way, the electrodes E4, E6, E8 of the vertical transfer paths 104c between the lines of each pixel are connected in common for each of the eight vertical transfer paths 104c (4 + 8n, 6 + 8n, 8 + 8n). To do. The vertical drive signal φV is applied to the vertical transfer electrodes E4, E6, E8 of the vertical transfer path 104c. _Four , φV ₆ , φV ₈ Are supplied respectively.
[0081]
The transfer gate 104b formed adjacent to the light receiving elements 104a in the (N + 2) th row performs common line connection for every 32 vertical transfer electrodes (3 + 32n) in the vertical transfer path 104c separated by 32. This common line has a vertical drive signal φV _3a Is applied.
[0082]
The transfer gate pulse TG is simultaneously applied to the transfer gate 104b formed adjacent to the light receiving elements 104a in the (N + 3) th row, the (N + 7) th row, the (N + 11) th row, and the (N + 15) th row. _Five Is applied. The vertical transfer electrode E5 of the vertical transfer path 104c adjacent to the transfer gate 104b is (5 + 8n) or line number L _n (L _n = 3 + 4n) Make a common connection for each row. This electrode has a vertical drive signal φV _Five Is supplied.
[0083]
Similarly, the transfer gate pulse TG is applied to the transfer gate 104b formed adjacent to the light receiving elements 104a in the (N + 4) th row, the (N + 8) th row, the (N + 12) th row, and the (N + 16) th row. ₇ Is supplied. The number of electrodes E7 of the vertical transfer path 104c adjacent to the transfer gate 104b is (7 + 8n) or line number L _n (L _n = 4 + 4n) Make a common connection for each row. The vertical drive signal φV is applied to the electrode E7. ₇ Is applied.
[0084]
The transfer gate 104b formed adjacent to the light receiving elements 104a in the (N + 6) th row, the (N + 10) th row, and the (N + 14) th row is also a transfer gate pulse TG. _3b Are supplied at the same time. This transfer gate pulse TG _3b Is the transfer gate pulse TG mentioned above _3a Are supplied at the same timing. However, the electrode E3b is set to every (11 + 8n) pieces or (L) so as to be different from the connection line relationship of the vertical transfer path 104c described above. _n = 6 + 4n) Connect common lines. Accordingly, it is possible to supply the transfer gate pulse supplied at the same timing but at a timing different from that of the (N + 2) th row. These vertical transfer paths 104c have a vertical drive signal φV _3b Are simultaneously applied.
[0085]
Finally, the transfer gate pulse TG is applied to the transfer gate 104b formed adjacent to the light receiving elements 104a in the (N + 9) th row. _1a Is applied. A vertical transfer path 104c is formed adjacent to the transfer gate 104b. Again transfer gate pulse TG _1a Is the transfer gate pulse TG mentioned above _1b Is a signal supplied at the same timing. This connection also makes it possible to independently extract only this signal charge.
[0086]
A horizontal transfer path 104d for transferring the signal charge output from the vertical transfer path 104c in the horizontal direction is formed on the output side (lower side) of the vertical transfer path 104c. Horizontal drive signal φH to horizontal transfer path 104d _n Is supplied from the driver unit 122, the signal charge is transferred in the horizontal direction.
[0087]
The signal charge on the horizontal transfer path 104d is supplied to the amplifier 104e. The amplifier 104e amplifies the signal charge and outputs it. Although not shown, the imaging unit 104 converts an amplified signal (current) into a signal indicated by a voltage, and outputs the signal as a video signal representing a subject image.
[0088]
Here, the signals handled by the drive signal generator 10C will be described with reference to the timing chart of FIG. Transfer gate pulse TG output from signal generator 120 _n And vertical drive timing signal V _n And vertical transfer signal φV output from driver section 122 _n Is shown in FIG. Transfer gate pulse TG _n And vertical drive timing signal V _n Is a binary signal (H level / L level). In contrast, the vertical drive signal φV _n The driver unit 122 outputs three values (H level / M level / L level) according to the supplied signal level.
[0089]
More specifically, vertical drive timing V _n Is changed from H level to L level at time t1, the vertical drive signal φV _n Rises from the L level to the middle M level. And the vertical drive timing signal V _n Transfer gate pulse TG at time t2 when is at L level _n Falls from the H level to the L level, the vertical drive signal φV _n Becomes H level. At time t3, transfer gate pulse TG _n Rises from L level to H level, the vertical drive signal φV _n Returns to the M level. At time t4, the vertical drive timing signal V _n Becomes H level again, the vertical drive signal φV _n Becomes L level.
[0090]
The vertical drive signal φV generated in this way _n Is applied to the vertical transfer electrode formed in the vertical transfer path 104c. Vertical drive signal φV _n When is at the H level, the transfer gate 104b is turned on. At this time, the signal charge accumulated in the light receiving element 104a is transferred to the vertical transfer path 104c. The vertical transfer path 104c is connected to the vertical drive signal φV _n When M is at the M level, the signal charge is moved according to the depth of the potential formed in the vertical transfer path 104c. Thus transfer gate pulse TG _n And vertical drive timing signal V _n Is used to transfer the signal charge accumulated in the light receiving element 104a to the vertical transfer path 104c and drive control to transfer the signal charge transferred to the vertical transfer path 104c.
[0091]
Next, a first reading process when reading a video signal from the imaging unit 104 shown in FIG. 2 will be described with reference to FIGS. In the first reading process, signal charges are read from the odd-numbered light receiving elements 104a in the first field, and signal charges are read from the even-numbered light receiving elements 104a in the second field. That is, interlaced scanning for reading out pixel lines line by line is performed. When performing this reading, the vertical transfer electrode and the vertical drive signal φV applied to the vertical transfer electrode _n Is the relationship shown in FIG. To realize this relationship, vertical synchronization signal VD, vertical drive timing signal V _n And transfer gate pulse TG _n The timing is as shown in FIG. This relationship is, for example, that the transfer gate pulse TG is applied to the odd-numbered transfer gate 104b. _1a , TG _1b , TG _Five Is turned on. In addition, the transfer gate pulse TG is applied to the transfer gate 104b of the even-numbered row. _3a , TG _3b , TG ₇ Is turned on. At this time, the supply timing is shifted by one field (for example, see times t12 and t14).
[0092]
A more specific description will be given using the main part of the imaging unit 104 shown in FIG. In the imaging section 104, only the signal charges accumulated in the light receiving elements 104a in the odd-numbered rows in the first field are shown. In this first field signal readout, the horizontal synchronization signal HD and the vertical drive timing signal V _n And transfer gate pulse TG _n Is a shorter time signal than the vertical synchronizing signal VD (see FIG. 7). Therefore, when the main part (near time t13) of the timing chart shown in FIG. 7 is enlarged, the signal waveform of FIG. 8 is obtained. Vertical drive timing signal V ₁ ~ V ₈ , Transfer gate pulse TG _1a , TG _1b , TG _3a , TG _3b , TG _Five , TG ₇ Is supplied to the driver section 122. That is, in the first field, the transfer gate pulse TG is applied to the vertical transfer electrodes E1a, E1b and E5 in synchronization with the vertical synchronization signal VD rising at time t13. _1a , TG _1b And TG _Five Is given. As described above, the vertical drive timing signal V _n And transfer gate pulse TG _1a , TG _1b And TG _Five Is applied to the vertical transfer electrodes E1a, E1b, and E5 at the H level, and a potential is formed in the vertical transfer path 104c. The signal charge accumulated in the formed potential is transferred. In the vertical transfer path 104c, an 8-phase vertical drive signal φV is applied to the vertical transfer electrode. _n Is transferred, the signal charge is transferred from the vertical transfer path 104c to the horizontal transfer path 104d. The signal charge is sent from the vertical transfer path 104c to the horizontal transfer path 104d. This signal charge is transferred in the horizontal direction in the horizontal transfer path 104d and output as a video signal of the first field.
[0093]
The other drive, that is, the relationship of the second field drive is shown in FIGS. The image pickup unit 104 in FIG. 9 reads signals with a shift of one line compared to the read position in FIG. In this case, this readout line corresponds to the light receiving elements 104a in even rows. FIG. 10 shows a timing chart when this signal is read, and FIG. 11 shows an enlarged view of the main part near time t14. In the second field, the transfer gate pulse TG is applied to the vertical transfer electrodes E3a, E3b, and E7 in synchronization with the vertical synchronization signal VD that rises at time t14. _3a , TG _3b , And TG ₇ Is given. Also at time t14, the signal charges that are guarded by the light receiving elements 104a in the even-numbered rows are transferred to the vertical transfer path 104c. The vertical drive pulse φV is applied to the vertical transfer electrode formed in the vertical transfer path 104c. _n Is transferred, the signal charge transferred to the vertical transfer path 104c is transferred in the vertical direction. The signal charge is output as the video signal of the second field via the horizontal transfer path 104d as in the case of the first field. In this way, interlaced readout is performed alternately by applying the vertical transfer electrodes E1a, E1b and E5 and the vertical transfer electrodes E3a, E3b and E7 for each field. Further, each of the first field and the second field is the same as reading out the video signal output from the imaging unit 104 by thinning the number of lines to 1/2 in the vertical direction. The first reading process shows the same process as a normal signal reading.
[0094]
Next, a second reading process for reading a video signal from the imaging unit 104 will be described with reference to FIGS. Vertical transfer electrode and vertical drive pulse φV applied to the vertical transfer electrode _n FIG. 12 shows the relationship. In the second reading process, as is clear from the relationship shown in FIG. 12, the signal charges accumulated in the light receiving elements 104a in the (m + 1) th row and the (m + 2) th row are read in the first field, and in the second field. The signal charges accumulated in the light receiving elements 104a in the (m + 3) th row and the (m + 4) th row are read out. That is, it is a process of reading signal charges by two lines per field.
[0095]
FIG. 13 is a timing chart showing this relationship. This timing chart shows the vertical synchronization signal VD and the vertical drive timing signal V as described above. _n And transfer gate pulse TG _n Is marked. When interlace scanning is performed to read out one field from the light receiving element 104a line by line in the connection relation described above, the transfer gate pulse is supplied at the timing of transfer gate pulse TG. _1a , TG _1b , TG _3a , TG _3b And transfer gate pulse TG _Five , TG ₇ It can be seen that it can be realized by dividing it. When these transfer gate pulses are supplied, the line relationship read out from the main part of the imaging unit 104 in the first field is schematically shown in FIG. When the signal charges accumulated in the light receiving elements 104a in the (m + 1) th row and the (m + 2) th row of the imaging unit 104a are read as, for example, the first field, the vertical transfer electrode is synchronized with the vertical synchronization signal VD at time t22. Transfer gate pulse TG to E1a, E1b, E3a and E3b _1a , TG _1b , TG _3a And TG _3b Is supplied via the driver unit 122 (see FIG. 15). When the vicinity of time t22 is enlarged in this, each signal is supplied in the timing relationship shown in FIG. As a result, the vertical transfer electrodes E1a, E1b, E3a and E3b have an H level vertical drive signal φV. _1a , φV _1b , φV _3a , φV _3b Is given.
[0096]
At time t22, this vertical drive signal φV is applied to the vertical transfer electrodes E1a, E1b, E3a and E3b. _1a , φ _1b , φ _3a And φ _3b Is applied, the signal charges accumulated in the light receiving elements 104a in the (m + 1) th row and the (m + 2) th row in FIG. 12 are transferred to the vertical transfer path 104c. The signal charge is transferred to the horizontal transfer path 104d in the vertical direction by the 8-phase vertical drive supplied to the vertical transfer electrodes of the vertical transfer path 104c. The signal charge of the horizontal transfer path 104d is the horizontal drive signal φH _n Is transferred in the horizontal direction in response to the supply of the video signal and output as a video signal of the first field.
[0097]
In the second field signal reading in FIG. 17, signal reading is performed for every two lines other than the two lines read out earlier than in FIG. For example, in the signal readout from the light receiving elements 104a in the (m + 3) th row and the (m + 4) th row in FIG. 12, as shown in FIG. _n And transfer gate pulse TG _n Is supplied to the driver section 122. Attention is paid to the vicinity of time t23 at the timing of each signal supplied. This further enlarged vicinity of this time is shown in the timing chart of FIG. As can be seen from these figures, the transfer gate pulse TG is applied to the vertical transfer electrodes E5 and E7 shown in FIG. 12 in synchronization with the vertical synchronization signal VD at time t23. _Five And TG ₇ Vertical synchronization signal φV including _Five , φV ₇ Is given. At this time, at time t23, the vertical drive signal φV including transfer gate pulses TG5 and TG7 on the vertical transfer electrodes E5 and E7 in FIG. _Five , φV ₇ Is applied, the signal charges accumulated in the light receiving elements 104a in the (m + 3) th row and the (m + 4) th row are transferred to the vertical transfer path 104c. These transferred signal charges are converted into vertical drive pulses φV supplied to the vertical transfer electrodes. _n Is transferred to the horizontal transfer path 104d. The signal charge of the horizontal transfer path 104d is the horizontal drive signal φH _n Is transferred in the horizontal direction in response to the supply of the video signal and output as the video signal of the second field. In this case, the vertical transfer electrodes E1a, E1b, E3a and E3b and the vertical transfer electrodes E5 and E7 are alternately applied for each field, Imaging unit 104 performs interlaced scanning by reading signals in which two lines are combined. The information amount of each field is 1/2 the number of pixels in the vertical direction as compared to the information amount of one screen. From this, it can be said that the field information (image signal) is thinned out to 1/2. Compared with the first readout process, the second readout process can read out signals from positions where the readout lines are spatially adjacent to align the three primary colors RGB, thus increasing the correlation of the spatial image. can do.
[0098]
Next, a third reading process in signal reading from the imaging unit 104 will be described. 20 and 21 are used for the description. As shown in FIG. 20, the imaging unit 104 collects the signal charges accumulated in the light receiving elements 104a arranged in the m + 3th row and the m + 4th row, for every two lines, for every two lines. Reading out. That is, it is the same as the signal reading of the second field in the second reading process described above. Vertical drive timing signal V used for reading this signal _n And two transfer gate pulses TG per vertical synchronization period _n (n = 5, 7) is supplied to the driver unit 122. Vertical drive signal φV from driver unit 122 _n Is supplied, the signal charge is transferred from the light receiving element 104a only to the vertical transfer path 104c having the vertical transfer electrodes E5 and E7. As a result, only one field information (image signal) out of half of all the pixel lines in each field is selectively read and thinned out to 1/2 in the vertical direction. In other words, this signal readout process enables 1/2 decimation when all pixels are read out.
[0099]
Next, a fourth readout process in signal readout from the imaging unit 104 will be described. 22 and 23 are used for the description. As shown in FIG. 22, the imaging unit 104 collects the signal charges accumulated in the light receiving elements 104a arranged in the m + 1st row and the m + 2th row, for every two lines, for every two lines. Reading out. That is, it is the same as the signal reading of the first field in the second reading process described above. Vertical drive timing signal V used for reading this signal _n And transfer gate pulse TG for each vertical synchronization period _n (n = 1a, 1b, 3a, 3b) is supplied to the driver unit 122. Vertical drive signal φV from driver unit 122 _n Is supplied, the signal charge is transferred from the light receiving element 104a only to the vertical transfer path 104c having the vertical transfer electrodes E1a, E1b, E3a, and E3b. As a result, only half of the field information (image signal) is selectively read out of all the pixel lines in each field and thinned out to 1/2 in the vertical direction. In this case as well, the signal readout process reduces the readout amount by half compared to the case where all pixels are read out.
[0100]
Next, a fifth readout process in signal readout from the imaging unit 104 will be described. 24 to 32 are used for the description. As shown in FIG. 24, the imaging unit 104 reads the signal charge accumulated in the light receiving element 104a line by line for every four lines so as not to be read out redundantly in each field. That is, when reading out the (m + 1) th row to the (m + 4) th row during the period of 4 fields, the first field reads out the signal charges accumulated in the light receiving elements 104a in the (m + 1) th row, In the second field, the signal charges accumulated in the light receiving elements 104a in the (m + 2) th row are read out, in the third field, the signal charges accumulated in the light receiving elements 104a in the (m + 3) th row are read out, and in the fourth field The signal charges accumulated in the light receiving elements 104a in the (m + 4) th row are read out.
[0101]
In the main part of the image pickup unit 104 shown in FIG. 25, the signal charge is read from the m + 1th row of the first line in the first field, the m + 5th row of the fourth line, and the m + 9th row (m + 1 + 4n: n is an integer). When only one line selectively placed at a predetermined position is read out using the signal line connection relationship of the imaging unit 104, as shown in FIG. 26, the transfer gate pulse TG _1a And TG _1b Only to the driver section 122. At time t31, the driver unit 122 generates a vertical drive signal φV that is set to a level that turns on the transfer gates to the vertical transfer electrodes E1a and E1b. _1a , φV _1b Is applied. As a result, the signal charges accumulated in the light receiving elements 104a in the (m + 1 + 4n) rows are transferred to the vertical transfer path 104c and read out.
[0102]
In the main part of the imaging unit 104 shown in FIG. 27, in the second field, the first line in FIG. 25 is the pixel line located below the (m + 1) th row, the (m + 2) th row, and the mth line of the fourth line from that line. The signal charge is read from the + 6th line and the m + 10th line (m + 2 + 4n: n is an integer). When only one line arranged selectively at a predetermined position is read out using the connection relationship of the signal lines of the imaging unit 104, as shown in FIG. 28, the transfer gate pulse TG _3a And TG _3b Only to the driver section 122. At time t32 in the second field, the driver unit 122 sets the vertical drive signal φV set to a level for turning on the transfer gates to the vertical transfer electrodes E3a and E3b. _3a , φV _3b Is applied. As a result, the signal charges accumulated in the light receiving elements 104a in the m + 2 + 4n rows are transferred to the vertical transfer path 104c and read out.
[0103]
In the main part of the image pickup unit 104 shown in FIG. 29, in the third field, the first line in FIG. 25 is a pixel line located 2 lines below the (m + 1) th row, the (m + 3) th row, and 4 lines from that line The signal charge is read from the m + 7th row of the eye (m + 3 + 4n: n is an integer). When only one line selectively placed at a predetermined position is read out using the signal line connection relationship of the imaging unit 104, a transfer gate pulse TG is obtained as shown in FIG. _Five Only to the driver section 122. At time t33 in the third field, the driver unit 122 sets the vertical drive signal φV set to a level at which the transfer gate is turned on to the vertical transfer electrode E5. _Five Is applied. As a result, the signal charges accumulated in the light receiving elements 104a in the m + 3 + 4n rows are transferred to the vertical transfer path 104c and read out.
[0104]
In the final fourth field in the readout process, in the main part of the image pickup unit 104 shown in FIG. 31, the first line in FIG. 25 is located below the m + 1th row, the m + 4th row, Signal charges are read from the m + 8th row of the fourth line from that line (m + 4 + 4n: n is an integer). When only one line arranged selectively at a predetermined position is read out using the connection relationship of the signal lines of the imaging unit 104, as shown in FIG. 32, the transfer gate pulse TG ₇ Only to the driver section 122. At time t34 in the fourth field, the driver unit 122 sets the vertical drive signal φV set to a level for turning on the transfer gate to the vertical transfer electrode E7. ₇ Is applied. As a result, the signal charges accumulated in the light receiving elements 104a in the m + 4 + 4n rows are transferred to the vertical transfer path 104c and read out.
[0105]
By reading out the signal charges in this way, only one-fourth of one field information (image signal) is selectively read out and thinned out in the vertical direction in each field. This is called 1/4 thinning. With this connection, for example, it is possible to easily perform interlaced scanning of 4 fields simply by switching the setting.
[0106]
Next, a sixth reading process in signal reading from the imaging unit 104 will be described. FIG. 33 is used for the description. As can be seen from FIG. 33, the total number of lines for reading out signal charges in two fields is half that of the signal reading in FIG. 4 (1/2 thinning). When considering the number of signal readout lines in each field with respect to the total number of lines, 1/4 thinning is performed. Actually, in the first field, the transfer gate pulse TG is applied to the vertical transfer electrode E5. _Five Vertical drive signal φV including _Five May be applied. In the second field, the transfer gate pulse TG is applied to the vertical transfer electrode E7. ₇ May be applied.
[0107]
Next, a seventh readout process in signal readout from the imaging unit 104 will be described. FIG. 34 is used for the description. As can be seen from FIG. 34, the thinning-out amount is the same as that in the above-described sixth reading process. That is, the total number of lines for reading signal charges in two fields is half that of the signal reading in FIG. 4 (1/2 thinning). When considering the number of signal readout lines in each field with respect to the total number of lines, 1/4 thinning is performed. Actually, the supply of the transfer gate pulse is different from the sixth read processing. In the first field, transfer gate pulses TG are applied to the vertical transfer electrodes E1a and E1b. _1a , TG _1b Vertical drive signal φV including _1a , φV _1b May be applied. Similar to the sixth read process, in the second field, the transfer gate pulse TG is applied to the vertical transfer electrode E7. ₇ May be applied.
[0108]
Since the sixth and seventh readout processes can only obtain GB or RG signals by using only the signals of each field because of the Bayer arrangement, the signal processing is performed so as to obtain the three primary colors RGB in the subsequent stage when performing color display. Good.
[0109]
Next, an eighth readout process in signal readout from the imaging unit 104 will be described. 35 to 38 are used for the description. As shown in FIG. 35, the signal charge is read from two lines out of the total number of 16 lines. Therefore, in this reading process, only 1/8 of the lines are read out during one field period. This process Is called 1/8 decimation. In the Bayer array, in consideration of the spatial balance when reading the GB line and the RG line one by one in 16 lines, that is, the point of resolution, the signal charge is calculated from the connection relationship of the signal lines of the imaging unit 104 described above. The positional relationship for reading is the line shown in FIG. Vertical drive signal φV supplied only to vertical drive electrodes E3a and E1a _3a , φV _1a The transfer gate pulse TG _3a , TG _1a Is included. Transfer gate pulse TG for each field _3a , TG _1a FIG. 37 shows that is supplied to the driver unit 122. Furthermore, the timing chart of FIG. 38 shows the transfer gate pulse TG near time t41. _3a , TG _1a Is supplied at a predetermined timing in synchronization with the vertical synchronizing signal VD and the horizontal synchronizing signal HD. By connecting the vertical drive electrodes in consideration of independently reading out each desired line in the Bayer array, 1/8 decimation in the vertical direction, which was difficult with conventional imaging, can be easily performed. .
[0110]
In this way, the imaging unit 104 is configured in consideration of the connection relationship of the 10-electrode signal lines, and is driven in eight phases, so that the field readout is decimated 1/2, 1/4, and 1/8 in the vertical direction. All will be realized. Of course, it is needless to say that all-pixel readout can also be realized. These readouts can be selected, and readout processing is performed according to the selection.
[0111]
Next, a description will be given of a second embodiment of the digital still camera using 12 electrodes in the connection relation of the image pickup unit 104 described above. Since the digital still camera 10 is basically the same as the configuration of the first embodiment, the same reference numerals are given and the description thereof is omitted. In this configuration, the imaging unit 104 has a vertical drive signal φV _n The connections between the vertical transfer paths 104c to which the signals are supplied are different. In the vertical transfer path 104c, the vertical drive signal φV _n A vertical drive electrode is provided. In the present embodiment, as shown in FIG. 2, reference numerals are not assigned based on the electrodes of the vertical transfer path 104c, but individual CCDs in the vertical transfer paths, that is, vertical transfer elements are assigned reference numerals to establish the connection relationship. To express. The imaging unit 104 forms two CCDs per pixel as a set in the vertical direction so as to separate individual signal charges so that the read signal charges are not mixed with the signal charges of adjacent pixels. The imaging unit 104 in FIG. 39 has a signal line connection relationship that repeats one cycle with 32 CCDs in order to read out signal charges with connection described later.
[0112]
The connection relationship of the signal lines will be described. Here, the first line in FIG. 39 is the first row, and n is an integer. The variable n corresponds to the variable j used in each claim. Vertical drive signal φV _1a Only one vertical transfer element V1a is provided for 32 leading lines. That is, the vertical transfer element V1a is provided and connected every 1 + 32n rows. Vertical drive signal φV ₂ Is provided and connected every 2 + 8n rows. Vertical drive signal φV _3a Also, only one vertical transfer element V3a is provided in this cycle. That is, the vertical transfer elements V3a are provided every 3 + 32n rows and connect vertical transfer elements having the same sign.
[0113]
Vertical drive signal φV _Four ~ ΦV ₈ Are provided for every 4 + 8n, 5 + 8n, 6 + 8n, 7 + 8n, and 8 + 8n rows, respectively. And it connects so that the same vertical drive signal may be supplied to the same vertical transfer elements. In addition to this, the vertical drive signal φV _1b , φV _3b The vertical transfer elements V1b and V3b to be supplied are provided for every 9 + 16n and 11 + 16n, respectively, to connect the same vertical transfer elements. In terms of lines, these relationships are 5 + 8n and 6 + 8n, respectively.
[0114]
And the vertical drive signal φV _1c , φV _3c The vertical transfer elements V1c and V3c to be supplied are 17 + 32n and 19 + 32n, respectively. That is, they are only one in 32 cycles. The vertical transfer elements V1c and V3c are provided near the center of the cycle. The signal line connection relationship can be prevented from becoming complicated because there are many repeated patterns as compared with the first embodiment.
[0115]
In this signal line connection relationship, the above-described so-called ¼ thinning is performed on the image pickup unit 104 for each field to perform interlaced driving for reading signal charges (see FIG. 40). As shown in FIG. 40, four lines are taken as a set, and this set of four lines is read during the four field period shown in FIGS. 40 (A) to (D). In order to realize this signal charge readout, signal readout from the pixel is divided for each field. The signal that defines this read process is the transfer gate pulse TG _n It is.
[0116]
It can be seen from the timing chart of FIG. 41 that each transfer gate pulse is supplied in synchronization with the vertical synchronization signal VD. In this embodiment, the number is increased by two electrodes compared to the previous embodiment. Adding this increase, the transfer gate pulse becomes TG _1a ~ TG _1c , TG _3a ~ TG _3c become. Transfer gate pulse TG in synchronization with the first vertical synchronization signal VD ₇ Supply. When the next vertical synchronization signal VD is supplied, the transfer gate pulse TG _Five Supply. When the third vertical synchronizing signal VD is supplied, the transfer gate pulse TG _1a ~ TG _1c Are supplied at the same timing. As indicated by the subscripts of the reference numerals of these signals, the supply destination only differs depending on the connection relationship of the signal lines. Correspondence between the subscript of the signal and the reference code of the vertical transfer element of the supply destination But The same reference numerals are used for easy understanding. Finally, when the fourth vertical synchronizing signal VD is supplied, the transfer gate pulse TG _3a ~ TG _3c Are supplying three at the same time.
[0117]
Among these, the timing of the first field is given. In this field, as shown in Figure 42, the transfer gate pulse TG ₇ Only supplied. When this supply is expanded in time to the timing of the horizontal synchronization signal HD, it can be seen that the level is set to L during a predetermined period in the vicinity of the center of the horizontal synchronization signal HD in synchronization with the horizontal synchronization signal HD. Refer to FIG. 3 again. Transfer gate pulse TG to driver section 122 _n And vertical drive timing signal V _n Are simultaneously supplied at the level L, the driver unit 122 generates the vertical drive signal φV. _n Set to level H and output. Level H vertical drive signal φV _n The signal charge accumulated only in the vertical transfer element to which is supplied can be taken out. The extracted signal charge is an 8-phase vertical drive timing signal V shown in FIG. _n Are transferred sequentially at level M.
[0118]
This relationship is the same at the timing of the second field. Transfer gate pulse TG in Fig. 44 _Five When the level L is supplied to the driver unit 122 in synchronization with the horizontal synchronizing signal HD, the vertical driving signal φV _Five To the imaging unit 104 to read out the signal charge accumulated in the light receiving element 104a. Transfer gate pulse TG in the third and fourth fields _n Are supplied in the timing relationship shown in FIGS. 45 (a) and 45 (b). By supplying a transfer gate pulse for signal readout at such timing, 1/4 interlace scanning can be performed from a desired position in the same manner as in the prior art even in such a connection.
[0119]
Next, a reading process for performing 1/2 thinning-out reading from the imaging unit 104 with the connection relation of the signal lines will be described. As shown in FIGS. 46 to 49, four lines are viewed as a group, and signal charges for two lines are read during a two-field period. That is, 1/2 decimation is performed. Since the Bayer array color filter CF is used, the GB line and the RG line or the RG line and the GB line are alternately read in this way. In the signal reading of FIG. 46, the latter process of alternately reading the RG line and the GB line is performed. This signal readout process is performed by transferring the transfer gate pulse TG to the driver unit 122 for each field. ₇ , TG _Five Supply.
[0120]
In addition to this signal line connection relationship, there is still another color drive relationship, that is, vertical drive that reads out signals while thinning out half so that all three primary colors RGB are aligned. For example, as shown in FIG. 48, three transfer gate pulses TG _1a , TG _1b , TG _1c At the same time and another transfer gate pulse TG ₇ (See FIG. 49). As is clear from FIGS. 48 (a) and 48 (b), the signals read in this case are adjacent to each other. Although not shown, the transfer gate pulse TG _Five And transfer gate pulse TG _3a , TG _3b , TG _3c Are alternately supplied for each field, and so-called 1/2 thinning is performed on the entire screen by performing so-called 1/4 thinning twice in the field.
[0121]
Next, in the signal line connection relationship of FIG. 39, further signal readout thinning processing is performed by field readout. This relationship is summarized in FIG. Since all colors G are included in each row in the Bayer array, the colors R and B are focused on. The focused color is indicated in the vertical direction, that is, in the column direction, and a reference numeral of the vertical transfer element supplied to the vertical transfer path 104c. Among them, symbols R and B indicating colors to be read are described at positions where signals are read by applying transfer gate pulses. Symbols A to K described at the top represent supply patterns. Hereinafter, the sequential operation will be described.
[0122]
As can be seen from FIG. 50, pattern A is a processing method for reading signal charges from the vertical transfer elements V1a, V1c, and V3b. The vertical transfer elements V1a and V1c both read the color B, and the vertical transfer element V3b reads the color R. The readout interval between the same colors is every 8 rows. When the signal charge is read out with this signal line connection, the spatial spacing between the colors R and B can be two lines. Actually, such signal readout is shown in FIG. In performing signal readout in this relationship, the driver unit 122 has a transfer gate pulse TG synchronized with the vertical early signal VD. _1a , TG _1c , TG _3b (See FIG. 52). Thus, the vertical drive signals φV1a, φV1c, and φV3b supplied from the driver unit 122 are applied to perform desired 1/4 thinning.
[0123]
Pattern B shown in FIG. 50 is a processing method of reading signal charges from the vertical transfer elements V1a, V1c, V3a and V3c. The vertical transfer elements V1a and V1c read the color B in the same manner as the pattern A, and the vertical transfer elements V3a and V3c read the color R. The readout interval between the same colors is every 7 rows. When variable i = 2, the read interval is 2 ^{i + 1} -1 = 2 ^Three This is because there is a relationship of -1 = 7. As a result, when variable i = 2, 1/4 decimation (1/2 ² Thinning). When the signal charge is read out by the connection relationship of the signal lines, the signal charge can be read out without leaving a spatial interval between the colors R and B. Actually, such signal readout is shown in FIG. In performing signal readout in this relationship, the driver unit 122 has a transfer gate pulse TG synchronized with the vertical early signal VD. _1a , TG _1c , TG _3a , TG _3c (See FIG. 54). Thus, the vertical drive signals φV1a, φV1c, φV3a, and φV3b supplied from the driver unit 122 are applied to perform desired 1/4 thinning.
[0124]
Further, pattern C in FIG. 50 is a processing method for reading signal charges from the vertical transfer elements V1b and V3b. The vertical transfer element V1b reads the color B similarly to the pattern A, and the vertical transfer element V3b reads the color R. The readout interval between the same colors is every 7 rows. When the signal charge is read out with this signal line connection relationship, the pattern obtained is the same pattern as when the signal B is read out by setting the read start position of pattern B 4 lines below. Actually, such signal readout is shown in FIG. When performing signal readout in this relationship, the driver unit 122 has a transfer gate pulse TG synchronized with the vertical early signal VD. _1b , TG _3b (See FIG. 56). Accordingly, the vertical drive signals φV1b and φV3b supplied from the driver unit 122 are applied to perform desired 1/4 thinning. Thus, patterns A to C read the same color every 7 rows.
[0125]
A signal readout process in which the signal charge readout of the pattern B (FIG. 57 (a)) and the pattern C (FIG. 57 (b)) is combined is performed alternately for each field. In this signal readout, signal charges are read out by two adjacent lines of each pattern, and in the next field, interlace scanning is performed to read out signal charges from two lines located in the middle of the previous field (that is, 2: 1). Interlaced scanning). This relationship is clear from FIG. Reading of each field is 1/4 thinning out as described above. Although the number of lines to be read is half that in the case of 4-field interlace scanning, the read time can be shortened to half. Such scanning can also be performed by the connection relationship of signal lines corresponding to these patterns B and C.
[0126]
Pattern D in FIG. 50 is a processing method for reading signal charges from the vertical transfer elements V1a and V3a. The vertical transfer element V1a reads the color B, and the vertical transfer element V3a reads the color R. The readout interval between the same colors is every 15 rows. When variable i = 3, the read interval is 2 ^{i + 1} -1 = 2 ^Four This is because there is a relationship of -1 = 15. As a result, when the variable i = 3, so-called 1/8 decimation (1/2) ^Three Thinning). When signal charges are read out with the connection relation of the signal lines, the color RB is obtained from adjacent rows. In this readout, since 2 lines are read out of 16 lines in one field period, only 1/8 of all pixels are read out. This thinning is performed by 1/8 thinning which cannot be performed by the conventional imaging unit 104. As shown in FIG. 60, this 1/8 decimation is performed by the driver unit 122 in the transfer gate pulse TG in synchronization with the vertical early signal VD. _1a , And TG _3a Supply. Thus, the vertical drive signals φV1a and φV3a supplied from the driver unit 122 are applied to perform 1/8 decimation.
[0127]
This thinning is not limited to the pattern D, but can also be performed by reading signal charges from the vertical transfer elements V1c and V3c (see pattern E in FIG. 50, FIGS. 61 and 62). In this case, as shown in FIG. 61, the driver unit 122 has a transfer gate pulse TG synchronized with the vertical early signal VD so that the same color is read every 15 rows. _1c , And TG _3c (See FIG. 62). Thus, the vertical drive signals φV1c and φV3c supplied from the driver unit 122 are applied to perform 1/8 decimation.
[0128]
Further, 1/8 decimation can also be performed by the pattern F in FIG. The lines read out corresponding to the transfer gate pulse supply positions in FIG. 50 are as shown in FIG. To read the signal at this position, the transfer gate pulse TG in FIG. _1a , And TG _3c Is supplied to the driver section 122. These signals and vertical drive timing signal V _n Drive signal φV generated by the supply of _n Of these, vertical drive signal φV _1a , φV _3c Includes a signal that enables signal charge readout. As a result, 1/8 decimation is performed.
[0129]
By combining this signal line connection relationship, that is, the pattern D and the pattern E, the 1/8 decimation readout 2: 1 interlace scanning can be performed as described above. As shown in FIG. 65, the signal readout from the imaging unit 104 is transferred by scanning the pattern D in the first field of (a) and transferring the pattern E in the second field of (b). In order to perform this operation, the driver unit 122 includes a transfer gate pulse TG shown in FIG. _1a , TG _3a And transfer gate pulse TG _1c , TG _3c (See FIG. 66). The driver unit 122 generates a vertical drive signal φV including these transgate pulses. _1a , φV _3a And vertical drive signal φV _1c , φV _3c Are alternately supplied at the timing synchronized with the vertical synchronizing signal for each field.
[0130]
Vertical drive signal φV supplied in this way _n By performing vertical drive in consideration of the connection relationship between the signal line and the signal line, not only normal reading and 1/2, 1/4 thinning, but also 1/8 thinning can be performed.
[0131]
Next, first to third modifications of the second embodiment will be described. In the second embodiment described above, 12 electrodes are used according to the type of vertical drive signal supplied to the imaging unit 104. This means that the driver unit 122 requires many V drivers for generating vertical drive signals. By the way, the digital still camera 10 may be given priority to the demand for downsizing the apparatus. In this case, the driver unit 122 of the digital still camera 10 should be made small. However, the circuit mounting area of the V driver is large and the above-mentioned requirements cannot be satisfied. Therefore, a configuration for smoothly thinning out signal readout while limiting the number of use of the V driver will be described in a first modification example with reference to FIG.
[0132]
The imaging unit 104 of the first modification example makes the vertical drive electrode V1a and the electrode V1c, and the vertical drive electrode V3a and the electrode V3c in common connection in addition to the signal line connection relationship of the second embodiment described above. This connection may be made externally. With this connection, the vertical drive signals to be supplied can be suppressed from 12 types to 10 types. The same vertical drive signal is supplied to the commonly connected electrodes. Therefore, the vertical drive signal φV supplied to the vertical drive electrodes V1c, V3c _1c , φV _3c Disappears. The uniqueness of the vertical drive electrodes V1c and V3c is lost, and it becomes impossible to supply vertical drive signals to these electrodes individually. As a result, 1/8 decimation vertical drive cannot be performed. Actually, in this connection, patterns G, H, and I in FIG. 50 are driven. These three patterns correspond to the patterns A, B, and C in FIG. In other words, this connection limits the thinning process for each field to 1/4 thinning. As a result, the digital still camera 10 can be easily downsized and processed up to 1/4 thinning.
[0133]
Next, a second modification will be described. In this modification, in addition to the signal line connection relationship of the second embodiment described above, the vertical drive electrode V1b and the electrode V1c and the vertical drive electrode V3b and the electrode V3c are connected in common as shown in FIG. Also in this case, the connection may be made externally. With this connection, the vertical drive signals to be supplied can be suppressed from 12 types to 10 types. With this connection, it can be seen that pattern J in FIG. 50 corresponds to pattern D in FIG. That is, the vertical drive signal φV supplied to the vertical drive electrodes V1a and V3a _1a , φV _3a Only transfer gate pulses are included. Therefore, this connection is a limited signal readout that only supports 1/8 decimation. By connecting in this way, the digital still camera 10 can easily perform downsizing and 1/8 thinning processing.
[0134]
Finally, a third modification of the imaging unit 104 will be described. In this modification, in addition to the signal line connection relationship of the second embodiment described above, the vertical drive electrode V1b and the electrode V1c and the vertical drive electrode V3a and the electrode V3b are connected in common as shown in FIG. Also in this case, the connection may be made externally. With this connection, the vertical drive signals to be supplied can be suppressed from 12 types to 10 types. However, the transfer gate pulse is supplied to the vertical drive signal supplied independently to one electrode, instead of supplying the transfer gate pulse to the vertical drive signal for reading the signal charge through the common connection as in the modified examples so far. . With this connection, it can be seen that the pattern K in FIG. 50 corresponds to the pattern F in FIG. That is, the vertical drive signal φV supplied to the vertical drive electrodes V1a and V3c _1a , φV _3c Only include the transfer gate pulse. Therefore, this connection is a limited signal readout that only supports 1/8 decimation. By connecting in this way, the digital still camera 10 can easily perform downsizing and 1/8 thinning processing. However, since the positional relationship of the signals to be read out is far away, the image obtained by this can have a much higher image quality than the images obtained by the signal reading that have been described so far. Not that.
[0135]
By configuring and driving as described above, in addition to the 1/2 and 1/4 thinned-out images obtained in the conventional configuration, the new signal charge thinning-out readout that could not be achieved in the conventional structure is 1 / 8 Thinning can be realized. As a result, the digital still camera, for example, captures high-quality images even when the imaging unit is configured with a high number of pixels of millions or more, and reads out signal charges by thinning out in the vertical direction in a desired mode. The imaging cycle and refresh rate can be maintained at the previous time. Therefore, the other circuit can use the conventional configuration as it is, and contributes to the efficiency of the design.
[0136]
【The invention's effect】
As described above, according to the solid-state imaging device of the present invention, the transfer gates included in the same group of the first transfer gate group to the sixth transfer gate group are connected in common through the gate pulse applying signal line. By applying each gate pulse to the transfer gate and reading the signal charge from the desired light receiving element, in addition to the 1/2, 1/4 thinned image obtained with the conventional configuration, it can be done with the conventional structure It is possible to realize 1/8 decimation of new signal charge decimation. As a result, the digital still camera, for example, captures high-quality images even when the imaging unit is configured with a high number of pixels of millions or more, and reads out signal charges by thinning out in the vertical direction in a desired mode. The imaging cycle and refresh rate can be maintained at the previous time. Therefore, the other circuit can use the conventional configuration as it is, which contributes to the design efficiency.
[0137]
In addition, according to the signal reading method of the present invention, a gate pulse is applied to the first transfer gate group to the sixth transfer gate group to read out the signal, and the signal in the vertical direction is 1/2, 1 / 4 decimation can perform 1/8 decimation, which is one degree larger than the original. As a result, even if the number of pixels of the solid-state imaging device exceeds, for example, several million, the imaging cycle and refresh rate can be maintained at the previous time, and an image corresponding to the display or recording mode is obtained. be able to.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a digital still camera to which a solid-state imaging device of the present invention is applied.
2 is a schematic diagram of a first embodiment illustrating a connection relationship of wirings for supplying a vertical drive signal to the imaging unit in the main part of the imaging unit of FIG. 1;
3 is a timing chart showing a relationship between a fa-trans gate pulse and a vertical drive timing signal with respect to the vertical drive signal of FIG. 2;
4 is a diagram showing a relationship between a vertical transfer electrode in the connection of FIG. 2 and a vertical drive signal including a field gate pulse applied for each field (hereinafter simply referred to as a vertical drive signal).
5 is a timing chart showing a relationship between a vertical drive timing signal and a transfer gate pulse with respect to a vertical synchronization signal that realizes the relationship of FIG.
6 is a schematic diagram showing reading of the first field by the imaging unit as the main part of FIG. 2; FIG.
7 is a timing chart showing the relationship between the vertical drive timing signal and the transfer gate pulse in the first field with respect to the timing of the vertical synchronization signal that is enlarged in time when the relationship of FIG. 4 is realized.
8 is a timing chart showing the relationship between the vertical drive timing signal and the transfer gate pulse with respect to the timing of the horizontal synchronization signal displayed in an enlarged manner when realizing the relationship of FIG.
FIG. 9 is a schematic diagram illustrating reading of a second field by the imaging unit that is the main part of FIG. 2;
10 is a timing chart showing the relationship between the vertical drive timing signal and transfer gate pulse in the second field with respect to the timing of the vertical synchronization signal displayed in an enlarged manner when realizing the relationship of FIG.
11 is a timing chart showing the relationship between the vertical drive timing signal and transfer gate pulse in the first field with respect to the timing of the horizontal synchronization signal when realizing the relationship of FIG. 4; FIG.
12 is a diagram showing a relationship between a vertical transfer electrode in the connection of FIG. 2 and a vertical drive signal applied by two lines for each field. FIG.
13 is a timing chart showing a relationship between a vertical drive timing signal and a transfer gate pulse with respect to a vertical synchronization signal that realizes the relationship of FIG.
14 is a schematic diagram illustrating reading of the first field in FIG. 12 by the imaging unit as the main part of FIG. 2;
FIG. 15 is a timing chart showing the relationship between the vertical drive timing signal and transfer gate pulse in the first field with respect to the timing of the vertical synchronization signal displayed in a time enlarged manner when realizing the relationship of FIG. 12;
FIG. 16 is a timing chart showing the relationship between the vertical drive timing signal and the transfer gate pulse with respect to the timing of the horizontal synchronization signal that is enlarged in time when the relationship of FIG. 12 is realized.
17 is a schematic diagram illustrating reading of the second field in FIG. 12 by the imaging unit that is the main part of FIG. 2;
18 is a timing chart showing the relationship between the vertical drive timing signal and transfer gate pulse in the second field with respect to the timing of the vertical synchronization signal displayed in an enlarged manner when realizing the relationship of FIG.
FIG. 19 is a timing chart showing the relationship between the vertical drive timing signal and transfer gate pulse in the first field with respect to the timing of the horizontal synchronizing signal when realizing the relationship of FIG. 12;
20 is a diagram showing the relationship between the vertical transfer electrodes in the connection of FIG. 2 and the vertical drive signal applied to the same line (second field) by two lines for each field. FIG.
21 is a timing chart showing the relationship between the vertical drive timing signal and transfer gate pulse in each field with respect to the timing of the vertical synchronization signal when realizing the relationship of FIG.
22 is a diagram showing the relationship between the vertical transfer electrodes in the connection of FIG. 2 and the vertical drive signal applied to the same line (first field) by two lines for each field. FIG.
23 is a timing chart showing the relationship between the vertical drive timing signal and transfer gate pulse in each field with respect to the timing of the vertical synchronization signal when realizing the relationship of FIG.
24 is a diagram showing a relationship between a vertical transfer electrode in the connection of FIG. 2 and vertical drive signals applied to different one of four lines for each field. FIG.
25 is a schematic diagram showing readout of the first field in FIG. 24 by the imaging unit as the main part of FIG. 2;
FIG. 26 is a timing chart showing the relationship between the vertical drive timing signal and the transfer gate pulse in the first field with respect to the timing of the vertical synchronization signal displayed in an enlarged manner when realizing the relationship of FIG. 24;
27 is a schematic diagram showing readout of the second field in FIG. 24 by the imaging unit as the main part of FIG. 2;
FIG. 28 is a timing chart showing the relationship between the vertical drive timing signal and transfer gate pulse in the second field with respect to the timing of the vertical synchronization signal displayed in an enlarged manner when the relationship of FIG. 24 is realized.
29 is a schematic diagram showing readout of the third field in FIG. 24 by the imaging unit which is the main part of FIG. 2;
30 is a timing chart showing the relationship between the vertical drive timing signal and the transfer gate pulse in the third field with respect to the timing of the vertical synchronization signal displayed in an enlarged manner when the relationship of FIG. 24 is realized.
31 is a schematic diagram showing readout of the fourth field in FIG. 24 by the imaging unit as the main part of FIG. 2;
FIG. 32 is a timing chart showing the relationship between the vertical drive timing signal and transfer gate pulse in the fourth field with respect to the timing of the vertical synchronization signal that is enlarged in time when realizing the relationship of FIG. 24;
33 is a diagram showing a relationship between vertical transfer electrodes in the connection of FIG. 2 and vertical drive signals applied alternately to adjacent one of four lines for each field.
34 is a diagram showing the relationship between the vertical transfer electrodes in the connection of FIG. 2 and vertical drive signals applied alternately to different one lines located at the ends of the four lines for each field.
35 is a diagram showing a relationship between a vertical transfer electrode in the connection of FIG. 2 and vertical drive signals applied to two different lines in 16 lines for each field.
36 is a schematic diagram showing readout of the field of FIG. 35 by the imaging unit of the main part of FIG. 2;
FIG. 37 is a timing chart showing the relationship between the vertical drive timing signal and the transfer gate pulse with respect to the timing of the vertical synchronization signal when realizing the relationship of FIG.
FIG. 38 is a timing chart showing a relationship between a vertical drive timing signal and a transfer gate pulse with respect to timings of a vertical synchronization signal and a horizontal synchronization signal that are displayed in an enlarged manner when realizing the relationship of FIG.
FIG. 39 is a schematic diagram of a second embodiment illustrating a connection relationship of wirings for supplying a vertical drive signal to the imaging unit in the main part of the imaging unit of FIG. 1;
40 is a schematic diagram illustrating a main part of the imaging unit when signal charges are read in each field when the imaging unit of FIG. 39 is subjected to interlace scanning of 4 fields.
41 is a timing chart showing the relationship between the fa-trans gate pulse and the vertical drive timing signal with respect to the vertical drive signal of FIG. 39. FIG.
42 is a timing chart showing the relationship of the first field of the vertical drive timing signal and transfer gate pulse with respect to the vertical synchronization signal and horizontal synchronization signal in the connection of FIG. 39;
43 is a timing chart showing vertical drive timing signals and transfer gate pulses for driving the imaging section of FIGS. 2 and 39 in eight phases.
44 is a timing chart showing the timing relationship of the second field among the timings for the signals in FIG. 41. FIG.
45 is a timing chart showing the timing relationship between the third and fourth fields in the timing for each signal in FIG. 41. FIG.
46 is a schematic diagram illustrating a main part of the imaging unit when signal charge reading is performed by 2: 1 interlaced scanning of two fields in the imaging unit of FIG. 39. FIG.
47 is a timing chart showing a vertical drive timing signal and a transfer gate pulse supplied to the vertical synchronizing signal in the signal charge reading of FIG. 46. FIG.
48 is a schematic diagram illustrating a main part of the imaging unit in a readout example different from that in FIG. 46 when signal charge readout is performed by 2-field 2: 1 interlace scanning in the imaging unit of FIG. 39. FIG.
49 is a timing chart showing a vertical drive timing signal and a transfer gate pulse supplied to the vertical synchronization signal in the signal charge reading of FIG. 48. FIG.
FIG. 50 is a diagram summarizing signal charge read patterns in a list while also showing the relationship of colors read from the imaging units in the connection relationship of FIG. 39;
51 is a schematic diagram showing the main part of the imaging unit when signal charges are read out with pattern A in FIG. 50. FIG.
52 is a timing chart showing a vertical drive timing signal and a transfer gate pulse supplied for a vertical synchronizing signal in the signal charge reading of FIG. 51. FIG.
53 is a schematic diagram showing the main part of the imaging unit when reading out signal charges with the pattern B in FIG. 50. FIG.
54 is a timing chart showing a vertical drive timing signal and a transfer gate pulse supplied for a vertical synchronization signal in the signal charge reading of FIG. 53. FIG.
55 is a schematic diagram showing the main part of the imaging unit when reading out signal charges with the pattern C in FIG. 50. FIG.
56 is a timing chart showing a vertical drive timing signal and a transfer gate pulse supplied to the vertical synchronization signal in the signal charge reading of FIG. 55. FIG.
FIG. 57 is a schematic diagram illustrating a main part of the imaging unit when signal charges are read out by 2: 1 interlace scanning in which the patterns B and C of FIG. 50 are applied alternately for each field.
58 is a timing chart showing a vertical drive timing signal and a transfer gate pulse supplied for a vertical synchronization signal in the signal charge reading of FIG. 57. FIG.
FIG. 59 is a schematic diagram showing the main part of the imaging unit when signal charges are read out with the pattern D in FIG.
60 is a timing chart showing a vertical drive timing signal and a transfer gate pulse supplied for a vertical synchronizing signal in the signal charge reading of FIG. 59. FIG.
61 is a schematic diagram showing the main part of the imaging unit when signal charges are read out with the pattern E in FIG. 50. FIG.
62 is a timing chart showing a vertical drive timing signal and a transfer gate pulse supplied to a vertical synchronizing signal in the signal charge reading of FIG. 61. FIG.
FIG. 63 is a schematic diagram showing the main part of the imaging unit when signal charges are read out with the pattern F in FIG.
64 is a timing chart showing a vertical drive timing signal and a transfer gate pulse supplied to the vertical synchronization signal in the signal charge reading of FIG. 63. FIG.
FIG. 65 is a schematic diagram showing the main part of the imaging unit when signal charges are read out by 2: 1 interlace scanning in which the patterns E and F of FIG. 50 are applied alternately for each field.
66 is a timing chart showing a vertical drive timing signal and a transfer gate pulse supplied to the vertical synchronization signal in the signal charge reading of FIG. 65. FIG.
FIG. 67 is a schematic diagram showing the main part of the imaging unit when signal charges are read out in a common connection relationship between the vertical drive electrodes V1a and V1c and the vertical drive electrodes V3a and V3c in addition to the connection relationship of FIG. FIG.
FIG. 68 is a schematic diagram showing the main part of the imaging unit when reading out signal charges with the connection of the vertical drive electrodes V1b and V1c and the connection of the vertical drive electrodes V3b and V3c in a common connection relationship in addition to the connection relationship of FIG. FIG.
FIG. 69 shows the main part of the imaging unit when signal charges are read out in a common connection relationship between the vertical drive electrodes V1b and V1c and the vertical drive electrodes V3a and V3b in addition to the connection relationship of FIG. It is a schematic diagram.
[Explanation of symbols]
10 Digital still camera
12 System controller
10A imaging system
10B signal processing system
10C drive signal generator
10D signal output system
10E mode specification part
104 Imaging unit
106 AF adjustment section
120 Signal generator
122 Driver section
104a photo detector
104b transfer gate
104c Vertical transfer path
104d horizontal transfer path
104e output amplifier
E1a, E1b, E2, E3a, E3b, E4 ~ E8 Vertical drive electrode
V1a, V1b, V1c, V2, V3a, V3b, V3c, V4 to V8 Vertical transfer element

Claims (31)

A plurality of light receiving elements formed in a row direction and a column direction;
A vertical transfer path formed adjacent to the light receiving element in the row direction and formed with a vertical transfer electrode; and a signal charge accumulated between the light receiving element and the vertical transfer path and accumulated in the light receiving element In a solid-state imaging device provided with a transfer gate that reads out from the light receiving element to the vertical transfer path, the device includes:
Among the light receiving elements, a first transfer gate group disposed adjacent to the light receiving elements of the (N + 1) th row, the (N + 5) th row, and the (N + 13) th row (N is an integer);
A second transfer gate group disposed adjacent to the light receiving elements of the (N + 2) th row among the light receiving elements;
Among the light receiving elements, a third transfer gate group disposed adjacent to the light receiving elements of the (N + 3) th row, the (N + 7) th row, the (N + 11) th row, and the (N + 15) th row;
Among the light receiving elements, a fourth transfer gate group disposed adjacent to the light receiving elements of the (N + 4) th row, the (N + 8) th row, the (N + 12) th row, and the (N + 16) th row;
Among the light receiving elements, a fifth transfer gate group disposed adjacent to the light receiving elements of the (N + 6) th row, the (N + 10) th row, and the (N + 14) th row;
Among the light receiving elements, gate pulse applying signal lines for simultaneously applying gate pulses respectively supplied to the sixth transfer gate group disposed adjacent to the light receiving elements in the (N + 9) th row are connected. A solid-state image pickup device.   2. The apparatus according to claim 1, wherein, among the light receiving elements, the gate pulse to the transfer gate corresponding to the odd-numbered light receiving elements is different from the gate pulse to the transfer gate corresponding to the even-numbered light receiving elements. The solid-state imaging device, further comprising: a first gate pulse output unit applied in the step. 2. The apparatus according to claim 1, further comprising second gate pulse output means for simultaneously applying a gate pulse to the transfer gate,
In the odd field, the second gate pulse output means has two rows among the light receiving elements of the (m + 1) th row, the (m + 2) th row, the (m + 3) th row, and the (m + 4) th row (m is an integer). A gate pulse is simultaneously applied to a transfer gate formed adjacent to the light receiving element of the first and second transfer gates different from the transfer gate of the row applied in the odd field among the light receiving elements of the four consecutive rows in the even field. A solid-state imaging device, wherein a gate pulse is simultaneously applied to the two. 2. The apparatus of claim 1, further comprising third gate pulse output means for applying the transfer gate to a single row or simultaneously applying a gate pulse to a plurality of rows.
The solid-state imaging device, wherein the third gate pulse output means applies the gate pulse to the transfer gates of four rows of light receiving elements that are continuous in each field.   2. The device according to claim 1, wherein the device applies a fourth gate pulse to the transfer gates formed adjacent to the light receiving elements of the (N + 2) th row and the (N + 9) th row at the same time. A solid-state imaging device further comprising output means. A plurality of light receiving elements formed in a row direction and a column direction; a vertical transfer path formed adjacent to the light receiving elements in the row direction and having a vertical transfer electrode; and the light receiving elements and the vertical transfer path A signal readout that reads the signal charge obtained by the light receiving element using a solid-state imaging device provided with a transfer gate arranged between the light receiving element and transferring the signal charge accumulated in the light receiving element from the light receiving element to the vertical transfer path In a method, the method comprises:
Among the light receiving elements, a gate pulse is simultaneously applied to a first transfer gate group disposed adjacent to the light receiving elements in the (N + 1) th row, the (N + 5) th row, and the (N + 13) th row (N is an integer). And
A gate pulse is simultaneously applied to a second transfer gate group disposed adjacent to the light receiving elements in the (N + 2) th row among the light receiving elements,
Among the light receiving elements, gate pulses are simultaneously applied to a third transfer gate group disposed adjacent to the light receiving elements in the (N + 3) th row, the (N + 7) th row, the (N + 11) th row, and the (N + 15) th row. Apply
Among the light receiving elements, gate pulses are simultaneously applied to a fourth transfer gate group disposed adjacent to the light receiving elements in the (N + 4) th row, the (N + 8) th row, the (N + 12) th row, and the (N + 16) th row. Apply
Among the light receiving elements, a gate pulse is simultaneously applied to a fifth transfer gate group disposed adjacent to the light receiving elements in the N + 6th row, the N + 10th row, and the N + 14th row;
Among the light receiving elements, a sixth transfer gate group disposed adjacent to the light receiving elements in the (N + 9) th row is supplied in combination with a timing for simultaneously applying a gate pulse, and the obtained signal charges are sequentially read out. A signal reading method characterized by the above. A plurality of light receiving elements that convert incident light into electric signals by photoelectric conversion are arranged in the row direction and the column direction, and a vertical transfer path for transferring the signal charges read in the column direction is arranged adjacent to the plurality of light receiving elements. A transfer gate is formed between the vertical transfer path and each light receiving element to transfer the signal charge accumulated in each light receiving element to the vertical transfer path at a predetermined timing, and the signal charges are sequentially transferred in the horizontal direction. A vertical drive signal including a transfer gate pulse for operating the transfer gate at the predetermined timing is supplied from a drive signal generation unit that generates a vertical drive signal to be transferred toward the horizontal transfer path, and the signal charge is read and transferred. In a solid-state imaging device that has an imaging unit that sequentially transfers and outputs signal charges that have reached the horizontal transfer path to the output side, and that captures an object scene, the device includes:
Two vertical transfer elements for preventing mixing of the signal charges read when the signal charges accumulated in the light receiving elements are read in the vertical transfer path of the imaging means are formed on each light receiving element.
The drive signal generating means accumulates in the light receiving element at (2 ^{i + 1} −1) line intervals (variable i is a natural number) from the predetermined light receiving element having the same color as the first color as seen in the row direction. Vertical drive to read out the signal charge stored in the light receiving element at intervals of (2 ^{i + 1} −1) rows from the predetermined light receiving element of the same color as the characteristic second color when viewed in the row direction The signal is regularly generated, and further, vertical transfer is performed in eight phases, and 12 types of vertical drive signals are generated in consideration of the supply position of the transfer gate ,
A solid-state imaging device, wherein signal lines for supplying the generated vertical drive signals at the intervals are wired. 8. The apparatus according to claim 7, wherein the signal line includes a first vertical driving signal to a third vertical driving signal, a fifth vertical driving signal among twelve types of the vertical driving signals respectively supplied from the driving signal generation unit, The transfer gate pulse is supplied to the vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal at a predetermined timing, and the signal level indicates the input of the transfer gate pulse Vertical drive signal is supplied,
1 + 16j rows (variable j is an integer) of signal lines for supplying the first vertical drive signal;
6 + 8j rows of signal lines for supplying the sixth vertical drive signal;
Each of the 9 + 16j signal lines for supplying the third vertical drive signal is commonly connected. 8. The apparatus according to claim 7, wherein the signal line includes a first vertical driving signal to a third vertical driving signal, a fifth vertical driving signal among twelve types of the vertical driving signals respectively supplied from the driving signal generation unit, The transfer gate pulse is supplied to the vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal at a predetermined timing, and the signal level indicates the input of the transfer gate pulse Vertical drive signal is supplied,
1 + 16j rows (variable j is an integer) of signal lines for supplying the first vertical drive signal;
2 + 16j rows of signal lines for supplying the fifth vertical drive signal;
9 + 16j rows of signal lines for supplying the third vertical drive signal;
Each of the 10 + 16j rows of signal lines for supplying the seventh vertical drive signal is commonly connected. 8. The apparatus according to claim 7, wherein the signal line includes a first vertical driving signal to a third vertical driving signal, a fifth vertical driving signal among twelve types of the vertical driving signals respectively supplied from the driving signal generation unit, The transfer gate pulse is supplied to the vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal at a predetermined timing, and the signal level indicates the input of the transfer gate pulse Vertical drive signal is supplied,
5 + 8j rows (variable j is an integer) of signal lines for supplying the second vertical drive signal;
Each of the 6 + 8j rows of signal lines for supplying the sixth vertical drive signal is commonly connected. 8. The apparatus according to claim 7, wherein the signal line includes a first vertical driving signal to a third vertical driving signal, a fifth vertical driving signal among twelve types of the vertical driving signals respectively supplied from the driving signal generation unit, The transfer gate pulse is supplied to the vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal at a predetermined timing, and the signal level indicates the input of the transfer gate pulse Vertical drive signal is supplied,
1 + 16j rows (variable j is an integer) of signal lines for supplying the first vertical drive signal;
2 + 16j rows of signal lines for supplying the fifth vertical drive signal;
9 + 16j rows of signal lines for supplying the third vertical drive signal;
10 + 16j rows of signal lines for supplying the seventh vertical drive signal;
5 + 8j rows of signal lines for supplying the second vertical drive signal;
Each of the 6 + 8j row signal lines for supplying the sixth vertical drive signal is connected in common, and the first, third, fifth, and seventh vertical drive signals are connected to the second and the second vertical drive signals. A solid-state imaging device, wherein a sixth vertical drive signal is alternately supplied for each field. 8. The apparatus according to claim 7, wherein the signal line includes a first vertical driving signal to a third vertical driving signal, a fifth vertical driving signal among twelve types of the vertical driving signals respectively supplied from the driving signal generation unit, The transfer gate pulse is supplied to the vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal at a predetermined timing, and the signal level indicates the input of the transfer gate pulse Vertical drive signal is supplied,
1 + 16j rows (variable j is an integer) of signal lines for supplying the first vertical drive signal;
A solid-state imaging device, characterized in that each of the signal lines in 2 + 16j rows supplying the fifth vertical drive signal is connected in common. 8. The apparatus according to claim 7, wherein the signal line includes a first vertical driving signal to a third vertical driving signal, a fifth vertical driving signal among twelve types of the vertical driving signals respectively supplied from the driving signal generation unit, The transfer gate pulse is supplied to the vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal at a predetermined timing, and the signal level indicates the input of the transfer gate pulse Vertical drive signal is supplied,
9 + 16j rows (variable j is an integer) of signal lines for supplying the third vertical drive signal;
Each of the 10 + 16j rows of signal lines for supplying the seventh vertical drive signal is commonly connected. 8. The apparatus according to claim 7, wherein the signal line includes a first vertical driving signal to a third vertical driving signal, a fifth vertical driving signal among twelve types of the vertical driving signals respectively supplied from the driving signal generation unit, The transfer gate pulse is supplied to the vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal at a predetermined timing, and the signal level indicates the input of the transfer gate pulse Vertical drive signal is supplied,
1 + 16j rows (variable j is an integer) of signal lines for supplying the first vertical drive signal;
Each of the 10 + 16j rows of signal lines for supplying the seventh vertical drive signal is commonly connected. 8. The apparatus according to claim 7, wherein the signal line includes a first vertical driving signal to a third vertical driving signal, a fifth vertical driving signal among twelve types of the vertical driving signals respectively supplied from the driving signal generation unit, The transfer gate pulse is supplied to the vertical drive signal through the seventh vertical drive signal, the ninth vertical drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal at a predetermined timing, and the signal level indicates the input of the transfer gate pulse Vertical drive signal is supplied,
1 + 16j rows (variable j is an integer) of signal lines for supplying the first vertical drive signal;
2 + 16j rows of signal lines for supplying the fifth vertical drive signal;
9 + 16j rows of signal lines for supplying the third vertical drive signal;
The signal lines of 10 + 16j rows that supply the seventh vertical drive signal are connected in common, and the first and fifth vertical drive signals and the third and seventh vertical drives are connected. A solid-state imaging device, wherein a signal is supplied alternately for each field. The apparatus according to any one of claims 8 to 10, wherein the signal line, the first signal line and the third vertical 1 + 16j line for supplying a vertical drive signal (the variable j is an integer) Connect 9 + 16j signal lines that supply drive signals in common,
A solid-state imaging device, wherein the 2 + 16j row signal lines supplying the fifth vertical drive signal and the 10 + 16j row signal lines supplying the seventh vertical drive signal are connected in common. 13. The apparatus according to claim 12 , wherein the signal lines supply 2 + 16j rows (variable j is an integer) of the second vertical drive signal and the third vertical drive signal. Connect 16j signal lines in common,
6. A solid-state imaging device characterized in that 6 + 16j rows of signal lines for supplying the sixth vertical drive signal and 10 + 16j rows of signal lines for supplying the seventh vertical drive signal are connected in common. 15. The apparatus according to claim 14 , wherein the signal line supplies a signal line of 5 + 8j rows (the variable j is an integer) that supplies the second vertical drive signal and the third vertical drive signal that supplies the third vertical drive signal. Connect 16j signal lines in common,
A solid-state imaging device characterized in that 2 + 16j rows of signal lines for supplying the fifth vertical drive signal and 6 + 8j rows of signal lines for supplying the sixth vertical drive signal are connected in common. 8. The apparatus according to claim 7 , wherein the drive signal generating means is a minimum of 2− ⁱ when the variable i is 1 or more, and includes a sum of increments to be driven separately from the number of phases to be driven. 2. A solid-state imaging device characterized in that a vertical drive signal is supplied as a set of 2 ^{+ 1} . A plurality of light receiving elements that convert incident light into electrical signals by photoelectric conversion are arranged in the row direction and the column direction, and a vertical transfer path for transferring the signal charges read in the column direction is arranged adjacent to the plurality of light receiving elements. A transfer gate is formed between the vertical transfer path and each light receiving element to transfer the signal charges accumulated in each light receiving element to the vertical transfer path at a predetermined timing, and the signal charges are sequentially transferred in the horizontal direction. A vertical drive signal including a transfer gate pulse that operates the transfer gate at the predetermined timing is supplied from a drive signal generation unit that generates a vertical drive signal to be transferred toward the horizontal transfer path, and the signal charge is read and transferred. In the signal readout method of preparing an imaging means for sequentially transferring and outputting the signal charges reaching the horizontal transfer path to the output side, and reading out the signal charges obtained by imaging the object scene from the imaging means, Method,
Two vertical transfer elements for preventing mixing of the signal charges read when the signal charges accumulated in the light receiving elements are read in the vertical transfer path of the imaging means are formed on each light receiving element.
The vertical drive signal is a vertical transfer signal having eight phases, and 12 types are generated in consideration of the supply position of the transfer gate ,
The (2 ^{i + 1} −1) line spacing (i is a natural number) from the predetermined light receiving element of the same color as the first color that is characteristic in the row direction, and the second color that is characteristic in the row direction Based on a predetermined light receiving element of the same color as the image pickup means wired with a signal line for supplying a vertical drive signal indicating the input of the transfer gate pulse at (2 ^{i + 1} −1) row intervals,
Reading out the accumulated signal charge by regularly applying the vertical drive signals corresponding to the first color and the second color at (2 ^{i + 1} −1) row intervals through the signal line. A characteristic signal readout method. 21. The method according to claim 20 , wherein among the 12 types of the vertical drive signals, a first vertical drive signal through a third vertical drive signal, a fifth vertical drive signal through a seventh vertical drive signal, a ninth vertical drive signal, Supply the transfer gate pulse at a predetermined timing to the vertical drive signal and the eleventh vertical drive signal, and set the signal level to indicate the input of the transfer gate pulse,
The first vertical drive signal in the signal line 1 + 16j rows (the variable j is an integer);
The sixth vertical drive signal in the signal line 6 + 8j rows;
A signal reading method, wherein the third vertical drive signal is simultaneously supplied to the signal lines 9 + 16j for each field. 21. The method according to claim 20 , wherein among the 12 types of the vertical drive signals, a first vertical drive signal through a third vertical drive signal, a fifth vertical drive signal through a seventh vertical drive signal, a ninth vertical drive signal, Supply the transfer gate pulse at a predetermined timing to the vertical drive signal and the eleventh vertical drive signal, and set the signal level to indicate the input of the transfer gate pulse,
The first vertical drive signal in the signal line 1 + 16j rows (the variable j is an integer);
The fifth vertical drive signal in the signal line 2 + 16j rows;
The third vertical drive signal in the signal line 9 + 16j rows;
A signal reading method, wherein the seventh vertical drive signal is simultaneously supplied to the signal lines 10 + 16j for each field. 21. The method according to claim 20 , wherein among the 12 types of the vertical drive signals, a first vertical drive signal through a third vertical drive signal, a fifth vertical drive signal through a seventh vertical drive signal, a ninth vertical drive signal, Supply the transfer gate pulse at a predetermined timing to the vertical drive signal and the eleventh vertical drive signal, and set the signal level to indicate the input of the transfer gate pulse,
The second vertical drive signal in the signal line 5 + 8j rows (the variable j is an integer);
A signal reading method, wherein the sixth vertical drive signal is simultaneously supplied to the signal lines 6 + 8j for each field. 21. The method according to claim 20 , wherein the signal line includes a first vertical driving signal through a third vertical driving signal, a fifth vertical driving signal through a seventh vertical driving signal among the 12 types of vertical driving signals. Supplying the transfer gate pulse at a predetermined timing to the drive signal, the ninth vertical drive signal, and the eleventh vertical drive signal, and setting the signal level to indicate the input of the transfer gate pulse;
The first vertical drive signal in the signal line 1 + 16j rows (the variable j is an integer);
The fifth vertical drive signal in the signal line 2 + 16j rows;
The third vertical drive signal in the signal line 9 + 16j rows;
The seventh vertical drive signal in the signal line 10 + 16j rows;
The second vertical drive signal in the signal line 5 + 8j rows;
The sixth vertical drive signal is supplied to each of the signal lines 6 + 8j, and the vertical drive signals are the first, third, fifth, and seventh vertical drive signals and the A signal reading method, wherein the second and sixth vertical drive signals are alternately supplied for each field. 21. The method according to claim 20 , wherein among the 12 types of the vertical drive signals, a first vertical drive signal through a third vertical drive signal, a fifth vertical drive signal through a seventh vertical drive signal, a ninth vertical drive signal, Supply the transfer gate pulse at a predetermined timing to the vertical drive signal and the eleventh vertical drive signal, and set the signal level to indicate the input of the transfer gate pulse,
The first vertical drive signal in the signal line 1 + 16j rows (the variable j is an integer);
A signal reading method, wherein the fifth vertical drive signal is simultaneously supplied to the signal lines 2 + 16j for each field. 21. The method according to claim 20 , wherein among the 12 types of the vertical drive signals, a first vertical drive signal through a third vertical drive signal, a fifth vertical drive signal through a seventh vertical drive signal, a ninth vertical drive signal, Supply the transfer gate pulse at a predetermined timing to the vertical drive signal and the eleventh vertical drive signal, and set the signal level to indicate the input of the transfer gate pulse,
The third vertical drive signal in the signal line 9 + 16j rows (the variable j is an integer);
A signal reading method, wherein the seventh vertical drive signal is simultaneously supplied to the signal lines 10 + 16j for each field. 21. The method according to claim 20 , wherein among the 12 types of the vertical drive signals, a first vertical drive signal through a third vertical drive signal, a fifth vertical drive signal through a seventh vertical drive signal, a ninth vertical drive signal, Supply the transfer gate pulse at a predetermined timing to the vertical drive signal and the eleventh vertical drive signal, and set the signal level to indicate the input of the transfer gate pulse,
The first vertical drive signal in the signal line 1 + 16j rows (the variable j is an integer);
A signal reading method, wherein the seventh vertical drive signal is simultaneously supplied to the signal lines 10 + 16j for each field. 21. The method according to claim 20 , wherein among the 12 types of the vertical drive signals, a first vertical drive signal through a third vertical drive signal, a fifth vertical drive signal through a seventh vertical drive signal, a ninth vertical drive signal, Supply the transfer gate pulse at a predetermined timing to the vertical drive signal and the eleventh vertical drive signal, and set the signal level to indicate the input of the transfer gate pulse,
The first vertical drive signal in the signal line 1 + 16j rows (the variable j is an integer);
The fifth vertical drive signal in the signal line 2 + 16j rows;
The third vertical drive signal in the signal line 9 + 16j rows;
The seventh vertical drive signals are supplied to the signal lines 10 + 16j, respectively, and the vertical signals are the first and fifth vertical drive signals and the third and seventh vertical drive signals. Is alternately supplied for each field. A method according to any one of claims 21 to 23, wherein the first vertical drive signal and the third of said signal lines 1 + 16j line and a vertical drive signal is regarded as the same vertical drive signal (the variable j Is an integer) and the signal line 9 + 16j row,
The fifth vertical drive signal and the seventh vertical drive signal are regarded as the same vertical drive signal and are supplied to the signal line 2 + 16j and the signal line 10 + 16j. A characteristic signal readout method. 26. The method according to claim 25 , wherein the fifth vertical drive signal and the third vertical drive signal are regarded as the same vertical drive signal, and the signal line 2 + 16j rows (the variable j is an integer) and the signal line To 9 + 16j lines and
The sixth vertical drive signal and the seventh vertical drive signal are regarded as the same vertical synchronization signal and supplied to the signal line 6 + 16j and the signal line 10 + 16j. Method. 28. The method according to claim 27 , wherein the second vertical drive signal and the third vertical drive signal are regarded as the same vertical drive signal, and the signal line 5 + 8j rows (the variable j is an integer) and the signal line To 9 + 16j lines and
A signal reading method in which the fifth vertical drive signal and the sixth vertical drive signal are regarded as the same vertical drive signal and are supplied to the signal lines 2 + 16j and the signal lines 6 + 8j.

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