JP3059921B2 - Imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus for taking image information into a computer device.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing a configuration of an image pickup apparatus using a frame transfer type CCD solid-state image pickup device.
FIG. 9 is a timing chart for explaining the operation. CC
The D solid-state imaging device 1 includes a light receiving unit 1i, a storage unit 1s, a horizontal transfer unit 1h, and an output unit 1f. Light receiving unit 1i
Consists of a plurality of shift registers that are arranged in parallel in the vertical direction and each bit of these shift registers forms a plurality of light receiving pixels, and information charges generated in each light receiving pixel corresponding to a subject image. To accumulate. Storage unit 1
s is composed of a plurality of shift registers continuous with each shift register of the imaging unit 1i. The number of bits of each shift register is set according to the number of bits of the shift register of the imaging unit 1i, and 1 is transferred from the imaging unit 1i. Information charges for the screen are temporarily stored. The horizontal transfer unit 1h is composed of a single shift register in which each output of the plurality of shift registers of the storage unit 1s is connected to each bit, and transfers the information charges for one screen stored in the storage unit 1s in units of one row. And sequentially output. The output unit 1f includes an electrically independent capacitance and an amplifier for extracting a potential change of the capacitance. The output unit 1f receives the information charges output from the horizontal transfer unit 1h in a unit of one pixel and converts the information charges into a voltage value. It is output as an image signal Y0 (t).

The driver circuit 2 includes a vertical clock generator 2
v, accumulated clock generator 2s, horizontal clock generator 2h
And a substrate clock generator 2b. The vertical clock generator 2v synchronizes with the vertical synchronizing signal VD, and outputs a vertical clock φv for quickly transferring the information charges of the image pickup unit 1i to the storage unit 1s during the blanking period of the vertical scan.
To supply. The storage clock generation unit 2s captures the information charges transferred by the vertical clock φv into the storage unit 1s, synchronizes the captured information charges for one screen with the horizontal synchronization signal HD, and outputs the information charges within a blanking period of horizontal scanning. An accumulation clock φs to be transferred to the horizontal transfer unit 1h line by line is supplied to the accumulation unit 1s. The horizontal clock generation unit 2h supplies the horizontal transfer unit 1h with a horizontal clock φh that synchronizes with the horizontal synchronization signal HD and sequentially transfers information charges taken in every row to the output unit 1f in response to the accumulated clock φs. . In the horizontal clock generating unit 2h, a reset clock φr for discharging information charges of the capacity of the output unit 1f is generated in synchronization with the horizontal clock φh, and supplied to the output unit 1f.
Then, the discharge clock generation unit 2d supplies the discharge clock φd which is started in the middle of the vertical scanning period to the drain region of the CCD solid-state imaging device 1 which absorbs the charges overflowing in the imaging unit 1i. This discharge clock φd is
This is for discharging the information charges accumulated in the imaging unit 1i. The period L from the completion of the discharge operation of the information charges by the discharge clock φd to the start of the transfer operation of the information charges by the vertical clock φv is defined as L. This is the information charge accumulation time. By changing the timing of the substrate clock φd, it is possible to control the accumulation period of the information charges of the CCD solid-state imaging device 1, that is, the shutter speed. The method of discharging the information charge is disclosed in, for example, JP-A-3-22768 or JP-A-3-48586.

[0004] The timing control circuit 3 controls the vertical synchronizing signal V
A vertical timing signal VT synchronized with vertical scanning, an accumulation timing signal ST synchronized with vertical scanning and horizontal scanning, and a horizontal timing signal HT synchronized with horizontal scanning are generated based on D and the horizontal synchronization signal HD. It supplies to each part 2v, 2s, 2h. For example, when complying with the NTSC system, the frequency 14.32 MHz, which is four times the frequency of 3.58 MHz of the chrominance subcarrier used in the signal processing process.
Is divided into 1/910 to generate a horizontal synchronizing signal, and the horizontal synchronizing signal is divided into 2/525 to generate a vertical synchronizing signal. As a result, the vertical clock φv
Are synchronized with the vertical synchronization signal VD, and the accumulated clock φs and the horizontal clock φh are synchronized with the horizontal synchronization signal HD. Also,
The timing control circuit 3 generates a discharge timing signal DT based on the exposure information generated by the signal processing circuit 4 and supplies the discharge timing signal DT to the substrate clock generation unit 2d of the driver circuit 2. This discharge timing signal DT is output to the signal processing circuit 4
When the exposure information indicates that the CCD solid-state imaging device 1 is overexposed, the timing is delayed to shorten the information charge accumulation time L, and conversely, when the exposure information indicates that the exposure is insufficient, Is generated so that the accumulation time of the information charge is extended. Thus, feedback control is performed so that the exposure state of the CCD solid-state imaging device 1 is always appropriate.

[0005] The signal processing circuit 4 includes a CCD solid-state imaging device 1.
After receiving the image signal Y0 (t) output from, and performing processes such as sample hold and gamma correction, processes such as color separation, a color difference matrix, and balanced modulation are performed. Further, a synchronization signal for determining the timing of vertical scanning and horizontal scanning is added, and an image signal Y1 including a luminance signal, a chrominance signal and a synchronization signal is added.
Generate (t). At the same time, the image signal Y0 (t) is integrated in units of one screen to generate exposure information indicating the exposure state of the CCD solid-state imaging device 1, and supplies the exposure information to the timing control circuit 3. The image signal Y1 (t) obtained in this manner is reproduced by a display device such as a television monitor or recorded by a recording device such as a VTR.

It is well known that an image scanner for scanning and scanning an original document is used to capture image data into a computer device such as a personal computer or a word processor. It is also considered to use an imaging device such as a camera. When connecting an imaging device equipped with a CCD solid-state imaging device to a computer device, an expansion board called a video capture board is attached to the computer device, and the image signal output from the imaging device is converted into a signal suitable for the computer device. After that, the data is stored in a memory built in the computer device.

FIG. 10 is a block diagram showing a configuration of a video capture board. Video capture board 10
Comprises an A / D conversion circuit 11, a frame memory 12, a synchronous detection circuit 13, a timing control circuit 14, and an interface circuit 15. The A / D conversion circuit 11
Synchronizing with the output operation of the CD solid-state imaging device 1, image signals input from the imaging device are sequentially converted from analog to digital,
Image data corresponding to each light receiving pixel of the CCD solid-state imaging device 1 is generated. The frame memory 12 stores the image data generated by the A / D conversion circuit 11 for each screen. As the frame memory 12, a dual-port type RAM is used, and writing and reading of image data are performed simultaneously. The synchronous detection circuit 13 detects a synchronous signal from an image signal input from the imaging device, and generates a timing pulse according to each timing of vertical scanning and horizontal scanning. Based on the timing pulse supplied from the synchronous detection circuit 13, the timing control circuit 14
The operation of the D conversion circuit 11 is synchronized with the operation of the CCD solid-state imaging device 1, and the timing of writing and reading of image data in the frame memory 12 is controlled in response to the timing pulse and an instruction from the personal computer. That is, the image signal Y0 input from the imaging device in units of one screen
(t) is converted into image data for each pixel and stored in the frame memory 12 for each screen, and at the same time, the operation timing of each unit is synchronized so that the data can be read and transferred to the personal computer side. The interface circuit 15 receives the instruction from the timing control circuit 14 and
The image data stored in is read out and transferred to the personal computer. The interface circuit 15 sends an interrupt instruction output from the timing control circuit 14 to the personal computer, and supplies a read instruction sent from the personal computer to the timing control circuit 14. This allows
The image data stored in the frame memory 12 is transferred to the personal computer in one screen unit.

In a personal computer that captures image data from the video capture board 10, in response to a command input from a keyboard or a command according to an operation program, capture of image data, various calculations, access to a built-in memory, and display of a screen are performed. Display control and the like are repeated in a time-division process. For this reason, it is difficult to continuously capture image data at high speed, and it is not possible to follow the operation of the imaging device. For example, in the case of an image pickup apparatus that conforms to a general television system such as the NTSC system or the PAL system, the image data D (n) is output at about 10 MHz, whereas the image data D (n) is output at an ISA bus or the like used in a normal personal computer. The transmission speed is 1 MHz or less. Therefore, the video capture board 10 is configured to extract a part of the image data D (n) and transfer it to the personal computer.

[0009]

In the case of such an image pickup system, the cost of the image pickup apparatus itself is increased, and in addition, the video capture board 10 has a high-speed A / D converter.
Since the conversion circuit 11 and the large-capacity frame memory 12 are required, the overall system is expensive. Accordingly, an object of the present invention is to reduce the cost of an imaging system that captures image information in a computer device.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that an image of a subject is taken and image information is supplied to a computer device in units of one screen. A plurality of light receiving pixels are arranged in a matrix, and an information charge corresponding to an illuminated subject image is stored in each light receiving pixel; and an information charge stored in each light receiving pixel of the solid state imaging device is provided. 1
A driver circuit for sequentially transferring and outputting a row unit to obtain an image signal, a timing control circuit for setting a vertical scan start timing and a horizontal scan start timing of the driver circuit, and an analog signal process for the image signal. An analog signal processing circuit to be applied, an A / D conversion circuit for performing analog / digital conversion of the image signal subjected to the analog signal processing to generate image data, and a digital signal processing to perform digital signal processing on the image data A line memory circuit for sequentially storing the image data subjected to the digital signal processing in units of one row, and synchronizing the timing of writing data to the line memory circuit with the signal processing operation of the digital signal processing circuit, A memory control circuit for setting the read timing of the memory to a desired cycle; In further comprising an interface control circuit for sending the image data to be read from the memory circuit of the computer equipment to the bus line, the.

Thus, the frequency of the image data can be converted by using a line memory having a smaller capacity than the frame memory, and the image data can be sequentially taken into a computer device.

[0012]

FIG. 1 is a block diagram showing the configuration of an image pickup apparatus according to the present invention, and FIG. 2 is a timing chart for explaining its operation. The CCD solid-state imaging device 1 and the driver circuit 2 are the same as those in FIG.
The D solid-state imaging device 1 is configured to be pulse-driven to obtain an image signal Y0 (t). That is, it corresponds to the imaging unit 1i, the storage unit 1s, and the horizontal transfer unit 1h of the CCD solid-state imaging device 1,
A vertical clock generator 2v, an accumulated clock generator 2s, and a horizontal clock generator 2h are provided.
v, the accumulated clock φs, and the horizontal clock φh are supplied to each unit of the CCD solid-state imaging device 1. In addition, the discharge clock φd generated from the discharge clock
The shutter operation of the D solid-state imaging device 1 is enabled.

The first control unit 20 includes an analog signal processing circuit 21, an A / D conversion circuit 22, a timing control circuit 23,
An exposure control circuit 24 and a command register 25,
They are integrated on a common semiconductor substrate to form a one-chip configuration. The analog signal processing circuit 21 performs processing such as sample hold and AGC (automatic gain control) on the image signal Y0 (t) output from the CCD solid-state imaging device 1, and performs a waveform-shaped image signal Y1 (t). Is supplied to the A / D conversion circuit 22. For example, in the sample and hold process, an image signal Y0 (t) in which the reference potential and the signal potential are repeated in synchronization with the output operation of the CCD solid-state imaging device 1 is received, and the reference potential portion and the signal potential portion are sampled, respectively. Those potential differences are taken out. In the AGC process, a gain corresponding to the average level in one vertical scanning period is given to the image signal that has been subjected to the sample and hold process, and the average level in each vertical scanning period is controlled to be substantially uniform. The A / D conversion circuit 22, which receives the image signal Y1 (t), performs digital / analog conversion of the image signal output from the analog signal processing circuit 21 for each pixel in synchronization with the drive timing of the CCD solid-state imaging device 1. Generate image data D (n). The image data D (n) generated here is transferred to the personal computer.

The timing control circuit 23 generates a vertical timing signal VT based on a reference clock having a constant period, and supplies it to the driver circuit 2. The cycle V of the vertical timing signal VT determines the vertical scan cycle of the CCD solid-state imaging device 1, and is set by a command stored in the command register 25. The driver circuit 2 receiving the vertical timing signal VT activates the vertical clock φv at the timing of the vertical timing signal VT, and
The information charges of the imaging unit 1i of the solid-state imaging device 1 are transferred to the storage unit 1s. At this time, the timing control circuit 23
An interrupt signal IT indicating that the D solid-state imaging device 1 can output information charges for one screen is transmitted to the personal computer. Further, the timing control circuit 23 generates a horizontal timing signal HT in response to a line feed trigger HS supplied from the personal computer, and supplies the horizontal timing signal HT to the driver circuit 2.
The driver circuit 2 receiving the horizontal timing signal HT receives the horizontal clock φh at the timing of the horizontal timing signal HT.
To transfer the information charges in the storage section 1s of the CCD solid-state imaging device 1 to the horizontal transfer section 1h line by line. in this way,
The timing of the vertical scanning of the CCD solid-state imaging device 1 is determined by the timing control circuit 23, while the timing of the horizontal scanning is determined by the personal computer that receives the image data D (n). Further, the timing control circuit 23
Generates a discharge timing signal DT for determining the discharge timing of the charges of the CCD solid-state imaging device 1 based on the exposure data supplied from the exposure control circuit 23, and supplies the discharge timing signal DT to the driver circuit 2. In response to the discharge timing signal DT, the driver circuit 2 raises the discharge clock φd and lowers the vertical clock φv to discharge the information charges of the CCD solid-state imaging device 1. Therefore, the period L from the completion of the discharge of the information charges to the start of the reading is variably set so as to always be in an appropriate state according to the exposure state of the CCD solid-state imaging device 1. The iris control circuit 24 integrates the image data D (n) generated by the A / D conversion circuit 22 in units of one screen, and supplies the integrated value to the timing control circuit 23 as exposure data. And the command register 25
Various commands supplied from the personal computer are stored, and the operation cycle of the timing control circuit 23 and the processing conditions of the analog signal processing circuit 21 are determined. For example, a command for designating a vertical scanning period of the CCD solid-state imaging device 1, that is, a cycle for outputting one screen of image data D (n) is stored in accordance with the ability of the personal computer to capture image data D (n). And
The operation cycle of the timing control circuit 23 is determined.

The above-described CCD solid-state imaging device 1, driver circuit 2, and first control unit 20 are integrally formed as a camera unit. The second control unit 30 includes a digital signal processing circuit 31, a line memory 32, a memory control circuit 33, an interface control circuit 34, and a command register 35, and is integrated on a common semiconductor substrate separately from the first control unit 20. Thus, a one-chip configuration is obtained.

The digital signal processing circuit 31 performs processing such as color separation, matrix operation, and white balance adjustment on the image data D (n) generated by the first control unit 20.
As shown in FIG. 3, luminance data Y (n) and color difference data U (n) and V (n) are generated corresponding to each image data D (n).
For example, in the matrix operation, the luminance data Y (n) is generated by combining the separated color components, and each color component is subtracted or added to correspond to a predetermined color component (R, G, B). Color component data R
(n), G (n) and B (n) are generated. Then, color difference data U (n) and V (n) are generated from the difference between the color component data R (n) and B (n) and the luminance data Y (n). Note that the output of the digital signal processing circuit 31 is the color component data R (n), G
(n) and B (n) can be taken out as they are.

The line memory 32 stores luminance data Y (n) and color difference data U (n), V (n) (color component data R (n), G (n), B) generated by the digital signal processing circuit 31. (n)
May be stored for one line. This line memory 32
Is composed of, for example, a FIFO buffer, and the number of bits is set according to the data output format. Normally, the format of the data taken into the personal computer is a 16-bit configuration including 8-bit luminance data Y (n) and 8-bit color difference data U (n) and V (n) taken out in a time-division manner. Color component data R (n), G
(n), a 15-bit configuration consisting of B (n) and the like are common,
In these cases, the number of bits of the line memory 32 may be 16 bits. The memory control circuit 32 synchronizes the signal processing operation of the digital signal processing circuit 31, that is, the output operation of the CCD solid-state imaging device 1, with the luminance data Y (n) and the color difference data U (n), V The timing of writing (n) is controlled. At this time, by stopping the writing to the line memory 32 at regular intervals,
A part of the luminance data Y (n) and the color difference data U (n) and V (n) is thinned out to reduce the data amount. Generally, on the personal computer side, luminance data Y (n) and color difference data U (n),
Since only a part of V (n) is often required, the luminance data Y (n) and the chrominance data U (n) and V (n) at the time of writing to the line memory 32 correspond to the demand of the personal computer. If thinned out, efficient data transmission becomes possible.
For example, luminance data Y (n) and color difference data U (n), V (n)
Is reduced to ３, as shown in FIG. 3, the write enable signal WEy corresponding to the luminance data Y (n) is raised every two clocks, and the luminance data Y (n) is increased.
Is not written into the line memory 32. Then, the color difference data U (n), V
The write enable signals WEu and WEv corresponding to (n) are raised every five clocks with a phase shift of three clocks from each other, so that the five of the color difference data U (n) and V (n) are raised.
/ 6 is not written in the line memory 32. At this time, one clock cycle corresponds to the digital signal processing circuit 31.
And coincides with the cycle of the horizontal clock φh of the CCD solid-state imaging device 1. The luminance data Y (n) and the color difference data U (n) and V (n) written in the line memory 32 in this manner are read out at a cycle corresponding to the data transmission speed of the data bus, and 34
Supplied to

The interface control circuit 34 controls the luminance data Y read from the line memory 32 at a predetermined cycle.
(n) and the color difference data U (n) and V (n) are fetched line by line and sent to the data bus of the personal computer. At the same time, it takes in the interrupt signal IT supplied from the first control unit 20 of the camera unit and sends it to the control bus of the personal computer. Further, the interface control circuit 34 fetches the line feed trigger HS from the control bus and supplies it to the first control unit 20 on the camera unit side. This line feed trigger HS is the luminance data Y for one line that has been reduced.
(n) and the chrominance data U (n) and V (n) are transmitted to the personal computer side, and then the luminance data Y (n) and the chrominance data U (n) and V (n) of the next row are transmitted to the personal computer side. It is started when the preparation for capturing is completed. Further, the interface control circuit 34
Captures various commands for determining operating conditions of the first control unit 20 and the second control unit 30 from the control bus and supplies them to the command register 25 of the first control unit 20 and the command register 34 of the second control unit 30. . And
The command register 34 stores various commands supplied from the personal computer, similarly to the command register 25 of the first control unit 20, and determines the processing conditions of the digital signal processing circuit 31 and the write cycle of the line memory 32.

The second control unit 30 is provided on the personal computer side and is connected to the first control unit of the camera unit. In this connection, since the image data D (n) for which analog signal processing has been completed and the timing signal may be transmitted, the luminance data Y (n) and the color difference data U (n), V ( n) (or color component data R (n), G (n),
B (n)) can be reduced in the number of transmission lines as compared with the case of transmitting B (n)).

FIG. 4 shows an image pickup section 1 of the CCD solid-state image pickup device 1.
It is a top view which shows an example of the mosaic type color filter attached to i. The CCD solid-state imaging device 1 is divided into a plurality of segments corresponding to each pixel of the image pickup unit 1i, and each segment includes, for example, Ye (yellow), Cy (cyan),
Each color component of W (white) and G (green) is periodically allocated. Here, the components of W and G are alternately arranged in odd rows, and the components of Ye and Cy are alternately arranged in even rows. Then, the CCD solid-state imaging device 1
In FIG. 5, two pixels adjacent in the vertical direction are mixed at the time of reading, and therefore, as shown in FIG. 5, in the reading of the odd-numbered rows, the image data D representing the respective components of W + Cy and G + Ye are read.
(n) are obtained alternately, and the image data D (n) representing the components of W + Ye and G + Cy are obtained alternately in the reading of the even-numbered rows. When the CCD solid-state imaging device 1 is interlaced, the combination of the pixels to be mixed is shifted by one line between the odd field and the even field as surrounded by a broken line. The color components obtained correspond to each other.

FIG. 7 is a block diagram showing an example of the configuration of the digital signal processing circuit 31. Here, a case corresponding to the mosaic type color filter shown in FIG. 4 is shown. The line memory circuit 41 is composed of three line memories connected in series, and stores three rows of image data D (n) that are continuous in one row and stores three rows of image data D (n) that are continuous.
a, D (n) b and D (n) c are output in parallel. Image data D (n) a, D (n) read from the line memory circuit 41
b and D (n) c respectively correspond to the configuration of the color filter mounted on the CCD 11, and a predetermined color component is continuous.
For example, when the CCD color filter is configured as shown in FIG. 4, as shown in FIG. 7, at the time of reading the odd-numbered rows, the W + Cy component and the G + Ye component are alternately repeated in the image data D (n) b. G + Cy component and W + Ye component are alternately repeated in the image data D (n) a and D (n) c. When reading the even-numbered rows, the arrangement of the color components is switched, and the G + Cy component and W
+ Ye is alternately repeated, and image data D (n) a,
In D (n) c, the component of W + Cy and the component of G + Ye are alternately repeated.

The RGB matrix circuit 42 includes three rows of image data D (n) a input from the line memory circuit 41,
Operation processing such as addition or subtraction is performed on D (n) b and D (n) c, and color component data R (n) corresponding to three primary colors (R: red, G: green, B: blue) G (n) and B (n) are output. That is, based on the image data D (n) a, D (n) b, and D (n) c, an R component is generated from the difference between W + Ye and G + Cy, and a B component is generated from the difference between W + Cy and G + Ye. doing. The G component is generated by subtracting the B component from G + Cy or subtracting the R component from G + Ye. At this time, since the R component and the B component are obtained alternately in the odd rows and the even rows, when one of the R component and the B component is obtained from the image data D (n) b of the row of the target pixel, , The image data D (n) a, D
(n) Interpolation processing is performed using the average value of the other component obtained from c. For example, at the time of reading an odd-numbered row, color component data B (n) representing a B component is generated from the image data D (n) a and D (n) c by the operation of Expression 1, and the image data D (n)
From the a and D (n) c, the color component data R (n) is generated from the R component by the calculation of Expression 2.

B (n) = | D (n) b−D (n + 1) b | (1) = [W + Cy] b− [G + Ye] b = [2B] R (n ) = (| D (n) a−D (n + 1) a | + | D (n) c−D (n + 1) c |) / 2 (2) = ([W + Ye] a- [G + Cy] a + [W + Ye] c- [G + Cy] c) / 2 = [2R] And each of the image data D (n) a, D (n) b, D (n) c And the color component data R (n), B obtained by the calculations of Equations 1 and 2.
(n) and the color component data G representing the G component by the operation of Equation 3
(n) is generated.

G (n) = (D (m) b−R (m) / 2 + D (m ± 1) a + D (m ± 1) c−B (m ± 1)) / 3 (3) = ([G + Ye] b- [R] + [G + Cy] a + [G + Cy] c- [2B]) / 3 = [2G] (m: even number) Also, when reading out even number rows, image data The color component data R (n) representing the R component is generated from D (n) b by the operation of Expression 4, and the color representing the B component is obtained from the image data D (n) a and D (n) c by the operation of Expression 5. Component data B (n) is generated.

R (n) = | D (n) b−D (n + 1) b | (4) = [W + Ye] b− [G + Cy] b = [2R] B (n ) = (| D (n) a−D (n + 1) a | + | D (n) c−D (n + 1) c |) / 2 (5) = [W + Cy] a − [G + Ye] a + [W + Cy] c− [G + Ye] c = [2B] Then, each of the image data D (n) a, D (n) b, D (n) c, Color component data R (n), B obtained by the operation of Equation 5
(n) and the image data G representing the G component by the calculation of Equation 6
(n) is generated.

G (n) = (D (m ± 1) b−B (m ± 1) / 2 + D (m) a + D (m) c−R (m) c) / 3 (6) = ( [G + Cy] b- [B] + [G + Ye] a + [G + Ye] c- [2R]) / 3 = [2G] The color component data R (n), G
If (n) and B (n) are generated, the positions of the centers of gravity represented by the respective data can be matched with each other.

The white balance control circuit 43 multiplies each of the color component data R (n), G (n), and B (n) by a unique gain coefficient to adjust the balance between them, and displays the data on the playback screen. Color reproducibility is improved. That is, in order to prevent the subject's color from being incorrectly reproduced on the playback screen due to changes in the illumination state of the subject or variations in sensitivity for each color component, a white subject is similarly represented white on the playback screen. The gains of the respective color component data R (n), G (n) and B (n) are adjusted as described above. Normally, in this white balance control, each color component data R
Feedback control is performed such that the integrated values of (n), G (n), and B (n) converge to a predetermined value.

The color difference matrix circuit 44 combines the respective color component data R (n), G (n) and B (n) at a ratio of 3: 6: 1,
The composite value is represented by color component data R representing an R component and a B component.
(n) and B (n), respectively, to obtain color difference signals RY,
The color difference data U (n) and V (n) corresponding to BY are generated.
In the color difference matrix circuit 43, the luminance data Y (n) generated by the luminance data generation circuit 45 described later is subtracted from the color component data R (n) and B (n) to obtain color difference data U (n) and V (n).
It is also possible to obtain (n).

The Y matrix circuit 45 outputs the image data D (n) a, D (n) b,
By combining the four color components contained in D (n) c,
Generate the luminance data Y (n). For example, image data D (n) b of the target pixel and image data D (n-1) b and D (n + 1) b before and after the target pixel
Accordingly, the luminance data Y (n) is generated by the calculation of Expression (7).

Y (n) = D (n) b + (D (n−1) b + D (n + 1) b) / 2 (7) = [G + Ye] b + ([W + Cy] b + [W + Cy] b) / 2 = [W + Cy] b + ([G + Ye] b + [G + Ye] b) / 2 = [2R] + [4G] + [2B] That is, Ye, Cy, If the components of G and W are synthesized as they are, Ye + Cy + G + W = (B + G) + (R + G) + G + (R + G + B) = 2R + 4G + 2B, and the luminance in which the components of R, G and B are synthesized at a ratio of 1: 2: 1. A signal can be obtained. Originally, according to the NTSC standard, the luminance signal is generated by combining the R, G, and B components at a ratio of 3: 6: 1, but is synthesized at a ratio close to this. If generated,
There is no practical problem. Further, each image data D (n) a, D (n)
b, D (n) c is subjected to the operation of Expression 7 to generate luminance data Ya (n), Yb (n), Yc (n) corresponding to each row, and the luminance data Y (n) a, By performing the same filtering processing as in the horizontal direction on Y (n) b and Y (n) c, the luminance is set as Y (n) = (Y (n) a + 2Y (n) b + Y (n) c) / 4 The data Y (n) may be obtained.

The aperture circuit 46 generates the luminance data Y (n)
Aperture data is generated by emphasizing a specific frequency component included in the luminance data Y (n).
Is added to. That is, in order to emphasize the outline of the subject image,
A filtering process is performed on the image data D (n) so as to emphasize a frequency component of サ ン プ リ ン グ of the sampling frequency when the image data D (n) is obtained from the image signal Y (t), and aperture data is generated. It is configured as follows. For example, aperture data A (n) is generated by performing arithmetic processing according to Expression 8 on the luminance data Y (n).

A (n) = (Y (n + 2) + 2Y (n) + Y (n−2)) (8) Then, the aperture data A (n) is converted into luminance data Y (n).
To enhance the contour of the subject image. As a result, in the digital signal processing circuit 31,
As shown in FIG. 3, luminance data Y (n) and color difference data U (n), V (n) are generated corresponding to the image data D (n).

In the above embodiment, the case where the CCD solid-state imaging device 1 is of the frame transfer type has been exemplified.
Any system that can hold information charges for a screen in the image sensor (for example, an interline system or a frame interline system) can be similarly employed. The configuration of the color filter is not limited to that shown in FIG.
Mosaic filter or stripe filter of the primary color system composed of each component of the above.

[0034]

According to the present invention, an output frequency of image data can be converted to a frequency corresponding to the transmission speed of a computer by a line memory, and an inexpensive imaging device which can be easily connected to a computer device is provided. Can be provided. Further, the data amount of the luminance data and the color difference data can be compressed by controlling the writing in the line memory, and the transmission efficiency of the image information from the imaging device to the computer device can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an imaging device of the present invention.

FIG. 2 is a timing chart showing the operation of the imaging device of the present invention.

FIG. 3 is a timing chart for explaining the operation of the line memory;

FIG. 4 is a plan view illustrating a configuration of a color filter mounted on the solid-state imaging device.

FIG. 5 is a diagram illustrating an arrangement of color components represented by image data obtained by a solid-state imaging device provided with a color filter.

FIG. 6 is a block diagram illustrating a configuration of a digital signal processing circuit of a second control unit.

FIG. 7 is a diagram showing an array of color components represented by image data.

FIG. 8 is a block diagram illustrating a configuration of a conventional imaging device.

FIG. 9 is a timing chart showing the operation of a conventional imaging device.

FIG. 10 is a block diagram illustrating a configuration of a video capture board.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 CCD solid-state imaging device 1 i imaging unit 1 s storage unit 1 h horizontal transfer unit 1 f output unit 2 driver circuit 2 v vertical clock generation unit 2 s storage clock generation unit 2 h horizontal clock generation unit 2 d discharge clock generation unit 3 timing control circuit 4 signal processing circuit 10 Video capture board 11 A / D conversion circuit 12 Frame memory 13 Synchronous detection circuit 14 Timing control circuit 15 Interface circuit 20 First control unit 21 Analog signal processing circuit 22 A / D conversion circuit 23 Timing control circuit 24 Exposure control circuit 25 Command register Reference Signs List 30 Second control unit 31 Digital signal processing unit 32 Line memory 33 Interface control circuit 34 Command register 41 Line memory circuit 42 RGB matrix circuit 43 White balance control circuit 44 Color difference matrix Circuit 45 Y matrix circuit 46 aperture circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/225 G06T 1/60 H04N 5/335

Claims (3)

(57) [Claims] In an image pickup apparatus for taking an image of a subject and supplying image information to a computer device in one screen unit, a plurality of light receiving pixels are arranged in a matrix, and information charges corresponding to an object image to be illuminated are transferred to each light receiving pixel. , A driver circuit for sequentially transferring and outputting information charges accumulated in each light-receiving pixel of the solid-state imaging device in units of one row to obtain an image signal, a starting timing of vertical scanning of the driver circuit, and A timing control circuit for setting the start timing of horizontal scanning, an analog signal processing circuit for performing analog signal processing on the image signal, and image data obtained by performing analog / digital conversion on the image signal subjected to analog signal processing A / D conversion circuit for generating digital image data, a digital signal processing circuit for performing digital signal processing on the image data, and a digital A line memory circuit for sequentially storing the image data subjected to the digital signal processing on a line-by-row basis, and synchronizing the timing of writing data to the line memory circuit with the signal processing operation of the digital signal processing circuit, and the timing of reading data. An image pickup apparatus comprising: a memory control circuit that sets a desired cycle; and an interface control circuit that sends the image data read from the line memory circuit to a bus line of a computer device. 2. The apparatus according to claim 1, wherein the memory control circuit suspends the writing of the image data to the line memory circuit at regular intervals to reduce a data amount of the image data. Imaging device. 3. The imaging device according to claim 2, wherein the memory control circuit includes a command register for storing a command indicating an interval at which the writing of the image data is suspended.