JP2931531B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device for color image pickup in which digital signal processing is used in the process of processing a video signal.

[0002]

2. Description of the Related Art In an imaging apparatus such as a television camera using a CCD solid-state imaging device, each scanning timing of the solid-state imaging device is set based on a synchronization signal according to a predetermined television system, and has a format corresponding to the system. A video signal is extracted. For example, in the case of the NTSC system, the vertical scanning period is set to 1/60 second, the horizontal scanning period is set to 2/525 of the vertical scanning period, and a video signal in which video information is continuous in one horizontal scanning period is output. Is done.

FIG. 6 shows a frame transfer type CCD.
FIG. 2 is a block diagram illustrating a configuration of an imaging device using a solid-state imaging device. The solid-state imaging device 1 includes an imaging unit 1a that receives information from a subject and generates information charges, a storage unit 1b that temporarily stores information charges, a horizontal transfer unit 1c that transfers and outputs information charges in a horizontal direction, and An output unit 1d converts the information charge amount into a voltage value and outputs the voltage value. Drive clock generation circuit 2
Comprises a frame transfer clock generator 2a, a vertical transfer clock generator 2b, and a horizontal transfer clock generator 2c, each of which operates in response to a timing signal from the timing control circuit 3. Frame transfer clock generator 2
a generates a frame transfer clock φF in synchronization with the vertical scanning timing, supplies the frame transfer clock φF to the imaging unit 1a of the solid-state imaging device 1, and transfers the information charges of the imaging unit 1a for each screen within a vertical scanning retrace period. The data is transferred to the storage unit 1b. The vertical transfer clock generating unit 2b generates a vertical transfer clock φV in synchronization with the horizontal scanning timing, supplies the generated vertical transfer clock φV to the storage unit 1b of the solid-state imaging device 1, and transfers the information charges in the storage unit 1b to the horizontal scanning for each row. The data is transferred to the horizontal transfer unit 1c within the retrace period. The horizontal transfer clock generation unit 2c generates a horizontal transfer clock φH in synchronization with the horizontal scanning timing, supplies the horizontal transfer clock φH to the horizontal transfer unit 1c, and transfers the information charges for one row transferred from the storage unit 1b during the horizontal scan period. To transfer and output to the output unit 1d. The timing control circuit 3 generates a timing signal of a vertical scanning period and a horizontal scanning period based on the reference clock CK, and supplies the timing signal to each unit of the driving clock generation circuit 2. Thereby, the imaging unit 1a
The information charges generated in step (1) are transferred to and stored in the storage section 1b in units of one screen at the timing of the start of the vertical scanning period. Then, the data is transferred from the storage unit 1b to the horizontal transfer unit 1c in units of one row at the timing of the start of the horizontal scanning period,
The data is transferred from the horizontal transfer unit 1c to the output unit 1d one bit at a time.

The reset clock generation circuit 4 generates a reset clock φR in synchronization with the operation of the horizontal transfer clock generation unit 2c, and supplies the reset clock φR to the output unit 1d of the solid-state imaging device 1. The output section 1d is provided with a diffusion region which is electrically independent of another region called a floating diffusion, and the information charges accumulated in this diffusion region are transferred to a charge discharging drain in response to a reset clock φR. Is discharged. That is, since the output unit 1d accumulates information charges transferred from the horizontal transfer unit 1c in the diffusion region and obtains a voltage value from a change in the potential of the diffusion region, the information charges of the horizontal transfer unit 1c are output from the output unit. Each time one bit is transferred to 1d, information charges are discharged in response to the reset clock φR. As a result, the information charge transferred and output from the horizontal transfer unit 1c is converted into a voltage value for each bit, and a video signal Y1 (t) that repeats a reset level and a signal level corresponding to the information charge amount is output.

[0005] The sampling circuit 5 outputs a video signal Y1 (t).
Is sampled at a timing according to the sampling clock φS, and is output as a video signal Y2 (t).
The sampling clock generation circuit 6 generates the sampling clock φS in synchronization with the operation of the horizontal transfer clock generation unit 2c and supplies the same to the sampling circuit 5, similarly to the reset clock generation circuit 4. The phase of the sampling clock φS is adjusted to a period during which a voltage value corresponding to the information charge amount is output from the output unit 1d of the solid-state imaging device 1, and the sampling clock φS is used for the video signal Y1 (t) output from the output unit 1d. Of which
Only the signal level is extracted to generate a video signal Y2 (t).

The video signal Y2 (t) output in this way is
Is sent to a recording medium or a playback monitor after signal processing such as automatic gain control and gamma correction.

[0007]

It is well known to use an image scanner for scanning and reading an original document when image data is taken into a device such as a personal computer or a word processor. It has been considered to use an image sensor that can respond to various subjects. For example, the imaging apparatus as described above is configured to digitally convert the output video signal Y2 (t) to generate video data, and transfer the video data to the device side in units of one screen.

However, on the monitor screen of the computer device, since the positions of the display pixels on the screen are predetermined, the ratio of the arrangement pitch (aspect ratio) of the light receiving pixels of the image pickup unit 1a in the vertical direction and the horizontal direction is determined. Does not match the monitor screen, the image displayed on the monitor screen will be distorted. For example, if the image data generated from the video signal Y2 (t) is displayed on a monitor screen having an aspect ratio of 1: 1 when the aspect ratio of the imaging unit 1a is 4: 3, the horizontal display interval is 3/3. 4, the image of the subject captured by the solid-state imaging device 1 is displayed vertically.

Therefore, it is necessary to convert the spatial frequency of the video signal Y2 (t) so as to correspond to the aspect ratio of the monitor screen. The conversion of the spatial frequency of the video signal Y2 (t) is mainly performed by the video signal Y2 passed through a low-pass filter.
(t) is sampled at a desired frequency by analog signal processing, and digital signal processing of generating intermediate position data by arithmetic processing from video data obtained by digitally converting the video signal Y2 (t). Can be raised.
In the case of the method based on analog signal processing, the configuration of the signal processing circuit is easy and the cost can be reduced. It cannot be adopted because it cannot pass. For example, as shown in FIG. 7, in a video signal Y2 (t) in which two types of color components are alternately repeated with a period corresponding to the horizontal transfer clock φH, the information representing the color components is 1 / の of the frequency of the horizontal transfer clock φH. 2 frequency components,
This information cannot be taken into the sampling circuit through a low-pass filter. On the other hand, in the case of the method based on digital signal processing, a video signal Y indicating a color video is used.
Although it can be adopted for 2 (t), there is a problem that the scale of the signal processing circuit becomes large and the cost is increased.

Accordingly, an object of the present invention is to make it possible to perform a spatial frequency conversion process on a video signal representing a color video by analog signal processing that can be reduced in cost.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized by a plurality of light receiving pixels which generate information charges in response to received light. Are arranged in the row direction and the column direction, and in each row, a first color component is given to odd columns and a second color component is given to even columns. A driving circuit that reads information charges from odd-numbered columns of light receiving pixels of the solid-state imaging device in a first period of the first half of the horizontal scanning period, and reads information charges from even-numbered columns of light receiving pixels in a second period of the second half of the horizontal scanning period A sampling circuit that obtains a video signal by sampling the output of the solid-state imaging device at a period that matches the read period of the information charge; and a low-pass filter that removes high-frequency components of the video signal obtained from the sampling circuit. And an A / D conversion circuit that samples the video signal obtained through the low-pass filter at a cycle longer or shorter than the sampling cycle of the sampling circuit, and digitally converts a sampled value to generate video data. That is.

[0012]

According to the present invention, from a plurality of light receiving pixels in which the first color component and the second color component are respectively associated with the odd columns and the even columns in each row, the light receiving pixels of the odd columns and the even columns are obtained. The information charges are read out at different timings from the light-receiving pixels, so that the information charges representing the same color component become 1
/ 2 lines are output continuously. Therefore,
In the video signal, the same color component is continuous every half of the horizontal scanning period, and the frequency of the information representing the color component becomes low. Therefore, this information is passed through a low-pass filter to an A / D conversion circuit. Can be captured. Then, the spatial frequency of the video signal is arbitrarily converted by variably setting the sampling period of the video signal in the A / D conversion circuit.

[0013]

FIG. 1 is a block diagram showing the configuration of a solid-state imaging device according to the present invention, and FIG. 2 is a timing chart for explaining its operation. The solid-state imaging device 11 includes an imaging unit 11a equipped with a mosaic-type color filter, an imaging unit 11b in which even-numbered vertical shift registers are formed on the output side by one bit more than odd-numbered vertical shift registers, and an imaging unit 11
The horizontal shift register 11c is associated with each bit of the horizontal shift register for every two columns of the vertical shift register b, and the output unit 11d extracts the video signal Y1 (t). The drive clock generation circuit 12 includes a frame transfer clock generation unit 12
a, a vertical transfer clock generator 12b and a horizontal transfer clock generator 12c. The frame transfer clock generation unit 12a supplies the frame transfer clock φF generated in synchronization with the vertical scanning timing to the imaging unit 11a of the solid-state imaging device 11, and stores the information charges of the imaging unit 11a to the storage unit 11b for each screen. Forward. The vertical transfer clock generation unit 12b supplies the vertical transfer clock φV to the storage unit 11b, and stores the information charges transferred from the imaging unit 11a in the storage unit 11b.
b, and the captured information charges are transferred in the vertical direction for each row. At this time, in the accumulation unit 11b, since the vertical shift registers of the even columns are formed one bit more on the output side than the vertical shift registers of the odd columns, the information charges of the last bit are generated in the vertical shift registers of the odd columns. The data is transferred to the horizontal shift register of the horizontal transfer unit 11c, and in the vertical shift registers of the even columns, the information charges of the same row are held in the last bit of the vertical shift register. At the same time, the vertical transfer clock generation unit 12b supplies the auxiliary transfer clock φT to the last bit of the even-numbered column vertical shift register of the storage unit 11b, and converts the information charges captured in the last bit into the odd-numbered column vertical shift register. Is transferred to the horizontal shift register of the horizontal transfer section 11c at a timing delayed by a half of the horizontal scanning period with respect to the transfer timing. The horizontal transfer clock generator 13c supplies the horizontal transfer clock φH generated in synchronization with the horizontal scanning timing to the horizontal transfer unit 11c, and transfers and outputs the information charges transferred from the storage unit 11b to the output unit 11d. The timing control circuit 13 determines the timing of vertical scanning and horizontal scanning based on the reference clock CK, and controls the operation timing of each unit 12a, 12b, 12c of the driving clock generation circuit 12. As a result, information charges generated in the imaging unit 11a are transferred to and accumulated in the storage unit 11b in units of one screen at the start of the vertical scanning period, and one line is output from the storage unit 11b at the start of the horizontal scanning period. The data is transferred to the horizontal transfer unit 11c in units. And
In the transfer process, the information charges read from the odd-numbered columns of light-receiving pixels and the information charges read from the even-numbered columns of light-receiving pixels are separated, and the information charges representing the same color component are divided by 1 / of the horizontal scanning period. The data is continuously transferred to the output unit 11d for every two periods.

The reset clock generating circuit 14 generates a horizontal transfer clock φ in synchronization with the horizontal transfer clock generator 12c.
A reset clock φR having the same cycle as H is generated and supplied to the output unit 11 d of the solid-state imaging device 11. Thereby, the discharging operation of the information charges in the output unit 11d is performed by the horizontal transfer unit 11c.
, The information charge for each pixel is accumulated in the output unit 11d. The sampling circuit 15 takes in the video signal Y1 (t) output from the output unit 11d, samples it at a timing according to the sampling clock φS, and outputs it as a video signal Y2 (t). Similarly to the reset clock generation circuit 14, the sampling clock generation circuit 16 synchronizes with the horizontal transfer clock generation unit 12c to generate a sampling clock φS having the same cycle as the horizontal transfer clock φH.
Is generated and supplied to the sampling circuit 15. The phase of the sampling clock φS is the same as the sampling clock φS of the solid-state imaging device shown in FIG.
It is set so that the signal level of (t) coincides with the output period.

The low-pass filter 17 removes a high-frequency component of the video signal Y2 (t) output from the sampling circuit 15 and supplies it to the A / D conversion circuit 18 as a video signal Y3 (t). The cut-off frequency of the low-pass filter 17 is set to サ ン プ リ ン グ of the sampling clock φC of the A / D conversion circuit 18 described later. In the video signal Y2 (t) output from the sampling circuit 15, since the same color component is continuous every half of the horizontal scanning period,
The information representing the color component does not include the high frequency component, and the information passes through the low-pass filter 17 together with the information representing the luminance component. The A / D conversion circuit 18 includes the low-pass filter 1
The video signal Y3 (t) obtained through the sampler 7 is sampled in response to a sampling clock φC, and the sampled value is sequentially converted to digital to generate video data YD (n). The sampling clock generation circuit 19 generates a sampling clock φC having a predetermined cycle based on a reference clock CK having a fixed cycle, and supplies the generated sampling clock φC to the A / D conversion circuit 18. In this sampling clock generation circuit 19,
The frequency of the sampling clock φC is set according to the spatial frequency required on the side receiving the video data YD (n). That is, by setting the frequency of the sampling clock φC to a value different from the frequency of the horizontal transfer clock φH, the spatial frequency of the video signal Y2 (t) is converted at the sampling stage in the A / D conversion circuit 18. , Video data YD (n) having a desired spatial frequency can be obtained. For example, when the spatial frequency of the video signal Y2 (t) is 2/3, as shown in FIG. 2, the period of the sampling clock φC is set to 3/2 and the video signal Y3 (t) is horizontally transferred. The sampling is performed at a frequency of 2/3 of the clock φH. As a result, the number of video data YD (n) in each horizontal scanning period becomes 2/3 of the number of bits in the horizontal direction,
This means that the spatial frequency has been converted to 2/3.

FIG. 3 is a plan view showing the structure of the solid-state image sensor 11, and FIG. 4 is a timing chart of each clock for driving the solid-state image sensor 11. In this figure, the light receiving pixels of the image pickup unit are shown in 6 rows × 8 columns for simplification of the drawing. The imaging unit 11a includes a plurality of vertical shift registers arranged in parallel with each other, and these vertical shift registers are each divided into a plurality of bits.
A plurality of light receiving pixels arranged in a matrix form. A mosaic type color filter including four color components a, b, c, and d is mounted on the imaging unit 11a. Thereby, in the light receiving pixels of the odd rows, the odd columns are associated with the first color component a, the even columns are associated with the second color component b,
In the light receiving pixels in the even rows, the odd columns are associated with the third color component c, and the even columns are associated with the fourth color component d. A frame transfer clock φF synchronized with the vertical scanning timing is applied to each vertical shift register of the imaging unit 11a, and information charges generated in each light receiving pixel are transferred to the storage unit 11b. The storage unit 11b includes a plurality of vertical shift registers that are continuous with the vertical shift register of the imaging unit 11a. These vertical shift registers are divided so as to correspond to the light receiving pixels of the imaging unit 11a, and are transferred from the imaging unit 11a. The information charge is taken in and temporarily stored. The vertical transfer clock φ is stored in the vertical shift register of the storage section 11b.
When V is applied, the information charges transferred from the vertical shift register of the imaging unit 11a are taken in and accumulated, and the accumulated information charges are vertically transferred in units of one row in synchronization with the horizontal scanning timing. On the output side of these vertical shift registers, one bit is formed in the even-numbered column more than the odd-numbered column, and the last bit of the even-numbered column is driven by the auxiliary transfer clock φT having a period of の of the vertical transfer clock φV. . Thereby, the transfer timing of the information charges from the accumulation unit 11b to the horizontal transfer unit 11c is set to １ ／ of the horizontal scanning period by the vertical shift registers of the odd columns and the vertical shift registers of the even columns.
The period is staggered. The horizontal transfer unit 11c includes one column of horizontal shift registers. The horizontal shift register is divided into a plurality of bits corresponding to every two columns of the vertical shift registers of the storage unit 11b, and each of the vertical shift registers of the storage unit 11b2. The information charge transferred from the device is taken into each bit. A horizontal transfer clock φH synchronized with the horizontal scanning timing is applied to the horizontal shift register of the horizontal transfer unit 11c, and the information charges transferred from the storage unit 11b to the horizontal transfer unit 11c are sequentially shifted in the horizontal direction every 1/2 row. Transfer and output.
The output unit 11d includes a capacitor that receives information charges output from the horizontal shift register of the horizontal transfer unit 11c, an output amplifier that extracts a change in the potential of the capacitors, and a reset transistor that discharges information charges accumulated in the capacitors. . A reset clock φR synchronized with the horizontal transfer clock φH is applied to the output unit 11d.
Information charges output from 1c and stored in the capacity in bit units are sequentially discharged. Thereby, the information charge transferred from the horizontal transfer unit 11c is converted into a voltage value in 1-bit units, and the video signal Y1 (t) corresponding to the information charge amount is converted.
Is output.

The vertical transfer clock φV is composed of, for example, four-phase clocks φV1 to φV4, and transfers information charges in the storage section 11b in the vertical direction by one row at the start of vertical scanning in synchronization with the horizontal synchronization signal HD. . At this time, in the odd-numbered column vertical shift registers, the information charges of the last bit are transferred to the horizontal shift register of the horizontal transfer unit 11c.
In an even column vertical shift register that is one bit larger than an odd column, information charges in the same row are held in the last bit of the vertical shift register. The auxiliary transfer clock φT for driving the last bit of the vertical shift register includes, for example, four-phase clock clocks φT1 to φT4, and together with the vertical transfer clock φV, transfers information charges at the beginning of horizontal scanning to the end of the vertical shift register. After capturing the bits,
When a half of the horizontal scanning period has elapsed, information charges are transferred from the last bit of the vertical shift register to the horizontal shift register of the horizontal transfer unit. The horizontal transfer clock φH is composed of, for example, two-phase clocks φH1 and φH2. Each time information charges are transferred from the vertical shift register of the storage unit 11b to the horizontal shift register of the horizontal transfer unit 11c, 1/1 of the horizontal scan is performed. In a period of 2, information charges for 1/2 row are transferred to the output unit 11d. The information charge transferred and output in this manner is １ ／ of the horizontal scanning period every horizontal scanning period.
, The same color component is continuous. For example, in an odd-numbered horizontal scanning period, the first half of the horizontal scanning period
The information charge representing the color component a of the second color component b is continuously output in the second half, and the information charge representing the second color component b is continuously output in the second half. In the even-numbered horizontal scanning period, the third color component is output in the first half of the horizontal scanning period. c
, And the information charges representing the fourth color component d are output continuously in the latter half. Therefore, in each horizontal scanning period, the video signal Y1 (t) output from the output unit 11d represents a single color component every half of the horizontal scanning period, and information representing the color component is displayed. Does not contain high frequency components.

Incidentally, the configuration for outputting the information charges of the storage section 11b into an odd column and an even column separately is not only that the number of bits of the vertical shift register is increased by one bit in the even column,
A method of controlling the potential of the horizontal transfer unit, a method of providing a transfer control electrode on the output side of the vertical shift register, and the like can be considered.
For example, a pair of transfer control electrodes in which the arrangement order is switched between an odd column and an even column are provided on the output side of the vertical shift register,
The transfer control electrodes may be configured to distribute the information charges in the vertical shift register into odd columns and even columns.

FIG. 5 is a plan view showing a configuration example of a mosaic type color filter mounted on a solid-state image sensor. The color filter includes first to fourth color components a, b, c, and d.
, The first and second elements E1, E2 are arranged alternately in odd columns, and the third and fourth elements are arranged in even columns.
Are alternately arranged. The first element E1 has Cy (cyan) and Ye (yellow) arranged at a ratio of 2: 1. The second element E2 has G
(Green) and Ye are arranged at a ratio of 2: 1. In the third element E3, G and Cy are arranged in a ratio of 2: 1. In the fourth element E4, Ye and Cy are arranged in a ratio of 2: 1. Therefore, the first to fourth color components a, b, c, and d are expressed as follows: a = 2Cy + Yeb = 2G + Yec = 2G + Cyd = 2Ye + Cy. Therefore, the first color component a and the second color component b
By combining these, a + b = (2Cy + Ye) + (2G + Ye) = 2R + 6G + 2B. Similarly, when the third color component c and the fourth color component d are combined, c + d = (2G + Cy) + (2Ye + Cy) = 2R + 6G + 2B = a + b. In these equations, R, G, and B components are synthesized at a ratio of 1: 3: 1, respectively, and represent a luminance signal. Note that this luminance signal does not match the original luminance signal, but there is no practical problem since the components are combined at a rate close to the standard.

The difference between the first color component a and the second color component b is given by: | a−b | = (2Cy + Ye) − (2G + Ye) = 2Cy−2G = 2B Obtainable. Similarly,
Taking the difference between the third color component c and the fourth color component d, | cd | = (2Ye + Cy) − (2G + Cy) = 2Ye−2G = 2R, and the red component R can be obtained.

As described above, the first to fourth elements E1
With regard to to E4, the first to fourth color components a, b, c, and d are realized by dividing each element into 2: 1 and making each divided region correspond to Cy, Ye, and G. be able to. Note that the first to fourth color components a, b, c, and d are not limited to the configuration shown in FIG. 4, and a + b = c + d | a-b | = C1 | cd | = C2 ( C1 and C2 indicate the difference between one component or two components of the three primary colors.) The three primary colors (red: R, green:
G, blue: B) and two to three components of its complementary colors (yellow: Ye, magenta: Mg, cyan: Cy) may be combined at a predetermined ratio.

Incidentally, such color filters are the first to the first.
The fourth elements E1 to E4 need only correspond to the light receiving pixels on a one-to-one basis, and the solid-state imaging device may be any of frame transfer, interline, and frame interline.

[0023]

According to the present invention, a video signal containing information representing a color component can be output through a low-pass filter, and a video signal obtained through the low-pass filter can be output at a desired frequency. The frequency can be easily converted by sampling with the sampling clock. Therefore, the conversion of the spatial frequency of the video signal can be performed with a simple circuit configuration, and the cost of the device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a solid-state imaging device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the solid-state imaging device of the present invention.

FIG. 3 is a plan view illustrating a configuration of a solid-state imaging device used in the solid-state imaging device of the present invention.

FIG. 4 is a timing chart of a clock for driving the solid-state imaging device of FIG. 3;

FIG. 5 is a plan view illustrating a configuration example of a color filter mounted on the solid-state imaging device in FIG. 3;

FIG. 6 is a block diagram illustrating a configuration of a conventional solid-state imaging device.

FIG. 7 is a timing chart for explaining the operation of a conventional solid-state imaging device.

[Explanation of symbols]

 1, 11 solid-state imaging device 1a, 11a imaging unit 1b, 11b storage unit 1c, 11c horizontal transfer unit 1d, 11d output unit 2, 12 drive clock generation circuit 2a frame transfer clock generation unit 2b vertical transfer clock generation unit 2c horizontal transfer clock Generation unit 3, 13 Timing control circuit 4 Reset clock generation circuit 5, 15 Sampling circuit 6, 16 Sampling clock generation circuit 17 Low-pass filter 18 A / D conversion circuit 19 Sampling clock generation circuit

Claims (3)

(57) [Claims] 1. A plurality of light receiving pixels which generate information charges in response to received light are arranged in a row direction and a column direction. In each row, a first color component is given to an odd column and an even column is provided. A solid-state imaging device to which a second color component is applied, and, for each horizontal scanning period, information charges are read from the light receiving pixels of the odd-numbered columns of the solid-state imaging device in a first period of the first half of the horizontal scanning period, and horizontal scanning is performed. A driving circuit for reading out information charges from the light receiving pixels in the even-numbered columns in a second period of the latter half of the period, and a sampling circuit for sampling the output of the solid-state imaging element at a period corresponding to the reading period of the information charges to obtain a video signal A low-pass filter for removing a high-frequency component of a video signal obtained from the sampling circuit; and a sampling circuit for the video signal obtained through the low-pass filter. A solid-state imaging device comprising: an A / D conversion circuit that performs sampling at a cycle longer than a period and converts the sampled value to digital to generate video data. 2. The solid-state imaging device according to claim 1, wherein the A / D conversion circuit samples the video signal obtained through the low-pass filter at a cycle shorter than a sampling cycle of the sampling circuit. 3. The solid-state imaging device according to claim 1, wherein a cut-off frequency of the low-pass filter is set to a half of a sampling frequency of the A / D converter.